liu.seSearch for publications in DiVA
Change search
Refine search result
1 - 9 of 9
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sadeghifar, Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs2011In: Circuit Theory and Design (ECCTD), 2011, IEEE , 2011, p. 274-277Conference paper (Refereed)
    Abstract [en]

    In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.

  • 2.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sadeghifar, Mohammad Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Fredriksson, P.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jansson, C.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Niklaus, F.
    FAUN AB.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low-noise readout circuit in 0.35-μm CMOS for low-cost uncooled FPA infrared network camera2009In: Infrared Technology and Applications XXXV, Proceedings of SPIE - The International Society for Optical Engineering, vol 7298, SPIE - International Society for Optical Engineering, 2009, Vol. 7298, article id 72982FConference paper (Refereed)
    Abstract [en]

    This paper describes a differential readout circuit technique for uncooled Infrared Focal Plane Arrays (IRFPA) sensors. The differential operation allows an efficient rejection of the common-mode noise during the biasing and readout of the detectors. This has been enabled by utilizing a number of blind and thermally-isolated IR bolometers as reference detectors. In addition, a pixel-wise detector calibration capability has been provided in order to allow efficient error corrections using digital signal processing techniques. The readout circuit for a 64×64 test bolometer-array has been designed in a standard 0.35-μm CMOS process. Circuit simulations show that the analog readout at 60 frames/s consumes 30 mW from a 3.3-V supply and results in a noise equivalent temperature difference (NETD) of 125 mK for f/1 infrared optics.

  • 3.
    Sadeghifar, Mohammad Reza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters2014Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.

    In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.

    ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.

    Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line.

    In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

    List of papers
    1. A survey of RF DAC Architectures
    Open this publication in new window or tab >>A survey of RF DAC Architectures
    2010 (English)In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010, 2010Conference paper, Published paper (Other academic)
    Abstract [en]

    A brief overview of different approaches to implement highfrequency,digital-to-analog converters (DACs), sometimes also referredto as radio-frequency DACs (RF DACs) or mixer DACs is given.

    Recently, there has been a fairly increased activity within this research field. RF CMOS processes have matured and enables a higher degree of integration with high-speed digital circuits at a more reasonable cost. Also, lately, some new advances have been reported which addresses the architectural-level design issues. These new advances include, for example, the implementation of high-speed, digital sigma-delta modulators to be used with RF DACs to further enable an increase of the output frequency of the DACs.

    This work presents a small survey on how RF DACs operate and in some sense how they can be implemented. We outline some different architectures and discuss the pros and cons of those. 

    Keywords
    Digital-to-analog converters, high-frequency data converters, mixer DACs, RF DACs, Sigma-Delta.
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-70620 (URN)
    Conference
    The 10th Swedish System-on-Chip Conference, SSOCC 2010, May 3-4 2010, Kolmården
    Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
    2. A higher Nyquist-range DAC employing sinusoidal interpolation
    Open this publication in new window or tab >>A higher Nyquist-range DAC employing sinusoidal interpolation
    2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Other academic)
    Abstract [en]

    This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

    Place, publisher, year, edition, pages
    IEEE, 2010
    Keywords
    Nyquist range DAC;analog interpolation technique;high speed digital-to-analog converter;linear approximation;oscillating signal;sinusoidal interpolation;time domain analysis;upconversion mixer;approximation theory;digital-analogue conversion;interpolation;mixers (circuits);oscillations;time-domain analysis;
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-70625 (URN)10.1109/NORCHIP.2010.5669460 (DOI)978-1-4244-8972-5 (ISBN)
    Conference
    NORCHIP, 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
    Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2019-11-04
    3. Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
    Open this publication in new window or tab >>Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
    2013 (English)In: ISCAS 2013, IEEE , 2013, p. 578-581Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

    Place, publisher, year, edition, pages
    IEEE, 2013
    Series
    IEEE International Symposium on Circuits and Systems. Proceedings, ISSN 0271-4302
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-100896 (URN)10.1109/ISCAS.2013.6571908 (DOI)000332006800142 ()978-1-4673-5760-9 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
    Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2019-11-04Bibliographically approved
    4. A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
    Open this publication in new window or tab >>A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
    2013 (English)In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, p. 641-644Conference paper, Published paper (Refereed)
    Abstract [en]

    A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

    Place, publisher, year, edition, pages
    IEEE, 2013
    Keywords
    Digital-to-analog converter; Mixer DAC; RFDAC; semi-digital FIR filter; SDFIR filter; IQ modulator; digital-RF converters
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-109895 (URN)10.1109/ICECS.2013.6815496 (DOI)000339725900166 ()978-1-4799-2452-3 (ISBN)
    Conference
    2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi
    Available from: 2014-08-28 Created: 2014-08-28 Last updated: 2019-11-04Bibliographically approved
    5. Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
    Open this publication in new window or tab >>Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
    2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, p. 2465-2468Conference paper, Published paper (Refereed)
    Abstract [en]

    An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

    Place, publisher, year, edition, pages
    IEEE, 2014
    Keywords
    Digital-to-analog converter; DAC; oversampled DAC; semi-digital FIR filter; SDFIR filter; digital Sigma Delta modulator; integer optimization
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113793 (URN)10.1109/ISCAS.2014.6865672 (DOI)000346488600616 ()2-s2.0-84907381691 (Scopus ID)978-1-4799-3432-4 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June, Melbourne, Australia.
    Available from: 2015-02-02 Created: 2015-01-30 Last updated: 2019-11-04Bibliographically approved
  • 4.
    Sadeghifar, Mohammad Reza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base-stations that can be vastly deployed. That is, while the electrical specification of a radio base-station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network.

    As the number of antenna elements increases in massive multiple-input multiple-output based radios such as in 5G, designing true multi-band base-station radios, with efficient physical size, power consumption and cost in emerging cellular bands especially in mid-bands (frequencies up to 10~GHz), is becoming a challenge. This demands a hard integration of radio components; particularly the radio's digital application-specific integrated circuits (ASIC) with high-performance energy-efficient multi-band data converters.

    In this dissertation radio frequency digital-to-analog converter (RF DAC) and semi-digital finite-impulse response (FIR) filter digital-to-analog converter has been studied. Different techniques are used in these structures to improve the transmitter's overall performance.

    In the RF DAC part, a radio frequency digital-to-analog converter solution is presented, which is capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture, while fulfills the stringent requirements of cellular network radio base station linearity and bandwidth. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone and hence achieving output frequencies up to the sample rate.

    In the semi-digital FIR part, optimization problem formulation for semi-digital FIR digital-to-analog converter is investigated. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital Sigma-Delta modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in semi-digital FIR DAC optimization problem formulation. It is shown that hardware cost of the semi-digital FIR DAC, can be reduced by introducing flexible coefficient precision in filter optimization while the semi-digital FIR DAC is not over-designed either. Different use cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metric are used in different use cases of the optimization problem formulation and solved to find out the optimum set of analog FIR taps.

    Moreover, a direct digital-to-RF converter (DRFC) is presented in this thesis where a semi-digital FIR topology utilizes voltage-mode RF DAC cells to synthesize spectrally clean signals at RF frequencies. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital Sigma-Delta modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter. The RF output frequencies are synthesized by a configurable voltage-mode RF DAC solution with a high linearity performance.

    A compensation technique to cancel the code-dependent supply current variation in voltage-mode RF DAC for radio frequency direct digital frequency synthesizer is also presented in this dissertation and is studied analytically. The voltage-mode RF DAC and the compensation technique are mathematically modeled and system-level simulation is performed to support the analytical discussion.

    List of papers
    1. A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters
    Open this publication in new window or tab >>A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters
    2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 100, no 3, p. 683-692Article in journal (Refereed) Published
    Abstract [en]

    As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radios digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into todays digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

    Place, publisher, year, edition, pages
    SPRINGER, 2019
    Keywords
    Radio frequency digital-to-analog converter; RF-sampling DAC; RF DAC; Digital transmitter; Digital-to-RF converter; Software-defined radio; Massive MIMO; 5G
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-159856 (URN)10.1007/s10470-019-01497-9 (DOI)000478898400016 ()
    Note

    Funding Agencies|Linkoping University

    Available from: 2019-08-27 Created: 2019-08-27 Last updated: 2019-11-22
    2. Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
    Open this publication in new window or tab >>Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
    2019 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 66, p. 128-134Article in journal (Refereed) Published
    Abstract [en]

    A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital EA modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

    Place, publisher, year, edition, pages
    ELSEVIER SCIENCE BV, 2019
    Keywords
    Direct digital-to-RF converter; DRFC; Semi-digital FIR; RF DAC; Digital sigma delta
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-158579 (URN)10.1016/j.vlsi.2019.02.005 (DOI)000469905300014 ()
    Available from: 2019-07-03 Created: 2019-07-03 Last updated: 2019-11-04
    3. Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics
    Open this publication in new window or tab >>Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics
    2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 99, no 2, p. 287-298Article in journal (Refereed) Published
    Abstract [en]

    Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

    Place, publisher, year, edition, pages
    SPRINGER, 2019
    Keywords
    Semi-digital FIR filter; Optimization of SDFIR DAC; Digital Sigma-delta modulator; Analog FIR
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-158361 (URN)10.1007/s10470-018-1370-7 (DOI)000465849300007 ()
    Available from: 2019-07-02 Created: 2019-07-02 Last updated: 2019-11-05
    4. A higher Nyquist-range DAC employing sinusoidal interpolation
    Open this publication in new window or tab >>A higher Nyquist-range DAC employing sinusoidal interpolation
    2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Other academic)
    Abstract [en]

    This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

    Place, publisher, year, edition, pages
    IEEE, 2010
    Keywords
    Nyquist range DAC;analog interpolation technique;high speed digital-to-analog converter;linear approximation;oscillating signal;sinusoidal interpolation;time domain analysis;upconversion mixer;approximation theory;digital-analogue conversion;interpolation;mixers (circuits);oscillations;time-domain analysis;
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-70625 (URN)10.1109/NORCHIP.2010.5669460 (DOI)978-1-4244-8972-5 (ISBN)
    Conference
    NORCHIP, 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
    Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2019-11-04
    5. A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
    Open this publication in new window or tab >>A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
    2013 (English)In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, p. 641-644Conference paper, Published paper (Refereed)
    Abstract [en]

    A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

    Place, publisher, year, edition, pages
    IEEE, 2013
    Keywords
    Digital-to-analog converter; Mixer DAC; RFDAC; semi-digital FIR filter; SDFIR filter; IQ modulator; digital-RF converters
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-109895 (URN)10.1109/ICECS.2013.6815496 (DOI)000339725900166 ()978-1-4799-2452-3 (ISBN)
    Conference
    2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi
    Available from: 2014-08-28 Created: 2014-08-28 Last updated: 2019-11-04Bibliographically approved
    6. Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
    Open this publication in new window or tab >>Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
    2013 (English)In: ISCAS 2013, IEEE , 2013, p. 578-581Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

    Place, publisher, year, edition, pages
    IEEE, 2013
    Series
    IEEE International Symposium on Circuits and Systems. Proceedings, ISSN 0271-4302
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-100896 (URN)10.1109/ISCAS.2013.6571908 (DOI)000332006800142 ()978-1-4673-5760-9 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
    Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2019-11-04Bibliographically approved
    7. Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
    Open this publication in new window or tab >>Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
    2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, p. 2465-2468Conference paper, Published paper (Refereed)
    Abstract [en]

    An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

    Place, publisher, year, edition, pages
    IEEE, 2014
    Keywords
    Digital-to-analog converter; DAC; oversampled DAC; semi-digital FIR filter; SDFIR filter; digital Sigma Delta modulator; integer optimization
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113793 (URN)10.1109/ISCAS.2014.6865672 (DOI)000346488600616 ()2-s2.0-84907381691 (Scopus ID)978-1-4799-3432-4 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June, Melbourne, Australia.
    Available from: 2015-02-02 Created: 2015-01-30 Last updated: 2019-11-04Bibliographically approved
  • 5.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Afzal, Nadeem
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO2013In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, p. 641-644Conference paper (Refereed)
    Abstract [en]

    A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

  • 6.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A higher Nyquist-range DAC employing sinusoidal interpolation2010In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper (Other academic)
    Abstract [en]

    This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

  • 7.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A survey of RF DAC Architectures2010In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010, 2010Conference paper (Other academic)
    Abstract [en]

    A brief overview of different approaches to implement highfrequency,digital-to-analog converters (DACs), sometimes also referredto as radio-frequency DACs (RF DACs) or mixer DACs is given.

    Recently, there has been a fairly increased activity within this research field. RF CMOS processes have matured and enables a higher degree of integration with high-speed digital circuits at a more reasonable cost. Also, lately, some new advances have been reported which addresses the architectural-level design issues. These new advances include, for example, the implementation of high-speed, digital sigma-delta modulators to be used with RF DACs to further enable an increase of the output frequency of the DACs.

    This work presents a small survey on how RF DACs operate and in some sense how they can be implemented. We outline some different architectures and discuss the pros and cons of those. 

  • 8.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators2013In: ISCAS 2013, IEEE , 2013, p. 578-581Conference paper (Refereed)
    Abstract [en]

    In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

  • 9.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter2014In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, p. 2465-2468Conference paper (Refereed)
    Abstract [en]

    An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

1 - 9 of 9
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf