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  • 1.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems2006In: IEEE NORCHIP,2006, 2006Conference paper (Refereed)
  • 2.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An 8-by-8 Point 2D DCT Processor Based on the GALS Approach2003In: IEEE NorChip Conf.,2003, 2003Conference paper (Refereed)
  • 3.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools2006In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 953-960Article in journal (Other academic)
  • 4.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    GALS Implementation of a 2-D DCT Processor2004In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
  • 5.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    GALS port implementation in FPGA2005In: National Conf. Radio Science RVK,2005, 2005Conference paper (Refereed)
  • 6.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Port controller for GALS with first come first served function2004In: TENCON 2004,2004, 2004Conference paper (Other academic)
  • 7.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Port controllers for a GALS Implementation of a 2-D DCT Processor2004In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004, 2004Conference paper (Other academic)
  • 8.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems2006In: WSEAS Int. Conf. Circuits,2006, 2006Conference paper (Refereed)
  • 9.
    Jalili, Armin
    et al.
    ECE Dept. Isfahan University of Technology, Isfahan, Iran.
    Sayedi, S. M.
    ECE Dept. Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Calibration of high-resolution flash ADCS based on histogram test methods2010In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, p. 114-117Conference paper (Other academic)
    Abstract [en]

    In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

  • 10.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    High-speed lattice wave digital filters for interpolation and decimation1996In: Proc. National Conf. on Radio Science and Communication, RVK'96, 1996, p. 543-547Conference paper (Other academic)
    Abstract [en]

    Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.

  • 11.
    Melander, Johan
    et al.
    n/a.
    Widhe, Torbjörn
    n/a.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    An FFT processor based on the SIC architecture with asynchronous PE1996In: Proc. IEEE 1996 Midwest Symp. on Circuits and Systems, MWSCAS'96, 1996, p. III-1313-III-1316Conference paper (Refereed)
    Abstract [en]

    A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.

  • 12.
    Melander, Johan
    et al.
    n/a.
    Widhe, Torbjörn
    n/a.
    Sandberg, Peter
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of a bit-serial FFT processor with a hierarchical control structure1995In: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95, 1995, p. I-423-I-426Conference paper (Refereed)
    Abstract [en]

    A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high  performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a  hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented  as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.

  • 13.
    Nilsson, Peter
    et al.
    Dept. of Applied Electronics, University of Lund.
    Torkelsson, Mats
    Dept. of Applied Electronics, University of Lund.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock1994In: Mobile Communications Advanced Systems and Components / [ed] Christoph G. Günther, Berlin ; New York: Springer-Vlg, cop. , 1994, p. 510-521Chapter in book (Other academic)
    Abstract [en]

    A chip for digital intermediate frequency filtering is introduced. The filter is intended move most of the analog intermediate frequency filtering to the digital domain in systems like the American mobile radio system (IS-54). It is a wave digital lattice filter realized with bit-serial arithmetic. Furthermore, a technique for local clocks on chip is presented. The method is based on a ring oscillator and a cycle counter which is controlled from outside the chip. A 0.8 micron technology custom test chip has been fabricated and tested.

  • 14.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Digital IF filter for mobile radio1995In: Proc. Nordic Radio Symposium, NRS'95, 1995, p. 271-276Conference paper (Other academic)
    Abstract [en]

    A multirate IF filter for mobile radio has been implemented in silicon. The filter consists of a decimation stage followed by a bandpass filter. Both parts use a lattice wave digital structure. The design and implementation are described beginning with the filter specification and proceed through algorithmic design, operations scheduling, and resource allocation and assignment. Every step tries to minimize the amount of resources in the final implementation, thereby reducing power consumption. Finally the architecture is selected and the system is described using synthesizable VHDL in order to arrive at a chip layout using standard-cell technology. This design technique is used to reduce the design work.

  • 15.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and implementation of an interpolator using wave digital filters1993In: Proc. National Conf. on Radio Science, RVK'93, 1993, p. 205-208Conference paper (Other academic)
    Abstract [en]

    The design and implementation of an interpolator using wave digital filters is presented. The interpolator increases the sample frequency with a factor of 4, from 800 kHz to 3.2 MHz. The design approach yields implementations with low power consumption and small chip area. The excellent stability and sensitivity properties of wave digital filters are retained.

  • 16.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Nordhamn, Erik
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A fast bit-serial lattice wave digital filter1992In: Proc. NUTEK Workshop on Digital Communications, 1992, p. 88-92Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss the implementation of maximally fast fixed-function digital filters. We demonstrate by means of an example that digital filters with sampling frequencies of more than hundred MHz can efficiently be implemented by using bit-serial PEs. The proposed approach lead to maximally fast filters that require little chip area and have low power consumption. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying equivalence transformations to the signal-flow graph.

  • 17.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Scheduling of data-independent recursive algorithms1995In: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95, 1995, p. II-855-II-858Conference paper (Refereed)
    Abstract [en]

    A new scheduling formulation for data independent recursive algorithms is proposed. This formulation is intuitive and finds a static rate optimal schedules. Processing elements may be non-preemptive and non-homogenous. Comparison with some other common scheduling methods to increase throughput is made.

  • 18.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Arithmetic transformations for fast bit-serial VLSI implementations of recursive algorithms1996In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, p. 391-394Conference paper (Refereed)
    Abstract [en]

    A method to increase the throughput of static recursive algorithms is presented. The signal-flow graph is transformed by first minimizing the number of summation points in the computational loops. A second transformation to rewrite the fixed coefficient multiplications as a sum of weighted signals is then followed by a reordering of the summations. It is how a sum of products can be implemented in this way. Sharing of sub-expressions are also discussed. A bit-serial implementation of a third order bireciprocal lattice WDF is used to illustrate the transformations and sharing of sub-expressions.

  • 19.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of static DSP algorithms using multiplexed PEs1996In: Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'96, 1996, p. 824-827Conference paper (Refereed)
    Abstract [en]

    An efficient and flexible ASIC implementation method suited for static DSP algorithms is presented. It is aimed at low power implementations with moderate speed requirements. The method allows for the processing elements to be multiplexed in order to reduce the amount of resources required. A method to find a minimal number of resources and a corresponding architecture from the cyclic scheduling formulation is described. An implementation of a wave digital bandpass filter is used as an example. The low power consumption and high resource utilization is obtained by using the cyclic scheduling formulation that leads to a maximally fast implementation. The excess speed can be converted to low power consumption by reducing the power supply voltage.

  • 20.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of narrow-band lattice wave digital filters1998In: Proc. 1998 IEEE Nordic Signal Processing Symp., NORSIG'98, 1998, p. 153-156Conference paper (Refereed)
    Abstract [en]

    Recently, a filter structure for narrow-band filtering based on lattice wave digital filters was introduced. The structure has increased parallelism over the corresponding direct realization. In this paper, hardware implementation of the filter structure is discussed. The suggested approach uses bit-serial processing elements that are scheduled so that a maximally fast implementation is achieved. An example is given where our implementation approach increases the sample frequency by a factor of 4 compared to a direct realization.

  • 21.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of fast bit-serial lattice wave digital filters1994In: Proc. 1994 IEEE Int. Symp. on Circuits and Systems, ISCAS'94, 1994, p. II-113-II-116Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss the design and implementation of fixed-function wave digital lattice filters. We demonstrate by means of an example that a sampling frequency of more than 130 MHz can be achieved by using bit-serial arithmetic. The proposed approach leads to very fast filters with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. (1981) often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of filters.

  • 22.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of fast DSP algorithms using bit-serial arithmetic1994In: National Conf. on Electronic Design Automation, EDA-meeting'94, 1994Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. The proposed approach leads to very fast recursive algorithms with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of DSP algorithms.

  • 23.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A CAD tool for synthesis of maximally fast lattice wave digital filters1999In: Proc. National Conf. on Radio Science and Communication, RVK'99, 1999, p. 456-460Conference paper (Other academic)
    Abstract [en]

    A synthesis tool has been developed that implements the scheduling and the hardware mapping of maximally fast, bit-serial lattice wave digital filters. Such implementa­tions are of interest for use in high-speed applications or in low-power applications after supply voltage scaling. The tool generates a synthesizable VHDL hardware netlist from a set of coefficients describing the filter. The VHDL netlist is further mapped to an ASIC using tools from Mentor Graphics. Currently the tool is capable of synthesizing two lattice wave digital filter structures as well as optimizing the structure for cases like the birecip­rocal form of the filter.

  • 24.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A comparison of three lattice wave digital filter implementations1996In: Proc. Int. Conf. on Signal Processing Applications & Technology, ICSPAT'96, 1996, p. II-1909-II-1913Conference paper (Refereed)
    Abstract [en]

    An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.

  • 25.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    High-speed multiplication in bit-serial digital filters1996In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, p. 179-182Conference paper (Refereed)
    Abstract [en]

    Canonic signed-digit code representation of multiplier coefficients is often used in digital filters to reduce the required amount of hardware resources. Another approach taken in this paper is to use canonic signed-digit coded coefficients to increase the throughput of the multiplier. We show how the suggested approach applies to serial/parallel multipliers with fixed coefficients. A max¬imally fast implementation of a digital filter is further used as an example to demonstrate the use of the multi¬pliers in recursive digital filters. The resulting bit-serial filters yield a throughput comparable to bit-parallel implemen¬tations, while using only a fractional amount of hardware resources. The filters can be used directly in high-speed applications or in low-power applications after supply voltage scaling.

  • 26.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Maximally fast, bit-serial lattice wave digital filters1996In: Proc. IEEE Digital Signal Processing Workshop, DSPWS'96, 1996, p. 207-210Conference paper (Refereed)
    Abstract [en]

    An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.

  • 27.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On implementation of fast, bit-serial loops1996In: Proc. IEEE 39th Midwest Symp. Circuits and Systems, MWSCAS'96, 1996, p. I-190-I-193Conference paper (Refereed)
    Abstract [en]

    In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier.

  • 28.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Serial squarers and serial/serial multipliers1996In: Proc. National Conf. on Radio Science and Communication, RVK'96, 1996, p. 518-522Conference paper (Other academic)
    Abstract [en]

    Algorithms for full-precision computation of squares and products are derived. The algorithms yield minimum bit-serial latency. We present logic realizations for the algorithms based on shift accumulators. The realizations have been partitioned into regular bit-slices suitable for hardware implementation.

  • 29.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sign-extension and quantization in bit-serial digital filters1996In: Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'96, 1996, p. 394-397Conference paper (Refereed)
    Abstract [en]

    A method for handling overflow and quantization in recursive digital filters is described. The method merges the sign-extension required for a serial/parallel multiplier with the required truncation in the bit-serial loops. The method works with maximally fast implementations, i.e., implementations for which the minimum sample period is used as sample period. The method is first described using a first-order recursive filter, and then applied to a third-order bireciprocal lattice wave digital filter.

  • 30.
    Zhuang, Shengxian
    et al.
    Sch. of Electr. Eng. Southwest Jiaotong Univ..
    Carlsson, Jonas
    Linköping University, Department of Electrical Engineering.
    Li, Weidong
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    GALS based approach to the implementation of the DWT filter bank2004In: International Conference on Signal Processing,2004, Beijing: Publishing House of Electronics Industry , 2004, p. 567-Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

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