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  • 1.
    Edman, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Björklid, Anders
    Saab Dynamics.
    Söderquist, Ingemar
    Saab Dynamics.
    A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters1998Inngår i: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers, 1998, s. 54-55Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

  • 2.
    Edman, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Christensen, J
    Emrich, A.
    Svensson, Christer
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.2001Inngår i: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, s. 258-265Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

  • 3.
    Edman, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Svensson, Christer
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Timing closure through a globally synchronous, timing partitioned design methodology.2004Inngår i: DAC,2004, New York: ACM, Inc. , 2004, s. 71-Konferansepaper (Fagfellevurdert)
  • 4.
    Edman, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Synchronous Latency-Insensitive Design for Multiple Clock Domain2005Inngår i: Proceedings of the IEEE International System-on-Chip Conference (SoCC), IEEE Explore , 2005, s. 83-86Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.

  • 5.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Edman, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Bit memory instructions for a general CPU2004Inngår i: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, s. 215-218Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

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