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  • 1.
    Eriksson, Henrik
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Larsson-Edefors, Per
    Chalmers.
    Full-custom vs standard-cell based design - An adder comparison.2002Inngår i: Swedish System-on-Chip conference.,2002, 2002Konferansepaper (Annet vitenskapelig)
  • 2.
    Eriksson, Henrik
    et al.
    Dept of Computer Engineering Chalmers tekniska högskola.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Larsson-Edefors, Per
    Dept of Computer Engineering Chalmers tekniska högskola.
    Svensson, Christer
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study2003Inngår i: Asia South Pacific Design Automation Conference,2003, 2003, s. 507-Konferansepaper (Fagfellevurdert)
  • 3.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Hardware Architecture for Protocol Processing2001Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.

    There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.

    I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.

    Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.

    Delarbeid
    1. Configurable Port Processor Increases Flexibility in the Protocol Processing Area
    Åpne denne publikasjonen i ny fane eller vindu >>Configurable Port Processor Increases Flexibility in the Protocol Processing Area
    2000 (engelsk)Inngår i: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, s. 275-Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

    (...)

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100437 (URN)
    Konferanse
    COOLChips III An International Symposium on Low-Power and High-Speed Chips. Kikai-Shinko-Kaikan, Tokyo, Japan. April 24-25. 2000
    Tilgjengelig fra: 2013-11-07 Laget: 2013-11-07 Sist oppdatert: 2013-11-07
    2. Specification of a configurable general-purpose protocol processor
    Åpne denne publikasjonen i ny fane eller vindu >>Specification of a configurable general-purpose protocol processor
    2000 (engelsk)Inngår i: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, s. 284-289Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100439 (URN)
    Konferanse
    Second International Symposium on Communication Systems, Networks and Digital Signal Processing. Bournemouth, UK. July 19-20. 2000
    Tilgjengelig fra: 2013-11-07 Laget: 2013-11-07 Sist oppdatert: 2013-11-07
    3. VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
    Åpne denne publikasjonen i ny fane eller vindu >>VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
    Vise andre…
    2001 (engelsk)Inngår i: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, s. 1215-1218Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33606 (URN)10.1109/ICECS.2001.957433 (DOI)19640 (Lokal ID)19640 (Arkivnummer)19640 (OAI)
    Konferanse
    The 8th IEEE Internationa Conference on Electronics, Circuits and Systems, Malta, September 2-5, 2001
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-07
    4. Specification of a configurable general-purpose protocol processor
    Åpne denne publikasjonen i ny fane eller vindu >>Specification of a configurable general-purpose protocol processor
    2002 (engelsk)Inngår i: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, nr 3, s. 198-202Artikkel i tidsskrift (Fagfellevurdert) Published
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33567 (URN)10.1049/ip-cds:20020443 (DOI)19599 (Lokal ID)19599 (Arkivnummer)19599 (OAI)
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2017-12-13
  • 4.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    In-Line CRC Calculation and Scheduling for 10 Gigabit Ethernet Transmission2002Inngår i: Swedish System-on-Chip Conference,2002, 2002Konferansepaper (Annet vitenskapelig)
  • 5.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Intra-packet data-flow protocol processor2003Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Protocol processing is the bottleneck in high-speed computer networks. Many network processors have been suggested for switches and routers. Protocol processing in terminals has other characteristics than the processing in switches and routers. Therefore a new type of processor is desirable for terminals.

    I define that the protocol processing tasks in a terminal can be partitioned into intra-packet tasks and inter-packet tasks. It is suitable to use two processors that work in a coarse-grained pipeline to implement this partition. The partition crosses over the protocol layers, which have previously been used for partitioning the protocol processing implementations.

    The inter-packet tasks are irregular and can be efficiently executed by a traditional von Neuman style processor. The intra-packet tasks can be sub-partitioned into regular tasks and irregular tasks. A novel processor architecture for intra-packet tasks has been developed that makes use of the sub-partitioning by executing the regular tasks in accelerator units and the irregular tasks in a data-flow core unit.

    Our core architecture is different from traditional processors because it does not operate on data stored in a memory. Instead it operates in a data-flow fashion directly on the data that is received on the network interface. Thereby no load and store operations are necessary. So the packets are already processed to a large extent when the payload is written into memory. This saves both data memory bandwidth, program memory size, processing time and power consumption. Most of the packets that should be discarded never have to be stored in memory at all.

    The data-flow processing also creates some problems since the program flow has to be perfectly synchronized with the incoming data stream, which prevents the use of a pipelined processor architecture. The performance requirements are fulfilled by splitting up the program into three parts and by using a dedicated program memory storage architecture. A standard cell implementation of the processor indicates support of a data flow of more than 10 Gigabit/s. The implementation can be used for network terminals as well as for port acceleration in switches and routers.

    The total silicon area of the processor including the program memory is small (0.4 mm2 in 0.18 micron standard cells) and accommodates for an increased number of ports on a real time Ethernet switching chip or the integration of the protocol processing off-loading onto the host processor chip in terminal equipment such as desktop computers.

    The accelerator for cyclic redundancy check (CRC) has been implemented with standard cells and manufactured in a 0.35 micron process technology. The chip has measured performance of more than 5.76 Gb/s.

    The most significant contribution of my research is the new data-flow processor architecture, which has been proven in a fully functional demonstrator system. The demonstrator system is based on my novel partition of protocol processing tasks into intra-packet tasks and inter-packet tasks. A dual processor architecture, implemented in an FPGA, receives, synchronizes and plays back an audio stream which is sent in UDP/IP packets over fast Ethemet.

    The processor architecture will be very important for any processor operating on a data flow. There are possible improvements to the processor, for example a detailed analysis between data width and flexibility will support trading off the internal width and program memory size. Future work also includes investigating in what other areas, besides networks, the processor architecture can be successfully used.

    My most important contributions are:

    • The partition of protocol processing

    • The data-flow processor architecture

  • 6.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Eriksson, Henrik
    Computer Engineering Chalmers tekniska högskola.
    Larsson-Edefors, Per
    Computer Engineering Chalmers tekniska högskola.
    Full Custom vs. Standard Cell Based Design - an Adder Comparison2002Inngår i: Swedish System-on-Chip Conference,2002, 2002Konferansepaper (Annet vitenskapelig)
  • 7.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Eriksson, Henrik
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Larsson-Edefors, Per
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    VLSI Implementation of CRC-32 for 10 Gigabit Ethernet2001Inngår i: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, s. 1215-1218Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

  • 8.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implementation of Fast CRC Calculation2003Inngår i: Asia South Pacific Design Automation Conference,2003, 2003, s. 563-Konferansepaper (Fagfellevurdert)
  • 9.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Novel ASIP and Processor Architecture for Packet Decoding2002Inngår i: Workshop of Application Specific Processors Digest,2002, 2002, s. 25-Konferansepaper (Fagfellevurdert)
  • 10.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Configurable Port Processor Increases Flexibility in the Protocol Processing Area2000Inngår i: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, s. 275-Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

    (...)

  • 11.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nordqvist, Ulf
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Embedded Protocol Processor for Fast and Efficient Packet Reception2002Inngår i: International Conference on Computer Design,2002, 2002, s. 414-Konferansepaper (Fagfellevurdert)
  • 12.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Specification of a configurable general-purpose protocol processor2000Inngår i: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, s. 284-289Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

  • 13.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Specification of a configurable general-purpose protocol processor2002Inngår i: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, nr 3, s. 198-202Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

  • 14.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Persson, Niclas
    Linköpings universitet, Institutionen för systemteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    VLSI Implementation of Internet Checksum Calculation for 10 gigabit Ethernet2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 114-Konferansepaper (Fagfellevurdert)
  • 15.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Pettersson, Magnus
    Gustafsson, Fredrik
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska högskolan.
    An Investigation of the Longitudinal Dynamics of a Car, especially Air Drag and Rolling Resistance1993Rapport (Annet vitenskapelig)
  • 16.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Verbauwhede, Ingrid
    EE Dept UCLA.
    Fast IP address lookup engine for SoC integration2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 200-Konferansepaper (Fagfellevurdert)
  • 17.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    VLSI implementation of a switch for on-chip networks2003Inngår i: Int workshop on Design and diagnostics of electronic circuits and systems DDECS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 18.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Configurable CRC Generator2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 192-Konferansepaper (Fagfellevurdert)
  • 19.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    CRC generation for protocol processing2000Inngår i: Proceedings of NORCHIP 2000, 2000, s. 288-293Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

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