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  • 1.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems, Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 29-32Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 2.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS2010In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

  • 3.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators2012Manuscript (preprint) (Other academic)
    Abstract [en]

    In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback  deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.

  • 4.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sadeghifar, Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs2011In: Circuit Theory and Design (ECCTD), 2011, IEEE , 2011, p. 274-277Conference paper (Refereed)
    Abstract [en]

    In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.

  • 5.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power efficient arrangement of oversampling sigma-delta DAC2012In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.

  • 6.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption2012Manuscript (preprint) (Other academic)
    Abstract [en]

    The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.

    To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.

  • 7.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Low-Complexity LMMSE Based Channel Estimation Algorithm for Multiple Standards in Mobile Terminals2010In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010, 2010Conference paper (Other academic)
    Abstract [en]

    A less complex and generic channel estimation algorithm for long term evolution (LTE) and digital video broadcasting-handheld (DVB-H) downlink standards, is proposed. The technique, here referred to as minimum mean square error sliding window (MSW) technique, obtains less computational complexity than previous mean squared error (MSE) algorithms [3] at the cost of some 0.3 dB less SNR. The computational complexity is decreased by a factor 3 for the LTE 5-MHz downlink case and by 30 for the DVB-H standard case. Simulated results in terms of mean squared error and bit error rates are presented for a quadrature phase-shift keying (QPSK) systems with interleaving and coding of the data. All simulations are done at the behaviolar-level level.

  • 8.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Study of modified noise-shaper architectures for oversampled sigma-delta DACs2010In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper (Other academic)
    Abstract [en]

    In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.

  • 9.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, p. 641-645Article in journal (Refereed)
    Abstract [en]

    In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

  • 10.
    Ahmed Aamir, Syed
    et al.
    University of Bielefeld, Germany .
    Angelov, Pavel
    AnaCatum Design AB, Linkoping, Sweden .
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS2014In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 22, no 4, p. 888-898Article in journal (Refereed)
    Abstract [en]

    This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

  • 11.
    Ahmed Aamir, Syed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob J
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers2013In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, p. 381-384Conference paper (Refereed)
    Abstract [en]

    This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

  • 12.
    Alvbrant, Joakim
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Study and Simulation Example of a Redundant FIR Filter2012In: Proceedings 30th Norchip Conference, IEEE, 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.

  • 13.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oskar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Steady-state cycles in digital oscillators2014Manuscript (preprint) (Other academic)
    Abstract [en]

    Digital recursive oscillators locked in steady-state can be used to generate sinusoids with high spectral purity. The locking occurs when the oscillator returns to a previously visited state and repeats its sequence. In this work we propose a new search algorithm and two new search strategies to find all steady-states for a given oscillator configuration. The improvement in spurious-free dynamic range is between 7 and 40 dB compared to previously reported results. The algorithm is also able to find oscillator sequences for more frequencies than previously reported work. A key part of the method is the reduction of the search space made possible by a proposed extension of existing theory on recursive oscillators. Specific properties of digital oscillators in a steady-state are also discussed. It is shown that the initial states can be used to individually control the phase, amplitude, spectral purity, and also cycle length of the oscillator output.

  • 14.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    Rudberg, Mikael
    Linköping University, Department of Electrical Engineering, Electronics System.
    Improvement of segmented DACs (Swedish pat. 0001917-4)2000Patent (Other (popular science, discussion, etc.))
  • 15.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A comparison of dynamic element matching in DACs1999In: Proceedings '99 : Oslo, Norway, 8-9 November 1999 / [ed] Trond Sæther, 1999, p. 385-390Conference paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some "new" important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

  • 16.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A strategy for implementing dynamic element matching in current-steering DACs2000In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, IEEE , 2000, p. 51-56Conference paper (Other academic)
    Abstract [en]

    Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)

  • 17.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Comparison of Different Dynamic Element Matching Techniques for Wideband CMOS DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some ”new” important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

  • 18.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Spectral shaping of DAC nonlinearity errors through modulation of expected errors2001In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, IEEE , 2001, Vol. 3, p. 417-420Conference paper (Refereed)
    Abstract [en]

    Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included

  • 19.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Characterization of a CMOS current-steering DAC using state-space models2000In: Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, IEEE , 2000, Vol. 2, p. 668-671 vol.2Conference paper (Refereed)
    Abstract [en]

    Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters

  • 20.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    Digital-to-analog converter having error correction (US pat. 6946983)2002Patent (Other (popular science, discussion, etc.))
  • 21.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.

  • 22.
    Angelov, Pavel
    et al.
    AnaCatum Design AB, S-58330 Linkoping, Sweden.
    Ahmed Aamir, Syed
    Heidelberg University, Germany.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 11, p. 860-864Article in journal (Refereed)
    Abstract [en]

    We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.

  • 23.
    Berggren, Magnus
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Simon, Daniel
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Nilsson, D
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Dyreklev, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Norberg, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Nordlinder, S
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Ersman, PA
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Gustafsson, G
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Hederén, J
    DU Radio, Ericsson AB, SE-583 30, Linköping, Sweden..
    Hentzell, H
    Swedish ICT Research, Box 1151, SE-164 26, Kista, Sweden..
    Browsing the Real World using Organic Electronics, Si-Chips, and a Human Touch.2016In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 28, no 10, p. 1911-1916Article in journal (Refereed)
    Abstract [en]

    Organic electronics have been developed according to an orthodox doctrine advocating "all-printed, "all-organic and "ultra-low-cost primarily targeting various e-paper applications. In order to harvest from the great opportunities afforded with organic electronics potentially operating as communication and sensor outposts within existing and future complex communication infrastructures, high-quality computing and communication protocols must be integrated with the organic electronics. Here, we debate and scrutinize the twinning of the signal-processing capability of traditional integrated silicon chips with organic electronics and sensors, and to use our body as a natural local network with our bare hand as the browser of the physical world. The resulting platform provides a body network, i.e., a personalized web, composed of e-label sensors, bioelectronics, and mobile devices that together make it possible to monitor and record both our ambience and health-status parameters, supported by the ubiquitous mobile network and the resources of the "cloud".

  • 24.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 25.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunicationapplications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigmadeltamodulators are needed to meet the dynamic performance requirements. This paper presents an oversamplingDAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the highorderone-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limitcycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. Fromour analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator havenon-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients isprovided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented ina 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 26.
    Gustavsson, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Tan, Nianxiong
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    CMOS Data Converters for Communications2000Book (Other academic)
    Abstract [en]

    CMOS Data Converters for Communications distinguishes  itself from other data converter books by emphasizing system-related  aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given  communication system (baseband, passband, and multi-carrier systems).  The authors also review CMOS data converter architectures and discuss  their suitability for communications.

    The rest of the book is  dedicated to high-performance CMOS data converter architecture and  circuit design. Pipelined ADCs, parallel ADCs with an improved passive  sampling technique, and oversampling ADCs are the focus for ADC  architectures, while current-steering DAC modeling and implementation  are the focus for DAC architectures. The principles of the  switched-current and the switched-capacitor techniques are reviewed  and their applications to crucial functional blocks such as  multiplying DACs and integrators are detailed.

    The book outlines the  design of the basic building blocks such as operational amplifiers,  comparators, and reference generators with emphasis on the practical  aspects. To operate analog circuits at a reduced supply voltage,  special circuit techniques are needed. Low-voltage techniques are also  discussed in this book.

    CMOS Data Converters for Communications can be used as a  reference book by analog circuit designers to understand the data  converter requirements for communication applications. It can also be  used by telecommunication system designers to understand the  difficulties of certain performance requirements on data converters.  It is also an excellent resource to prepare analog students for the  new challenges ahead.

  • 27.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Kazim, Muhammad Irfan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    An Analog Receiver Front-End for Capacitive Body-Coupled Communication2012In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper (Other academic)
    Abstract [en]

    This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

  • 28.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Pillai, Anu Kalidas Muralidharan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob J
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Study on Switched-Capacitor Blocks for Reconfigurable ADCs2011In: Electronics, Circuits and Systems (ICECS), 2011, 2011, p. 649-652Conference paper (Refereed)
    Abstract [en]

    Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.sigma-delta ADCs

  • 29.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 28-38Article in journal (Refereed)
    Abstract [en]

    This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

  • 30.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS2015In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, p. 249-252Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

  • 31.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump2014In: NORCHIP 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.

  • 32.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 33.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications2015In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 13-16Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

  • 34.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias2015In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

  • 35.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Dehghani, Rasoul
    Isfahan University of Technology, Iran.
    Jalili, Armin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor2015In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 236, p. 82-91Article in journal (Refereed)
    Abstract [en]

    This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 x 16 DPS with pixel size of 23 x 23 mu m(2) and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. (C) 2015 Elsevier B.V. All rights reserved.

  • 36.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit2016In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 244, p. 243-251Article in journal (Refereed)
    Abstract [en]

    A high-speed and compact in-pixel light-to-time converter (LTC), with low power consumption and wide dynamic range is presented. By using the proposed LTC, a digital pixel sensor (DPS) based on a pulse width modulation (PWM) scheme has been designed and fabricated in a standard 180-nm, single-poly, six-metal complementary metal oxide semiconductor (CMOS) technology. The prototype chip consists of a 16 x 16 pixel array with an individual pixel size of 21 x 21 mu m(2) and a fill factor of 39% in the 180-nm CMOS technology. Experimental results show that the circuit operates at supply voltages down to 800 mV and achieves an overall dynamic range of more than 140 dB. The power consumption at 800 mV supply and room light intensity is approximately 2.85 nW. (C) 2016 Elsevier B.V. All rights reserved.

  • 37.
    Jalili, Armin
    et al.
    ECE Department, Isfahan University of Technology, Isfahan, Iran.
    Sayedi, S. M.
    ECE Department, Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Calibration of sigma-delta analog-to-digital converters based on histogram test methods2010In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.

  • 38.
    Jalili, Armin
    et al.
    ECE Dept. Isfahan University of Technology, Isfahan, Iran.
    Sayedi, S. M.
    ECE Dept. Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Calibration of high-resolution flash ADCS based on histogram test methods2010In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, p. 114-117Conference paper (Other academic)
    Abstract [en]

    In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

  • 39.
    Jalili, Armin
    et al.
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Sayedi, S. M.
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Zeidaabadi Nezhad, Abolghasem
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    A nonlinearity error calibration technique for pipelined ADCs2011In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 44, no 3, p. 229-241Article in journal (Refereed)
    Abstract [en]

    This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

  • 40.
    Jalili, Armin
    et al.
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Sayedi, Sayed Masoud
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs2011In: Microelectronics Journal, ISSN 0959-8324, Vol. 42, no 1, p. 158-164Article in journal (Refereed)
    Abstract [en]

    This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18‐μm CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels.

    Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.

  • 41.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering. Department of Electrical Engineering, Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.
    Cunha, Bernardo
    IEETA Institute of electronics and informatics engineering, University of Aveiro, Protugal.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Martins, Rui
    IEETA Institute of electronics and informatics engineering, University of Aveiro, Protugal.
    Capacitive Body Coupled Communication: A Step Towards Reliable Short Range Wireless Technology2015Manuscript (preprint) (Other academic)
    Abstract [en]

    The paradigm of computation is currently changing from desktop computing towards ubiquitous computing by interfacing ambulatory devices with mobile phones/platforms. For an efficient implementation, ultra short range wireless network technologies, such as the body area network (BAN), are needed which could avoid the saturation of carrier frequencies, low power dissipation, and the electromagnetic interference. In this work, body coupled communication (BCC) based on capacitive reactive field has been  outlined as an important extension of BAN. It has been experimentally demonstrated as an alternative to traditional short range wireless communication based on radio frequency (RF) technologies. The concept of signal transmission through the capacitive BCC channel is explained using a lumped circuit model which is further supported by electromagnetic (EM) simulations. There are three different communication architectures which have been experimentally demonstrated using discrete electronic components for capacitive BCC channel for data rates between 1 kbps to 100 kbps. The architectures are based on digital baseband communication and passband communication with LC resonant mode driver. The best architecture is based on passband communication which has been demonstrated for reliable ECG measurement in the context of preventive healthcare.

  • 42.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Kazim, Muhammad Imran
    Department of Electrical Engineering, Eindhoven University of Technology (TU/e), P.O. Box 513, 5600 MB Eindhoven, The Netherlands.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An Efficient Full-Wave Electromagnetic Analysis for Capacitive Body-Coupled Communication2015In: International Journal of Antennas and Propagation, ISSN 1687-5869, E-ISSN 1687-5877, Vol. 2015, p. 15-, article id 245621Article in journal (Refereed)
    Abstract [en]

    Measured propagation loss for capacitive body-coupled communication (BCC) channel (1 MHz to 60 MHz) is limitedly available in the literature for distances longer than 50 cm. This is either because of experimental complexity to isolate the earth-ground or design complexity in realizing a reliable communication link to assess the performance limitations of capacitive BCC channel. Therefore, an alternate efficient full-wave electromagnetic (EM) simulation approach is presented to realistically analyze capacitive BCC, that is, the interaction of capacitive coupler, the human body, and the environment all together. The presented simulation approach is first evaluated for numerical/human body variation uncertainties and then validated with measurement results from literature, followed by the analysis of capacitive BCC channel for twenty different scenarios. The simulation results show that the vertical coupler configuration is less susceptible to physiological variations of underlying tissues compared to the horizontal coupler configuration. The propagation loss is less for arm positions when they are not touching the torso region irrespective of the communication distance. The propagation loss has also been explained for complex scenarios formed by the ground-plane and the material structures (metals or dielectrics) with the human body. The estimated propagation loss has been used to investigate the link-budget requirement for designing capacitive BCC system in CMOS sub-micron technologies.

  • 43.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Department of Electrical Engineering, Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.
    Kazim, Muhammad Imran
    Department of Electrical Engineering, Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Complex path impedance estimation and matching requirements for body-coupled communication2015In: Circuit Theory and Design (ECCTD), 2015 European Conference on, IEEE , 2015, p. 424-427Conference paper (Refereed)
    Abstract [en]

    Capacitive body coupled communication (BCC) channel has been modeled as a two-port complex path impedance matrix [Z] which varies as a function of ten different body positions over the frequency range of 1 MHz to 60 MHz. A systematic numerical simulation methodology has been used to estimate [Z] parameters. The estimated complex path impedance [Z] is a symmetric matrix showing BCC channel is a reciprocal network of passive components for given coupler configuration, body positions and frequency range. The estimated complex path impedance has been utilized to determine either input impedance Zin or output impedance Zout to conjugately match to Zs at transmitter or Zl at receiver, respectively for maximum power transfer. It has been found that the resistive matching below 1000 O and inductive matching between 0.5 ï¿œH to 5 ï¿œH on any side of the two ports can meet the conjugate matching requirements for maximum power transfer for the given body positions and frequency range.

  • 44.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Kazim, Muhammad Imran
    Department of Electrical Engineering, Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Realistic path loss estimation for capacitive body-coupled communication2015In: Circuit Theory and Design (ECCTD), 2015 European Conference on, IEEE , 2015, p. 173-176Conference paper (Refereed)
    Abstract [en]

    Realistic estimation of path loss is vital for designing an effective capacitive body-coupled communication system. The estimation based on simplified analytical models, however, results in errors as they do not model capacitive couplers accurately and different body positions. The proposed efficient full-wave electromagnetic (EM) model takes into account the effect of capacitive coupler, electro-physiological properties of tissues in human body, different body positions and environment all together to realistically predict the path loss. A comparison of both approaches is made in this paper, showing the superior performance of the proposed model.

  • 45.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a Sub-mW Front-End Amplifier for Capacitive BCC Receiver in 65 nm CMOS2016In: Proceedings of 2016 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 607-610Conference paper (Refereed)
    Abstract [en]

    A low power front-end fully differential operational transconductance amplifier (OTA) has been designed in 65 nm CMOS technology which is suitable to receive low data rates upto 300 kbps for capacitive body coupled communication (BCC) channel. The current shunt current mirror OTA topology has been utilized in open loop configuration in the context of digital baseband architecture on the receiver side. The simulated resuts show that OTA achieves unity gain bandwidth (UGBW) of 200 MHz, dc gain of 40 dB, phase margin of 45 degree and rms integrated noise of 130 μV between 10 kHz to 150 MHz for 1.5 pF load capacitance and power consumption of approximately 250 μW. The OTA achieves high CMRR and PSRR (due to positive supply) of more than 120 dB at 100 Hz.

  • 46.
    Kazim, Muhammad Irfan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering. Department of Electrical Engineering, Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Printed Electrodes with Memory Labels Embracing Body Coupled Communication: An Alternate M2M Communication Paradigm for Internet of Things2015Manuscript (preprint) (Other academic)
    Abstract [en]

    A cost-effective concept of silicon-printed hybrid memory label for capacitive body coupled communication (BCC) is discussed in this paperin the context of internet of things (IoT). The strength of a hybrid approach is deliberated after careful review of organic thin film transistors (OTFTs) performance in the existing printed technologies. Further, the performance of battery operated baseband and passband communication architectures have experimentally been demonstrated for an alternate, short range, wireless, machine-to-machine (M2M) communication paradigm for smart phones platform, the capacitive BCC channel. The  operating frequency range is from 100 kHz to 10 MHz for different body positions and printed electrodes configuration/sizes in conjunction with different output drivers. The transmission/reception of signals to the smart phone has been carried out through an SPI and Bluetooth interface to ensure that isolated earth ground conditions were guaranteed for capacitive BCC channel. The BCC passband communication architecture achieves 1 kbps while the digital baseband architecture achieves 100 kbps data rate for 10−2 packet error rate (PER) in the given experimental setup.

  • 47.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems2015In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 308-311Conference paper (Refereed)
    Abstract [en]

    MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

  • 48.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Design considerations for interface circuits to low-voltage piezoelectric energy harvesters2014Conference paper (Refereed)
    Abstract [en]

    In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm2 and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.

  • 49.
    Qazi, Fahad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sundström, Timmy
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ahmad, Shakeel
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A/D Conversion for Software Defined Radio2010In: Proceedings of the GigaHerz Symposium 2010 / [ed] Henrik Sjöland, Lund University, 2010, p. 36-36Conference paper (Other academic)
  • 50.
    Qazi, Fahad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sundström, Timmy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ahmad, Shakeel
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A/D Conversion for Software Defined Radio: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March2010In: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March, Lund: Lund University , 2010, p. 36-Conference paper (Other academic)
12 1 - 50 of 79
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