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  • 1.
    Asani, Golnaz
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Zadegan, Farrokh Ghani
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling with Constraints for IEEE P1687 (poster)2011In: International Test Conference (ITC11), Anaheim, CA, USA, September 18-23, 2011., 2011Conference paper (Refereed)
  • 2.
    Ghani Zadegan, Farrokh
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Semcon AB.
    Carlsson, Gunnar
    Ericsson AB.
    Larsson, Erik
    Lund University, Sweden .
    Access Time Analysis for IEEE P16872012In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 61, no 10, p. 1459-1472Article in journal (Refereed)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.

  • 3.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Zadegan, Farrokh Ghani
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Test scheduling on IJTAG2010In: Nordic Test Forum (NTF 2010), Drammen, Norway., 2010Conference paper (Refereed)
  • 4.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Lund University, Sweden.
    Scenario-Based Network Design for P16872013In: SSoCC'13, 2013Conference paper (Other academic)
    Abstract [en]

    To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead.

  • 5.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Asani, Golnaz
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints2011In: Proceedings of the Asian Test Symposium, IEEE , 2011, p. 525-531Conference paper (Refereed)
    Abstract [en]

    In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

  • 6.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Automated Design for IEEE P16872011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011., 2011Conference paper (Other academic)
  • 7.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Automation for IEEE P16872011In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, p. 1-6Conference paper (Refereed)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

  • 8.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Lund University, Sweden.
    Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P16872012In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 29, no 2, p. 79-88Article in journal (Refereed)
    Abstract [en]

    This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.

  • 9.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Time Analysis for IEEE P16872010In: Proceedings of the Asian Test Symposium, 2010, p. 455-460Conference paper (Refereed)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

  • 10.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    A Study of Instrument Reuse and Retargeting in P16872011In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Modern chips may contain a large number of embedded test, debug, configuration, and monitoring features, called instruments. An instrument and its instrument data, instrument access procedures, may be pre-developed and reused and instruments may be accessed in different ways through the life-time of the chip, which requires retargeting. To address instruments reuse and retargeting, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.

1 - 10 of 10
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  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
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  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
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  • html
  • text
  • asciidoc
  • rtf