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  • 1.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Power Constrained Test Scheduling for 3D Stacked Chips: (poster)2010In: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA., 2010Conference paper (Refereed)
  • 2.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2011In: Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, Washington, DC, USA: IEEE Computer Society , 2011, p. 72-77Conference paper (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.

  • 3.
    Sengupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2012In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 1, p. 121-135Article in journal (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.

  • 4.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for Stacked 3D Chips under Power Constraints2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 5.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of test flow, we present a cost model with the optimal test flow. In the test flow alternatives, we analyse the effect of all possible moments of testing for a 3D TSV-SIC, viz., wafer sort, intermediate test and package test. For the optimal test flow, we have performed experiments with various varying yield and test time parameters, which further support our claim.

  • 6.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for 3D Stacked ICs with Through-Silicon Vias2011In: 3D-TEST, 2011Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs and 3D TSV-SICs with two chips in the stack. We have implemented our techniques and experiments show significant reduction of test cost.

  • 7.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for Core-based 3D Stacked ICs under Power Constraints2012In: RASDAT 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.

  • 8.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias2012In: VLSI 2012, IEEE , 2012Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

  • 9.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)2011In: European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011Conference paper (Refereed)
  • 10.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Scheduling for 3D Stacked ICs under Power Constraints2011In: 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011Conference paper (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

1 - 10 of 10
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf