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  • 1.
    Aragon, Elena
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Jimenez, Juan M.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Maghazeh, Arian
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Rasmusson, Jim
    Sony Mobile Communications, Sweden.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Pattern matching in OpenCL: GPU vs CPU energy consumption on two mobile chipsets2014In: Proceedings of the International Workshop / OpenCL 2013 & 2014 (IWOCL '14), ACM Digital Library, 2014, p. Article No. 5-Conference paper (Other academic)
    Abstract [en]

    Adaptations of the Aho-Corasick (AC) algorithm on high performance graphics processors (also called GPUs) have garnered increasing attention in recent years. However, no results have been reported regarding their implementations on mobile GPUs. In this paper, we show that implementing a state-of-the-art Aho-Corasick parallel algorithm on a mobile GPU delivers significant speedups. We study a few implementation optimizations some of which may seem counter-intuitive to standard optimizations for high-end GPUs. More importantly, we focus on measuring the energy consumed by different components of the OpenCL application rather than reporting the aggregate. We show that there are considerable energy savings compared to the CPU implementation of the AC algorithm.

  • 2.
    Bordoloi, Udeepta
    et al.
    AMD, Sunnyvale, USA.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Accelerating System-Level Design Tasks using Graphics Processors2011Other (Other academic)
    Abstract [en]

    Recent years have seen the increasing use of graphics processing units (GPUs) for nongraphics related applications. Applications that have harnessed the computational power of GPUs span across numerical algorithms, computational geometry, database processing, image processing, astrophysics and bioinformatics. There are many compelling reasons behind exploiting GPUs for such general-purpose computing tasks. First, modern GPUs are extremely powerful. For example, highend GPUs such as the NVidia GeForce GTX 480 and ATI Radeon 5870 have 1.35 TFlops and 2.72 TFlops of peak single precision performance, whereas a high-end general-purpose processor such as the Intel Core i7-960 has a peak performance of 102 Gflops. Additionally, the memory bandwidth of these GPUs are more than 5x greater than what is available to a CPU, which allows them to excel even in low compute intensity but high bandwidth usage scenarios. Second, GPUs are now commodity items as their costs have dramatically reduced over the last few years.

    In spite of a wide variety of computationally expensive system-level design tasks (in the context of embedded systems design) that are regularly solved by software tools running on desktops and laptops equipped with high-end GPUs, the use of GPUs for accelerating such problems is still not a conventional practice within the design automation community. As a result, of late, there has been a lot of research interest in demonstrating the applicability of GPUs in accelerating design automation tasks. Some of tasks that have been accelerated using modern GPUs include schedulability/timing analysis, hardware/software partitioning, fault simulation, and verification of digital designs. In this tutorial we will describe techniques for programming GPUs for general purpose computing (i.e., nongraphics applications) and cover a number of case studies from the electronic design automation area. We will demonstrate how GPUs can lead to significant improvement in running times and hence the usability of the design tools that exploit them. In particular, we will start by introducing the graphics processor architecture and programming models for GPUs (OpenCL and CUDA). OpenCL is an open standard for programming GPUs (and also other modern processors) and is a cross-platform alternative to CUDA. It has been created by a consortium that includes AMD, Apple, IBM, Intel, and Nvidia. We will then discuss various examples of system-level design tasks and identify their computational kernels. Finally, we will present different case studies to illustrate how system-level design algorithms have to be suitably modified in order to map them onto GPUs.

  • 3.
    Bordoloi, Unmesh D.
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Aminifar, Amir
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Schedulability Analysis of Ethernet AVB Switches2014In: 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2014), Chongqing, China, Aug. 20-22, 2014., IEEE Computer Society, 2014Conference paper (Refereed)
    Abstract [en]

    Ethernet AVB is being actively considered by the automotive industry as a candidate for in-vehicle communication backbone. However, several questions pertaining to schedulability of hard real-time messages transmitted via such a switch remain unanswered. In this paper, we attempt to fill this void. We derive equations to perform worst-case response time analysis on Ethernet AVB switches by considering its credit-based shaping algorithm. Also, we propose several approaches to reduce the pessimism in the analysis to provide tighter bounds.

  • 4.
    Bordoloi, Unmesh D.
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Huynh, Huynh P.
    Institute of High Performance, Singapore.
    Mitra, Tulika
    National University of Singapore.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications2010In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010), IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    Multiprocessor System-on-Chips or MPSoCs in the embedded systems domain are increasingly employing multiple customizable processor cores. Such cores offer higher performance through application-specific instruction-set extensions without sacrificing the flexibility of software solutions. Existing techniques for generating appropriate custom instructions for an application domain are primarily restricted to specializing a single processor with the objective of maximizing performance. In a customizable MPSoC, in contrast, the different processor cores have to be customized in a synergistic fashion to create a heterogeneous MPSoC solution that best suits the application. Moreover, such a platform presents conflicting design tradeoffs between system throughput and on-chip memory/logic capacity. In this paper, we propose a framework to systematically explore the complex design space of customizable MPSoC platforms. In particular, we focus on multimedia streaming applications, as this class of applications constitutes a primary target of MPSoC platforms. We capture the high variability in execution times and the bursty nature of streaming applications through appropriate mathematical models. Thus, our framework can efficiently and accurately evaluate the different customization choices without resorting to expensive system-level simulations. We perform a detailed case study of an MPEG encoder application with our framework. It reveals design points with interesting tradeoffs between silicon area requirement for the custom instructions and the on-chip storage for partially-processed video data, while ensuring that all the design points strictly satisfy required QoS guarantees.

  • 5.
    Bordoloi, Unmesh D.
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Suri, Bharath
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Nunna, Swaroop
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Customizing Instruction Set Extensible Reconfigurable Processors using GPUs2012In: 25th International Conferennce on VLSI Design, Hyderabad, India, January 07-11, 2012., IEEE , 2012, p. 418-423Conference paper (Refereed)
    Abstract [en]

    Many reconfigurable processors allow their instruction sets to be tailored according to the performance requirements of target applications. They have gained immense popularity in recent years because of this flexibility of adding custom instructions. However, most design automation algorithms for instruction set customization (like enumerating and selecting the optimal set of custom instructions) are computationally intractable. As such, existing tools to customize instruction sets of extensible processors rely on approximation methods or heuristics. In contrast to such traditional approaches, we propose to use GPUs (Graphics Processing Units) to efficiently solve computationally expensive algorithms in the design automation tools for extensible processors. To demonstrate our idea, we choose a custom instruction selection problem and accelerate it using CUDA (CUDA is a GPU computing engine). Our CUDA implementation is devised to maximize the achievable speedups by various optimizations like exploiting on-chip shared memory and register usage. Experiments conducted on well known benchmarks show significant speedups over sequential CPU implementations as well as over multi-core implementations.

  • 6.
    Bordoloi, Unmesh D.
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tanasa, Bogdan
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    On the Timing Analysis of the Dynamic Segment of FlexRay2012In: International Symposium on Industrial Embedded Systems (SIES 2012), Karlsruhe, Germany, June 20-22, 2012., 2012Conference paper (Other academic)
    Abstract [en]

    FlexRay, developed by a consortium of over hundred automotive companies, is a real-time communication protocol for automotive networks. A communication cycle in FlexRay consists of an event-triggered component known as the dynamic (DYN) segment, apart from a time-triggered segment. Predicting the worst-case response time of messages transmitted on the DYN segment is a difficult problem. This is because a set of complex rules, apart from the priorities of the messages, govern the DYN segment protocol. In this paper, we survey techniques for the timing analysis of the DYN segment. We discuss the challenges associated with the timing analysis of the FlexRay protocol, the proposed techniques and their limitations.

  • 7.
    Bordoloi, Unmesh D.
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tanasa, Bogdan
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tahoori, Mehdi B.
    Institute of Computer Science & Engineering (ITEC), Karlsruhe Institute of Technology (KIT), Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Shazli, Syed Z.
    Northeastern University, USA.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic2012In: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012), Seoul, Korea, August 19-22, 2012., 2012Conference paper (Refereed)
    Abstract [en]

    Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application.In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

  • 8.
    Bordoloi, Unmesh
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Software Model Checking for GPGPU Programs, Towards a Verification Tool2011Report (Other academic)
    Abstract [en]

    The tremendous computing power GPUs are capable of makes of them the epicenter of an unprecedented attention for applications other than graphics and gaming. Apart from the highly parallel nature of the programs to be run on GPUs, the sought after gain in computing power is only achieved with low level tuning at threads level and is therefore veryerror prone. In fact the level of intricacy involved when writing such programs is already a problem and will become a major bottleneck in spreading the technology.

    Only very recent and rare works started looking into using formal methods for helping GPU programmers avoiding errors like data races, incorrect synchronizations or assertions violations. These are at their infancy and directly import techniques adapted for other (sequential) systems with simple approximations for concurrency. Besides that, theonly help we are aware of right now takes a concrete input and explores a tiny portion of the possible thread scheduling looking for such errors. This easily misses common errors and makes of GPU programming a nightmare task. There is therefore still a lot of work to do in order to come up with helpful and scalable tools for today's and tomorrow's GPGPU software.

    We state in this paper our intention in building in Linköping a agship verication tool that will take CUDA code and track and report, with minimal assistance from the programmer, errors like data races, incorrect synchronizations or assertions violations. In order to achieve this ambitious and vital goal for the widespread of GPU programming, webuild on our experience using and implementing CUDA and GPU code and on our latest work in the verication of multicore and concurrent programs. In fact, GPU programs like those written in CUDA are suitable for verication as they typically neither manipulate pointer arithmetics nor allowrecursion. This restricts the focus to concurrency and array manipulation, combined with intra and inter procedural analysis. To give a avor of where we start from, we report on our experiments in automatically verifying two synchronization algorithms that appeared in a recent paper proposing effiient barriers for inter-block synchronization. Unlike any other verication approach for GPU programs,we can show that the algorithms neither deadlock nor violate the barrier condition regardless of the number of threads. We also capture bugs in case basic relations are violated between the number of blocks and the number of threads per block.

  • 9.
    Bordoloi, Unmesh
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    The Frame Packing Problem for CAN-FD2014In: Real-Time Systems Symposium (RTSS 2014), Rome, Italy, Dec. 2-5, 2014., IEEE Press, 2014, p. 284-293Conference paper (Refereed)
    Abstract [en]

    CAN with flexible data rate (CAN-FD) allows transmission of larger payloads compared to standard CAN. However, efficient utilization of CAN-FD bandwidth space calls for a systematic strategy. The challenge arises from the nature of the frame sizes stipulated by CAN-FD as well as the heterogeneity of the periods of the messages and the signals. In this paper, we formulate a frame packing problem for CAN-FD with the optimization objective of bandwidth utilization while meeting temporal constraints. As part of the solution, first, we propose a formula to compute the best-case and the worst-case transmission times of the CAN-FD frames. Thereafter, we propose a framework that solves the optimization problem in pseudo-polynomial time. Experiments show the gains achieved by our framework. The results also show that, when applied to standard CAN, our heuristic provides improved results over existing techniques.

  • 10.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Dastgeer, Usman
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. Ericsson Sweden.
    Andrei, Alexandru
    Ericsson Sweden.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems2017In: DAC '17 Proceedings of the 54th Annual Design Automation Conference 2017, New York, NY, USA: Association for Computing Machinery (ACM), 2017Conference paper (Refereed)
    Abstract [en]

    In response to the tremendous growth of the Internet, towards what we call the Internet of Things (IoT), there is a need to move from costly, high-time-to-market specific-purpose hardware to flexible, low-time-to-market general-purpose devices for packet processing. Among several such devices, GPUs have attracted attention in the past, mainly because the high computing demand of packet processing applications can, potentially, be satisfied by these throughput-oriented machines. However, another important aspect of such applications is the packet latency which, if not handled carefully, will overshadow the throughput benefits. Unfortunately, until now, this aspect has been mostly ignored. To address this issue, we propose a method that considers the variable bit rate of the traffic and, depending on the current rate, minimizes the latency, while meeting the rate demand. We propose a persistent kernel based software architecture to overcome the challenges inherent in GPU implementation like kernel invocation overhead, CPU-GPU communication and memory access overhead. We have chosen packet classification as the packet processing application to demonstrate our technique. Using the proposed approach, we are able to reduce the packet latency on average by a factor of 3.5, compared to the state-of-the-art solutions, without any packet drop.

  • 11.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    General Purpose Computing on Low-Power Embedded GPUs: Has It Come of Age?2013In: 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2013), Samos, Greece, July 15-18, 2013., IEEE Press, 2013Conference paper (Refereed)
    Abstract [en]

    In this paper we evaluate the promise held by low power GPUs for non-graphic workloads that arise in embedded systems. Towards this, we map and implement 5 benchmarks, that find utility in very different application domains, to an embedded GPU. Our results show that apart from accelerated performance, embedded GPUs are promising also because of their energy efficiency which is an important design goal for battery-driven mobile devices. We show that adopting the same optimization strategies as those used for programming high-end GPUs might lead to worse performance on embedded GPUs. This is due to restricted features of embedded GPUs, such as, limited or no user-defined memory, small instruction-set, limited number of registers, among others. We propose techniques to overcome such challenges, e.g., by distributing the workload between GPUs and multi-core CPUs, similar to the spirit of heterogeneous computation.

  • 12.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Horga, Adrian
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Saving Energy without Defying Deadlines on Mobile GPU-based Heterogeneous Systems2014In: 2014 International Conference on Hardware/Software Codesign and System Synthesis, Association for Computing Machinery (ACM), 2014Conference paper (Refereed)
    Abstract [en]

    With the advent of low-power programmable compute cores based on GPUs, GPU-equipped heterogeneous platforms are becoming common in a wide spectrum of industries including safety-critical domains like the automotive industry. While the suitability of GPUs for throughput oriented applications is well-accepted, their applicability for real-time applications remains an open issue. Moreover, in mobile/embedded systems, energy-efficient computing is a major concern and yet, there has been no systematic study on the energy savings that GPUs may potentially provide. In this paper, we propose an approach to utilize both the GPU and the CPU in a heterogeneous fashion to meet the deadlines of a real-time application while ensuring that we maximize the energy savings. We note that GPUs are inherently built to maximize the throughput and this poses a major challenge when deadlines must be satisfied. The problem becomes more acute when we consider the fact that GPUs are more energy efficient than CPUs and thus, a naive approach that is based on maximizing GPU utilization might easily lead to infeasible solutions from a deadline perspective.

  • 13.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Perception-aware power management for mobile games via dynamic resolution scaling2015In: 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), IEEE , 2015, p. 613-620Conference paper (Refereed)
    Abstract [en]

    Modern mobile devices provide ultra-high resolutions in their display panels. This imposes ever increasing workload on the GPU leading to high power consumption and shortened battery life. In this paper, we first show that resolution scaling leads to significant power savings. Second, we propose a perception-aware adaptive scheme that sets the resolution during game play. We exploit the fact that game players are often willing to trade quality for longer battery life. Our scheme uses decision theory, where the predicted user perception is combined with a novel asymmetric loss function that encodes users' alterations in their willingness to save power.

  • 14.
    Nunna, Swaroop
    et al.
    TU Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakraborty, Samarjit
    TU Munich, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Exploiting GPU On-Chip Shared Memory for Accelerating Schedulability Analysis2010In: International Symposium on Electronic System Design (ISED10), Bhubaneswar, India, December 2010., 2010Conference paper (Refereed)
    Abstract [en]

    Embedded electronic devices like mobile phones and automotive control units must perform under strict timing constraints. As such, schedulability analysis constitutes an important phase of the design cycle of these devices. Unfortunately, schedulability analysis for most realistic task models turn out to be computationally intractable (NP-hard). Naturally, in the recent past, different techniques have been proposed to accelerate schedulability analysis algorithms, including parallel computing on Graphics Processing Units (GPUs). However, applying traditional GPU programming methods in this context restricts the effective usage of on-chip memory and in turn imposes limitations on fully exploiting the inherent parallel processing capabilities of GPUs. In this paper, we explore the possibility of accelerating schedulability analysis algorithms on GPUs while exploiting the usage of on-chip memory. Experimental results demonstrate upto 9× speedup of our GPU-based algorithms over the implementations on sequential CPUs.

  • 15.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Control-Quality Optimization for Distributed Embedded Systems with Adaptive Fault Tolerance2012In: ECRTS 2012, IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a design framework for distributed embedded control systems that ensures reliable execution and high quality of control even if some computation nodes fail. When a node fails, the configuration of the underlying distributed system changes and the system must adapt to this new situation by activating tasks at operational nodes. The task mapping as well as schedules and control laws that are customized for the new configuration influence the control quality and must, therefore, be optimized. The number of possible configurations due to faults is exponential in the number of nodes in the system. This design-space complexity leads to unaffordable design time and large memory requirements to store information related to mappings, schedules, and controllers. We demonstrate that it is sufficient to synthesize solutions for a small number of base and minimal configurations to achieve fault tolerance with an inherent minimum level of control quality. We also propose an algorithm to further improve control quality with a priority-based search of the set of configurations and trade-offs between task migration and replication.

  • 16.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Optimized Schedule Synthesis under Real-Time Constraints for the Dynamic Segment of FlexRay2010In: International Conference of Embedded and Ubiquitous Computing, Hong Kong SAR, China, 2010Conference paper (Refereed)
    Abstract [en]

    The design process for automotive electronics isan iterative process, where new components and distributedapplications are added over several design cycles incrementally.Hence, at each design iteration an existing communicationschedule is extended by new messages that have to be scheduledappropriately. In this paper, the goal has been to synthesizeschedules under real-time constraints for the dynamic segmentof FlexRay with respect to the 64-cycle protocol specification. Wepropose a flexible scheduling framework to generate all feasibleschedules for a set of messages satisfying real-time and protocolconstraints. Further, we present an optimization procedure toretain schedules according to suitable design metrics. Eventhough the size of the possible design space is exponential inthe number of messages, our proposed method keeps down theschedule synthesis time to practically acceptable values as shownin the experiments.

  • 17.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On the Quantification of Sustainability and Extensibility of FlexRay Schedules2011In: Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, New York, USA: ACM , 2011, p. 375-380Conference paper (Refereed)
    Abstract [en]

    FlexRay has emerged as the de-facto next generation in-vehicle communication protocol. Messages are scheduled incrementally on FlexRay according to the automotive design paradigm where new applications are added iteratively. On this account, the schedules must be (i) sustainable, i.e., when messages are added in later iterations, they must preserve deadline guarantees of existing messages and (ii) extensible, i.e., they must accommodate future messages without changes to existing schedules. Unfortunately, traditionally used metrics of sustainability and extensibility for timing and schedulability analysis are generic and can not be trivially adapted to FlexRay schedules. This is because of platform-specific properties of FlexRay like being a hybrid paradigm, where both time-triggered and event-triggered segments are used for communication. In this paper, we first introduce new notions of sustainability and extensibility for FlexRay that capture protocol-specific properties and then present novel metrics to quantify sustainable and extensible schedules. We demonstrate the applicability of our results with industrial-size case studies and show that our proposed metrics may be visually represented allowing easy interpretation by system designers in the automotive industry.

  • 18.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany .
    Goswami, Dip
    Eindhoven University of Technology, Netherlands .
    Chakraborty, Samarjit
    Technical University of Munich, Germany .
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Quantifying Notions of Extensibility in FlexRay Schedule Synthesis2014In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 19, no 4, p. 32-Article in journal (Refereed)
    Abstract [en]

    FlexRay has now become a well-established in-vehicle communication bus at most original equipment manufacturers (OEMs) such as BMW, Audi, and GM. Given the increasing cost of verification and the high degree of crosslinking between components in automotive architectures, an incremental design process is commonly followed. In order to incorporate FlexRay-based designs in such a process, the resulting schedules must be extensible, that is: (i) when messages are added in later iterations, they must preserve deadline guarantees of already scheduled messages, and (ii) they must accommodate as many new messages as possible without changes to existing schedules. Apart from extensible scheduling having not received much attention so far, traditional metrics used for quantifying them cannot be trivially adapted to FlexRay schedules. This is because they do not exploit specific properties of the FlexRay protocol. In this article we, for the first time, introduce new notions of extensibility for FlexRay that capture all the protocol-specific properties. In particular, we focus on the dynamic segment of FlexRay and we present a number of metrics to quantify extensible schedules. Based on the introduced metrics, we propose strategies to synthesize extensible schedules and compare the results of different scheduling algorithms. We demonstrate the applicability of the results with industrial-size case studies and also show that the proposed metrics may also be visually represented, thereby allowing for easy interpretation.

  • 19.
    Suri, Bharath
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    A Scalable GPU-Based Approach to Accelerate the Multiple-Choice Knapsack Problem2012In: Design Automation and Test in Europe (DATE12) (short paper), Dresden, Germany, March 12-16, 2012., IEEE , 2012, p. 1126-1129Conference paper (Refereed)
    Abstract [en]

    Variants of the 0-1 knapsack problem manifest themselves at the core of several system-level optimization problems. The running times of such system-level optimization techniques are adversely affected because the knapsack problem is NP-hard. In this paper, we propose a new GPU-based approach to accelerate the multiple-choice knapsack problem, which is a general version of the 0-1 knapsack problem. Apart from exploiting the parallelism offered by the GPUs, we also employ a variety of GPU-specific optimizations to further accelerate the running times of the knapsack problem. Moreover, our technique is scalable in the sense that even when running large instances of the multiple-choice knapsack problems, we can efficiently utilize the GPU compute resources and memory bandwidth to achieve significant speedups.

  • 20.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2016In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, no 3, p. 54:1-54:31Article in journal (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as reformulating the MILP itself.

    Most importantly, we also show how our framework can handle correlations between the queuing events of messages. This is challenging because one cannot apply the convolution operator in the same way as in the case of independent queuing events.

  • 21.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Probabilistic Response Time and Joint Analysis of Periodic Tasks2015In: PROCEEDINGS OF THE 2015 27TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS (ECRTS 2015), IEEE Communications Society, 2015, p. 235-246Conference paper (Refereed)
    Abstract [en]

    In this paper we address the problem of computing the probability response time distribution of periodic tasks scheduled on a uniprocessor systems. Our framework assumes an arbitrary non-idling preemptive scheduling policy that may be either a fixed-priority scheduler (such as Rate Monotonic - RM) or a dynamic-priority scheduler (such as Earliest Deadline First - EDF). At the same time, our framework can handle arbitrary execution time distributions arbitrary deadlines providing numerically accurate results. We also show how the framework can be extended to compute the correlation coefficients between the response times of different jobs by performing the joint analysis.

  • 22.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Reliability-Aware Frame Packing for the Static Segment of FlexRay2011In: EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software                         , Association for Computing Machinery (ACM), 2011, p. 175-184Conference paper (Refereed)
    Abstract [en]

    FlexRay is gaining wide acceptance as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling signals, which are generated by real-time applications, on the FlexRay bus. Signals are first packed together into frames at the application-level and the frames are then transmitted over the bus. To ensure reliability of frames in the presence of faults, frames must be retransmitted over the bus but this comes at the cost of higher bandwidth utilization. To address this issue, in this paper, we propose a novel frame packing method for FlexRay bus. Our method computes the required number of retransmissions of frames that ensures the specified reliability goal. The proposed frame packing method also ensures that none of the signals violates its deadline and that the desired reliability goal for guaranteeing fault-tolerance is met at the minimum bandwidth cost. Extensive experiments on synthetic as well as a industrial case study demonstrate the benefits of our method.

  • 23.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE Computer Society , 2010, p. 385-394Conference paper (Refereed)
    Abstract [en]

    FlexRay has been widely accepted as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling messages on the FlexRay bus, in order to meet the hard realtime deadlines of the automotive applications. However, these techniques do not generate reliable schedules in the sense that they do not provide any performance guarantees in the presence of faults. In this work, we will present a framework for generating fault-tolerant message schedules on the time-triggered (static) segment of the FlexRay bus. We provide formal guarantees that the generated fault-tolerant schedules achieve the reliability goal even in the presence of transient and intermittent faults. Moreover, our technique minimizes the required number of retransmissions of the messages in order to achieve such fault tolerant schedules, thereby, optimizing the bandwidth utilization. Towards this, we formulate the optimization problem in Constraint Logic Programming (CLP), which returns optimal results. However, this procedure is computationally intensive and hence, we also propose an efficient heuristic. The heuristic guarantees the reliability of the constructed schedules but might be sub-optimal with respect to bandwidth utilization. Extensive experiments run on synthetic test cases and real-life case studies illustrate that the heuristic performs extremely well. The experiments also establish that our heuristic scales significantly better than the CLP formulation.

  • 24.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2013In: 25th Euromicro Conference on Real-Time Systems (ECRTS), IEEE , 2013, p. 135-144Conference paper (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratios of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as re-formulating the MILP itself.

  • 25.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Kosuch, Stefanie
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Schedulability Analysis for the Dynamic Segment of FlexRay: A Generalization to Slot Multiplexing2012Conference paper (Refereed)
    Abstract [en]

    FlexRay, developed by a consortium of over hundred automotive companies, is a real-time communication protocol for automotive networks. In this paper, we propose a new approach for timing analysis of the event-triggered component of FlexRay, known as the dynamic segment. Our technique accounts for the fact that the FlexRay standard allows slot multiplexing, i.e., the same priority can be assigned to more than one message. Existing techniques have either ignored slot multiplexing in their analysis or made simplifying assumptions that severely limit achieving high bandwidth utilization. Moreover, we show that our technique returns less pessimistic results compared to previously known techniques even in the case where slot multiplexing is ignored.

1 - 25 of 25
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