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  • 1.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design of Integrated Building Blocks for the Digital/Analog Interface2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The integrated circuit has, since it was invented in the late 1950's, undergone a tremendous development and is today found in virtually all electric equipment. The small feature size and low production cost have made it possible to implement electronics in everyday objects ranging from computers and mobile phones to smart prize tags. Integrated circuits are typically used for data communication, signal processing and data storage. Data is usually stored in digital format but signal processing can be performed both in the digital and in the analog domain. For best performance, the right partition of signal processing between the analog and digital domain must be used. This is made possible by data converters converting data between the domains. A device converting an analog signal into a digital representation is called an analog-to-digital converter (ADC) and a device converting digital data into an analog representation is called a digital-to-analog converter (DAC). In this work we present research results on these data converters and the results are compiled in three different categories. The first contribution is an error correction technique for DACs called dynamic element matching, the second contribution is a power efficient time-to-digital converter architecture and the third is a design methodology for frequency synthesis using digital oscillators.

    The accuracy of a data converter, i.e., how accurate data is converted, is often limited by manufacturing errors. One type of error is the so-called matching error and in this work we investigate an error correction technique for DACs called dynamic element matching (DEM). If distortion is limiting the performance of a DAC, the DEM technique increases the accuracy of the DAC by transforming the matching error from being signal dependent, which results in distortion, to become signal independent noise. This noise can then be spectrally shaped or filtered out and hereby increasing the overall resolution of the system. The DEM technique is investigated theoretically and the theory is supported by measurement results from an implemented 14-bit DAC using DEM. From the investigation it is concluded that DEM increases the performance of the DAC when matching errors are dominating but has less effect at conversion speeds when dynamic errors dominate.

    The next contribution is a new time-to-digital converter (TDC) architecture. A TDC is effectively an ADC converting a time difference into a digital representation. The proposed architecture allows for smaller and more power efficient data conversion than previously reported and the implemented TDC prototype is smaller and more power efficient as compared to previously published TDCs in the same performance segment.

    The third contribution is a design methodology for frequency synthesis using digital oscillators. Digital oscillators generate a sinusoidal output using recursive algorithms. We show that the performance of digital oscillators, in terms of amplitude and frequency stability, to a large extent depends on the start conditions of the oscillators. Further we show that by selecting the proper start condition an oscillator can be forced to repeat the same output sequence over and over again, hence we have a locked oscillator. If the oscillator is locked there is no drift in amplitude or frequency which are common problems for recursive oscillators not using this approach. To find the optimal start conditions a search algorithm has been developed which has been thoroughly tested in simulations. The digital oscillator output is used for test signal generation for a DAC or used to generate tones with high spectral purity using DACs.

    List of papers
    1. A comparison of dynamic element matching in DACs
    Open this publication in new window or tab >>A comparison of dynamic element matching in DACs
    1999 (English)In: Proceedings '99 : Oslo, Norway, 8-9 November 1999 / [ed] Trond Sæther, 1999, p. 385-390Conference paper, Published paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some "new" important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112582 (URN)8798263722 (ISBN)
    Conference
    The 17th NORCHIP Conference, November 8-9, Oslo, Norway
    Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2014-12-04Bibliographically approved
    2. A strategy for implementing dynamic element matching in current-steering DACs
    Open this publication in new window or tab >>A strategy for implementing dynamic element matching in current-steering DACs
    2000 (English)In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, IEEE , 2000, p. 51-56Conference paper, Published paper (Other academic)
    Abstract [en]

    Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)

    Place, publisher, year, edition, pages
    IEEE, 2000
    Keywords
    0.35 micron;11 MHz;14 bit;3.3 V;88 MHz;CMOS wideband DAC;current-steering DACs;dynamic element matching;partial randomization technique;wideband digital-to-analog converter;CMOS integrated circuits;digital-analogue conversion;
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-70637 (URN)10.1109/SSMSD.2000.836445 (DOI)0-7803-5975-5 (ISBN)
    Conference
    SSMSD 2000, 27 - 29 Feb. 2000, San Diego, CA , USA
    Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2014-12-04
    3. Models and Implementation of a Dynamic Element Matching DAC
    Open this publication in new window or tab >>Models and Implementation of a Dynamic Element Matching DAC
    2003 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, p. 7-16Article in journal (Refereed) Published
    Abstract [en]

    The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.

    Place, publisher, year, edition, pages
    Netherlands: Springer, 2003
    Keywords
    DAC, DEM, CMOS, matching, current-steering
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-21845 (URN)10.1023/A:1020331415597 (DOI)
    Available from: 2009-10-06 Created: 2009-10-06 Last updated: 2017-12-13
    4. A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
    Open this publication in new window or tab >>A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
    2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed) Published
    Abstract [en]

    A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2014
    Keywords
    CMOS; delay latch; time-to-digital converter (TDC); Vernier
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112180 (URN)10.1109/TCSII.2014.2345289 (DOI)000343320500009 ()
    Available from: 2014-11-18 Created: 2014-11-18 Last updated: 2017-12-05
    5. Power-efficient time-to-digital converter for all-digital frequency locked loops
    Open this publication in new window or tab >>Power-efficient time-to-digital converter for all-digital frequency locked loops
    2015 (English)In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 300-303Conference paper, Published paper (Refereed)
    Abstract [en]

    An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112589 (URN)10.1109/ECCTD.2015.7300008 (DOI)000380498200010 ()978-1-4799-9877-7 (ISBN)
    Conference
    European Conference on Circuit Theory and Design (ECCTD)
    Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2016-09-25Bibliographically approved
    6. Steady-state cycles in digital oscillators
    Open this publication in new window or tab >>Steady-state cycles in digital oscillators
    2014 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    Digital recursive oscillators locked in steady-state can be used to generate sinusoids with high spectral purity. The locking occurs when the oscillator returns to a previously visited state and repeats its sequence. In this work we propose a new search algorithm and two new search strategies to find all steady-states for a given oscillator configuration. The improvement in spurious-free dynamic range is between 7 and 40 dB compared to previously reported results. The algorithm is also able to find oscillator sequences for more frequencies than previously reported work. A key part of the method is the reduction of the search space made possible by a proposed extension of existing theory on recursive oscillators. Specific properties of digital oscillators in a steady-state are also discussed. It is shown that the initial states can be used to individually control the phase, amplitude, spectral purity, and also cycle length of the oscillator output.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112590 (URN)
    Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2015-03-11Bibliographically approved
  • 2.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed)
    Abstract [en]

    A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

  • 3.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power-efficient time-to-digital converter for all-digital frequency locked loops2015In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 300-303Conference paper (Refereed)
    Abstract [en]

    An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

  • 4.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oskar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Steady-state cycles in digital oscillators2014Manuscript (preprint) (Other academic)
    Abstract [en]

    Digital recursive oscillators locked in steady-state can be used to generate sinusoids with high spectral purity. The locking occurs when the oscillator returns to a previously visited state and repeats its sequence. In this work we propose a new search algorithm and two new search strategies to find all steady-states for a given oscillator configuration. The improvement in spurious-free dynamic range is between 7 and 40 dB compared to previously reported results. The algorithm is also able to find oscillator sequences for more frequencies than previously reported work. A key part of the method is the reduction of the search space made possible by a proposed extension of existing theory on recursive oscillators. Specific properties of digital oscillators in a steady-state are also discussed. It is shown that the initial states can be used to individually control the phase, amplitude, spectral purity, and also cycle length of the oscillator output.

  • 5.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    Rudberg, Mikael
    Linköping University, Department of Electrical Engineering, Electronics System.
    Improvement of segmented DACs (Swedish pat. 0001917-4)2000Patent (Other (popular science, discussion, etc.))
  • 6.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A comparison of dynamic element matching in DACs1999In: Proceedings '99 : Oslo, Norway, 8-9 November 1999 / [ed] Trond Sæther, 1999, p. 385-390Conference paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some "new" important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

  • 7.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A strategy for implementing dynamic element matching in current-steering DACs2000In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, IEEE , 2000, p. 51-56Conference paper (Other academic)
    Abstract [en]

    Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)

  • 8.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Comparison of Different Dynamic Element Matching Techniques for Wideband CMOS DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some ”new” important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

  • 9.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Spectral shaping of DAC nonlinearity errors through modulation of expected errors2001In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, IEEE , 2001, Vol. 3, p. 417-420Conference paper (Refereed)
    Abstract [en]

    Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included

  • 10.
    Jalili, Armin
    et al.
    ECE Department, Isfahan University of Technology, Isfahan, Iran.
    Sayedi, S. M.
    ECE Department, Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Calibration of sigma-delta analog-to-digital converters based on histogram test methods2010In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.

  • 11.
    Rudberg, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    Scrambler and a method of scrambling data words, (US pat. 2002027519)2002Patent (Other (popular science, discussion, etc.))
  • 12.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Andersson, Niklas U.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Synthesis of time-to-digital convertersManuscript (preprint) (Other academic)
    Abstract [en]

    We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.

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