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  • 1.
    Garrido Gálvez, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Källström, Petter
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Kumm, Martin
    University of Kassel, Germany.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    CORDIC II: A New Improved CORDIC Algorithm2016Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, nr 2, s. 186-190Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this brief, we present the CORDIC II algorithm. Like previous CORDIC algorithms, the CORDIC II calculates rotations by breaking down the rotation angle into a series of microrotations. However, the CORDIC II algorithm uses a novel angle set, different from the angles used in previous CORDIC algorithms. The new angle set provides a faster convergence that reduces the number of adders with respect to previous approaches.

  • 2.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Källström, Petter
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs2012Ingår i: 22nd International Conference on Field Programmable Logic and Applications (FPL) / [ed] Dirk Koch, Satnam Singh, Jim Torresen, Piscataway, NJ, USA: IEEE Communications Society, 2012, s. 71-74Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.

  • 3.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Källström, Petter
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Qureshi, Fahad
    Not Found:Linkoping Univ, Dept Elect Engn, SE-58183 Linkoping, Sweden; Tampere University of Technology, Finland.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Efficient FPGA Mapping of Pipeline SDF FFT Cores2017Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 25, nr 9, s. 2486-2497Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

  • 4.
    Källström, Petter
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Garrido Gálvez, Mario
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Low-Complexity Rotators for the FFT Using Base-3 Signed Stages2012Ingår i: APCCAS 2012 : 2012 IEEE Asia Pacific Conference on Circuits and Systems, Piscataway, N.J., USA: IEEE , 2012, s. 519-522Konferensbidrag (Refereegranskat)
    Abstract [en]

    Rotations by angles that are fractions of the unit circle find applications in e.g. fast Fourier transform (FFT) architectures. In this work we propose a new rotator that consists of a series of stages. Each stage calculates a micro-rotation by an angle corresponding to a power-of-three fractional parts. Using a continuous powers-of-three range, it is possible to carry out all rotations required. In addition, the proposed rotators are compared to previous approaches, based of shift-and-add algorithms, showing improvements in accuracy and number of adders.

  • 5.
    Källström, Petter
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs2016Ingår i: 26th International Conference on Field-Programmable Logic and Applications, Lausanne: IEEE , 2016, s. 338-341Konferensbidrag (Refereegranskat)
    Abstract [en]

    Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. The result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.

  • 6.
    Källström, Petter
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Magnitude Scaling for Increased SFDR in DDFS2011Ingår i: 29th Norchip Conference, Lund, Sweden, 14-15 November 2011, IEEE , 2011, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding.This results in uncontrolled rounding of up to 0.5 LSB, causing some noise.In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB.

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