liu.seSearch for publications in DiVA
Change search
Refine search result
1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ring-oscillator-based timing generator for ultralow-power applications2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 2.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS2016In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

  • 3.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Angelov, Pavel
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    This paper presents three self-oscillating multilevel time-interleaved switched-capacitor DC/DC converters implemented and taped-out in 0:18-mu m CMOS targeting microwatt power levels. Two of the converters are step-up with ratios of 1:2, 1:3, and 1:4, and one is a step-down with ratios of 2:1, 3:1, and 4:1. They all regulate the output voltage towards a targeted reference removing the need for a separate regulator. Aimed for use in vibration energy harvesting systems, the converters have a wide combined input voltage range of 450 mV to 20 V. The low voltage step-up converter operates from an input voltage of 475 mV and has a peak measured power efficiency of 82.2 % with an area of 0.62 mm(2). The medium voltage step-up converter operates from an input voltage of 700 mV and has a peak power efficiency of 74.5 % and an area of 0.53 mm(2). Lastly, the step-down converter works with input voltages up to 20 V and achieves a peak power efficiency of 68.7 % with an area of 0.55 mm(2).

  • 4.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems2015In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 308-311Conference paper (Refereed)
    Abstract [en]

    MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

  • 5.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Design considerations for interface circuits to low-voltage piezoelectric energy harvesters2014Conference paper (Refereed)
    Abstract [en]

    In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm2 and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.

  • 6.
    Schuffny, Franz Marcus
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Hayoz, Michel
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Bae, Cheolyong
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Arya, Ishan
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Gokhale, Madhur
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Chandar, Annapragada Hema
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Angelov, Pavel
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Zero-Crossing Detector for a Piezoelectric Energy Harvester2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Energy harvesting is a method that extracts electrical energy from the environment. This paper presents an integrated circuit in 0.35-mu m CMOS that harvests energy from mechanical vibration using a piezoelectric transducer. The circuit applies a bias-flip rectifier to improve the efficiency of the energy extraction. The paper focuses on the design of the key element of the bias-flip rectifier, the zero-crossing detector. It detects the zero crossing of the input current from the piezoelectric transducer and generates the control signals for the bias-flip rectifier. Post-layout simulations show a very low power consumption and high efficiency of the harvester.

1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf