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  • 1.
    Chen, Kairang
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Energy-Efficient Data Converters for Low-Power Sensors2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energy-harvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxide-semiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications.

    The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-μm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage capacitive charge pump (CCP) is utilized to achieve the gain-stage instead of using the switch capacitor (SC) amplifier. Unity-gain OTAs have been used as the analog buffers to prevent the charge sharing between the CCP stages. The detailed design considerations are given in this work. The prototype ADC, designed and fabricated in a low-cost 0.35-μm CMOS process, achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 μW and 96 μW, respectively. The corresponding Schreier FoM are 166.7 dB and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR > 75 dB up

    to 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    As the low-power sensors might be active only for very short time triggered by an external pulse to acquire the data, the third work is a 14-bit asynchronous two-stage pipelined SAR ADC which has been designed and simulated in 0.18-μm CMOS process. A self-synchronous loop based on an edge detector is utilized to generate an internal clock with variable phase. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Three separate asynchronous clock generators are implemented to create the control signals for two sub-ADCs and the gain-stage between. Aiming to reduce the power consumption of the gain-stage, simple source followers as the analog buffers are implemented in the 3-stage CCP gain-stage. Post-layout simulation results show that the ADC achieves a SNDR of 83.5 dB while consuming 2.39 μW with a sampling rate of 10 kS/s. The corresponding Schreier FoM is 176.7 dB.

    List of papers
    1. Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    Open this publication in new window or tab >>Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    Place, publisher, year, edition, pages
    Springer, 2016
    Keywords
    Pipelined SAR ADC; High resolution; OTA; Capacitive DAC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-124472 (URN)10.1007/s10470-015-0648-2 (DOI)000367750900011 ()
    Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2017-11-30Bibliographically approved
    2. A pipelined SAR ADC with gain-stage based on capacitive charge pump
    Open this publication in new window or tab >>A pipelined SAR ADC with gain-stage based on capacitive charge pump
    2017 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    Place, publisher, year, edition, pages
    New York: Springer, 2017
    Keywords
    Capacitive charge pump, OTA, Switch capacitor integrator, Two-stage pipelined SAR ADC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Computer Engineering Software Engineering
    Identifiers
    urn:nbn:se:liu:diva-133228 (URN)10.1007/s10470-016-0872-4 (DOI)000391922200005 ()
    Available from: 2016-12-15 Created: 2016-12-15 Last updated: 2018-01-13Bibliographically approved
    3. Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    Open this publication in new window or tab >>Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    2015 (English)In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    Keywords
    High resolution; pipeline; power consumption; successive approximation analog-to-digital; converter; two-stage
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-122623 (URN)10.1109/MIXDES.2015.7208570 (DOI)000364071600094 ()978-8-3635-7806-0 (ISBN)
    Conference
    The22 International Conference “Mixed Design of Integrated Circuits and Systems”(MIXDES), Toruń, Poland, 25-27 June 2015
    Available from: 2015-11-16 Created: 2015-11-12 Last updated: 2016-12-15Bibliographically approved
    4. Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    Open this publication in new window or tab >>Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    2016 (English)In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

    Place, publisher, year, edition, pages
    IEEE, 2016
    Keywords
    Capacitive charge pump; successive approximation analog-to-digital converter; power consumption; pipeline; two-stage
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-132104 (URN)10.1109/MIXDES.2016.7529729 (DOI)000383221700035 ()978-8-3635-7808-4 (ISBN)
    Conference
    23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
    Available from: 2016-10-18 Created: 2016-10-17 Last updated: 2016-12-15
  • 2.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

  • 3.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Capacitive Charge Pump Gain-stage with Source Follower Buffers for Pipelined SAR ADCs2016In: 2016 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 mu m CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 mu W at a sampling frequency of 10 kHz.

  • 4.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump2016In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

  • 5.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Power Analysis for Two-Stage High Resolution Pipeline SAR ADC2015In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

  • 6.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

  • 7.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS2016In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

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