liu.seSearch for publications in DiVA
Change search
Refine search result
1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the 'Create feeds' function.
  • 1.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Pasha, Muhammad Touqir
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Aliasing-Compensated Polar PWM Transmitter2017In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 64, no 8, p. 912-916Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

  • 2.
    Pasha, Muhammad Touqir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Ali Shah, Yasir
    COMSATS Institute IT, Pakistan.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Wide Range All-Digital Delay Locked Loop for Video Applications2015In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), IEEE , 2015, p. 372-375Conference paper (Refereed)
    Abstract [en]

    An all-digital delay locked loop (DLL) for use in an analog video front end (AFE) is presented. The DLL is designed for a wide input frequency range of 40-300 MHz to cater to a range of different video standards currently in use. The proposed DLL has a closed loop architecture that tracks PVT variations and locks to the input signal in a maximum of nine clock cycles. At its output, the DLL generates 32 uniformly distributed phases of the input clock to provide an optimal sampling point for the analog to digital conversion of the input signal in the AFE.

  • 3.
    Pasha, Muhammad Touqir
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Fahim Ul Haque, Muhammad
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. NED Univ Engn and Technol, Pakistan.
    Ahmad, Jahanzeb
    Intel Corp, England.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Modified All-Digital Polar PWM Transmitter2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, no 2, p. 758-768Article in journal (Refereed)
    Abstract [en]

    This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

  • 4.
    Touqir Pasha, Muhammad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Circuit Design for All-Digital Frequency Synthesizers2014Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The market for low cost portable electronics is rapidly growing. Physical activity monitors, portable music players, and smart watches are fast becoming a part of daily life. As the market for wearable devices has grown, a primary concern for IC manufacturers is to provide low cost, low power and lightweight circuit solutions. In a bid to lower the costs and extend battery life there is an increased interest in using low-cost, low-power CMOS processes. As a result fully integrated systems on chips (SOC) have been realized that efficiently perform the required functions. These SOCs house digital, analog and in some cases radio circuits on a single die in a bid to reduce cost and improve productivity.

    Phase Locked Loops (PLLs) are a key building block for all SOCs where they are used to generate clock signals for synchronous systems. In monolithic implementations the design cost of a circuit is measured in terms of the silicon area and not the number of devices in the circuit. With the advent of all-digital techniques, there is a renewed interest in the design of compact PLLs as the area occupied by the traditional PLLs is very large due to the presence of large passive components in the loop filter and the oscillator. As a result, various digital circuit design techniques are being explored to design compact all-digital PLLs (ADPLLs) while satisfying the performance requirements for the target applications.

    The focus of this work is to explore new techniques for area, power and time efficient design of ADPLL component blocks. The first part of this works focuses on the feasibility of using automatic place and route (P&R) tools to synthesize a time-to-digital converter (TDC). An area efficient TDC is synthesized in a 65 nm CMOS process using automated P&R which exhibits a time resolution of 6.5 ps with an input sampling rate of 100 MS/s while occupying an area of 0.002 mm2. A modified switching scheme is also presented which reduces the power consumption of the thermometer-to-binary encoder by up to 40%.

    The second part of this thesis proposes a power supply filter for mitigating the affect of cyclostationary noise on the voltage controlled ring oscillator. The key idea is to raise the impedance in the current supply during the sensitive periods and lower it during insensitive periods of the oscillator operation. To demonstrate the feasibility of the proposed filter, a pseudo differential ring oscillator is designed in a 65 nm CMOS process which exhibits an rms jitter of less than 14 ps at 2.4 GHz in the presence of a 500 mV noise tone in the power supply.

    List of papers
    1. Synthesis of time-to-digital converters
    Open this publication in new window or tab >>Synthesis of time-to-digital converters
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113277 (URN)
    Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-14
    2. A modified switching scheme for multiplexer based thermometer-to-binary encoders
    Open this publication in new window or tab >>A modified switching scheme for multiplexer based thermometer-to-binary encoders
    2014 (English)In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper, Oral presentation only (Refereed)
    Abstract [en]

    A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

    Place, publisher, year, edition, pages
    IEEE, 2014
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113278 (URN)10.1109/NORCHIP.2014.7004733 (DOI)978-1-4799-5442-1 (ISBN)
    Conference
    NORCHIP 2014. The Nordic Microelectronics event, 32nd Norchip Conference 27-28 October 2014, Tampere, Finland
    Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-03-26Bibliographically approved
    3. Frequency control schemes for single ended ring oscillators
    Open this publication in new window or tab >>Frequency control schemes for single ended ring oscillators
    2011 (English)In: 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden, IEEE , 2011, p. 361-364Conference paper, Oral presentation only (Refereed)
    Abstract [en]

    An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.

    Place, publisher, year, edition, pages
    IEEE, 2011
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113279 (URN)10.1109/ECCTD.2011.6043361 (DOI)978-1-4577-0616-5 (ISBN)978-1-4577-0617-2 (ISBN)
    Conference
    20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden
    Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-21Bibliographically approved
    4. A novel technique to reduce the supply sensitivity of CMOS ring oscillators
    Open this publication in new window or tab >>A novel technique to reduce the supply sensitivity of CMOS ring oscillators
    2014 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-113280 (URN)
    Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-14
  • 5.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Andersson, Niklas U.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Synthesis of time-to-digital convertersManuscript (preprint) (Other academic)
    Abstract [en]

    We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.

  • 6.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A novel technique to reduce the supply sensitivity of CMOS ring oscillators2014Manuscript (preprint) (Other academic)
    Abstract [en]

    A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf