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  • 1.
    Abdulla, Parosh Aziz
    et al.
    Department of Information Technology, Uppsala University, Sweden.
    Atig, Mohamed Faouzi
    Department of Information Technology, Uppsala University, Sweden.
    Chen, Yu-Fang
    Institute of Information Science, Academia Sinica, Taiwan.
    Holik, Lukas
    Faculty of Information Technology, Brno University of Technology, Czech Republic.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Rümmer, Philipp
    Department of Information Technology, Uppsala University, Sweden.
    Stenman, Jari
    Department of Information Technology, Uppsala University, Sweden.
    String Constraints for Verification2014In: 26th International Conference on Computer Aided Verification (CAV 2014), Vienna, Austria, Jul. 9-12, 2014., Springer, 2014, 150-166 p.Conference paper (Refereed)
    Abstract [en]

    We present a decision procedure for a logic that combines (i) word equations over string variables denoting words of arbitrary lengths, together with (ii) constraints on the length of words, and on (iii) the regular languages to which words belong. Decidability of this general logic is still open. Our procedure is sound for the general logic, and a decision procedure for a particularly rich fragment that restricts the form in which word equations are written. In contrast to many existing procedures, our method does not make assumptions about the maximum length of words. We have developed a prototypical implementation of our decision procedure, and integrated it into a CEGAR-based model checker for the analysis of programs encoded as Horn clauses. Our tool is able to automatically establish the correctness of several programs that are beyond the reach of existing methods.

  • 2.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University, Sweden.
    Atig, Mohamed Faouzi
    Uppsala University, Sweden.
    Chen, Yu-Fang
    Academia Sinica, Taiwan.
    Leonardsson, Carl
    Uppsala University, Sweden.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Automatic fence insertion in integer programs via predicate abstraction2012In: Static Analysis: 19th International Symposium, SAS 2012, Deauville, France, September 11-13, 2012. Proceedings / [ed] Antoine Miné, David Schmidt, Springer Berlin/Heidelberg, 2012, 164-180 p.Conference paper (Refereed)
    Abstract [en]

    We propose an automatic fence insertion and verification framework for concurrent programs running under relaxed memory. Unlike previous approaches to this problem, which allow only variables of finite domain, we target programs with (unbounded) integer variables. The problem is difficult because it has two different sources of infiniteness: unbounded store buffers and unbounded integer variables. Our framework consists of three main components: (1) a finite abstraction technique for the store buffers, (2) a finite abstraction technique for the integer variables, and (3) a counterexample guided abstraction refinement loop of the model obtained from the combination of the two abstraction techniques. We have implemented a prototype based on the framework and run it successfully on all standard benchmarks together with several challenging examples that are beyond the applicability of existing methods.

  • 3.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University, Sweden.
    Atig, Mohamed Faouzi
    Uppsala University, Sweden.
    Chen, Yu-Fang
    Academia Sinica, Taiwan.
    Leonardsson, Carl
    Uppsala University, Sweden.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Memorax, a Precise and Sound Tool for Automatic Fence Insertion under TSO2013In: Tools and Algorithms for the Construction and Analysis of Systems: 19th International Conference, TACAS 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013. Proceedings, Springer Berlin/Heidelberg, 2013, 530-536 p.Conference paper (Refereed)
    Abstract [en]

    We introduce MEMORAX, a tool for the verification of control state reachability (i.e., safety properties) of concurrent programs manipulating finite range and integer variables and running on top of weak memory models. The verification task is non-trivial as it involves exploring state spaces of arbitrary or even infinite sizes. Even for programs that only manipulate finite range variables, the sizes of the store buffers could grow unboundedly, and hence the state spaces that need to be explored could be of infinite size. In addition, MEMORAX in- corporates an interpolation based CEGAR loop to make possible the verification of control state reachability for concurrent programs involving integer variables. The reachability procedure is used to automatically compute possible memory fence placements that guarantee the unreachability of bad control states under TSO. In fact, for programs only involving finite range variables and running on TSO, the fence insertion functionality is complete, i.e., it will find all minimal sets of memory fence placements (minimal in the sense that removing any fence would result in the reachability of the bad control states). This makes MEMORAX the first freely available, open source, push-button verification and fence insertion tool for programs running under TSO with integer variables.

  • 4.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University.
    Atig, Mohammed Faouzi
    Uppsala University.
    Ganjei, Zeinab
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Zhu, Yunyun
    Uppsala University.
    Verification of Cache Coherence Protocols wrt. Trace Filters2015Conference paper (Refereed)
    Abstract [en]

    We address the problem of parameterized verification of cache coherence protocols for hardware accelerated transactional memories. In this setting, transactional memories leverage on the versioning capabilities of the underlying cache coherence protocol. The length of the transactions, their number, and the number of manipulated variables (i.e., cache lines) are parameters of the verification problem. Caches in such systems are finite-state automata communicating via broadcasts and shared variables. We augment our system with filters that restrict the set of possible executable traces according to existing conflict resolution policies. We show that the verification of coherence for parameterized cache protocols with filters can be reduced to systems with only a finite number of cache lines. For verification, we show how to account for the effect of the adopted filters in a symbolic backward reachability algorithm based on the framework of constrained monotonic abstraction. We have implemented our method and used it to verify transactional memory coherence protocols with respect to different conflict resolution policies.

  • 5.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University, Sweden.
    Dwarkadas, Sandhya
    University of Rochester, U.S.A..
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Shriraman, Arrvindh
    Simon Fraser University, Canada.
    Zhu, Yunyun
    Uppsala University, Sweden.
    Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory2013In: Design, Automation & Test in Europe (DATE 2013), Grenoble, France, March 18-22, 2013., IEEE , 2013, 785-790 p.Conference paper (Refereed)
    Abstract [en]

    We consider the verification of safety (strict se- rializability and abort consistency) and liveness (obstruction and livelock freedom) for the hybrid transactional memory framework FLEXTM. This framework allows for flexible imple- mentations of transactional memories based on an adaptation of the MESI coherence protocol. FLEXTM allows for both eager and lazy conflict resolution strategies. Like in the case of Software Transactional Memories, the verification problem is not trivial as the number of concurrent transactions, their size, and the number of accessed shared variables cannot be a priori bounded. This complexity is exacerbated by aspects that are specific to hardware and hybrid transactional memories. Our work takes into account intricate behaviours such as cache line based conflict detection, false sharing, invisible reads or non-transactional instructions. We carry out the first automatic verification of a hybrid transactional memory and establish, by adopting a small model approach, challenging properties such as strict serializability, abort consistency, and obstruction freedom for both an eager and a lazy conflict resolution strategies. We also detect an example that refutes livelock freedom. To achieve this, our prototype tool makes use the latest antichain based techniques to handle systems with tens of thousands of states.

  • 6.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University.
    Haziza, Frédéric
    Uppsala University.
    Holik, Lukas
    Brno University of Technology, Czech Republic.
    Jonsson, Bengt
    Uppsala University.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    An Integrated Specification and Verification Technique for Highly Concurrent Data Structures2013In: The 19th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2013), Rome, Italy, March 16-24, 2013., 2013Conference paper (Refereed)
    Abstract [en]

    We present a technique for automatically verifying safety properties of concurrent programs, in particular programs which rely on subtle dependencies of local states of different threads, such as lock-free implementations of stacks and queues in an environment without garbage collection. Our technique addresses the joint challenges of infinite-state specifications, an unbounded number of threads, and an unbounded heap managed by explicit memory allocation. Our technique builds on the automata-theoretic approach to model checking, in which a specification is given by an automaton that observes the execution of a program and accepts executions that violate the intended specification.We extend this approach by allowing specifications to be given by a class of infinite-state automata. We show how such automata can be used to specify queues, stacks, and other data structures, by extending a data-independence argument. For verification, we develop a shape analysis, which tracks correlations between pairs of threads, and a novel abstraction to make the analysis practical. We have implemented our method and used it to verify programs, some of which have not been verified by any other automatic method before.

  • 7.
    Abrahamsson, Robin
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Berntsen, David
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Comparing modifiability of React Native and two native codebases2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Creating native mobile application on multiple platforms generate a lot of duplicate code. This thesis has evaluated if the code quality attribute modifiability improves when migrating to React Native. One Android and one iOS codebase existed for an application and a third codebase was developed with React Native. The measurements of the codebases were based on the SQMMA-model. The metrics for the model were collected with static analyzers created specifically for this project. The results created consists of graphs that show the modifiability for some specific components over time and graphs that show the stability of the platforms. These graphs show that when measuring code metrics on applications over time it is better to do this on a large codebase that has been developed for some time. When calculating a modifiability value the sum of the metrics and the average value of the metrics between files should be used and it is shown that the React Native platform seems to be more stable than native.

  • 8.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, Software and Systems.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation2011In: Digital System Design (DSD), 2011 14th Euromicro Conference on, IEEE, 2011, 197-204 p.Conference paper (Refereed)
    Abstract [en]

    High temperature and process variation areundesirable effects for modern systems-on-chip. The hightemperature is a prominent issue during test and should be takencare of during the test process. Modern SoCs, affected by largeprocess variation, experience rapid and large temperaturedeviations and, therefore, a traditional static test schedule which isunaware of these deviations will be suboptimal in terms of speedand/or thermal-safety. This paper presents an adaptive testscheduling method which addresses the temperature deviationsand acts accordingly in order to improve the test speed andthermal-safety. The proposed method is divided into acomputationally intense offline-phase, and a very simple online-phase.In the offline-phase a schedule tree is constructed, and inthe online-phase the appropriate path in the schedule tree istraversed, step by step and based on temperature sensor readings.Experiments have demonstrated the efficiency of the proposedmethod.

  • 9.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs2014In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, IEEE conference proceedings, 2014Conference paper (Refereed)
    Abstract [en]

    Burn-in is usually carried out with high temperature and elevated voltage. Since some of the early-life failures depend not only on high temperature but also on temperature gradients, simply raising up the temperature of an IC is not sufficient to detect them. This is especially true for 3D stacked ICs, since they have usually very large temperature gradients. The efficient detection of these early-life failures requires that specific temperature gradients are enforced as a part of the burn-in process. This paper presents an efficient method to do so by applying high power stimuli to the cores of the IC under burn-in through the test access mechanism. Therefore, no external heating equipment is required. The scheduling of the heating and cooling intervals to achieve the required temperature gradients is based on thermal simulations and is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed method.

  • 10.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs2015In: 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015., Institute of Electrical and Electronics Engineers (IEEE), 2015, 526-531 p.Conference paper (Refereed)
    Abstract [en]

    In a modern 3D IC, electrical connections between vertically stacked dies are made using through silicon vias. Through silicon vias are subject to undesirable early-life effects such as protrusion as well as void formation and growth. These effects result in opens, resistive opens, and stress induced carrier mobility reduction, and consequently circuit failures. Operating the ICs under extreme temperature cycling can effectively accelerate such early-life failures and make them detectable at the manufacturing test process. An integrated temperature-cycling acceleration and test technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration procedures. All these result in a reduction in the overall test costs. The proposed method is a schedule-based solution that creates the required temperature cycling effect along with performing the tests. Experimental results demonstrate its efficiency.

  • 11.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Efficient Test Application for Rapid Multi-Temperature Testing2015In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, Association for Computing Machinery (ACM), 2015, 3-8 p.Conference paper (Other academic)
    Abstract [en]

    Different defects may manifest themselves at different temperatures. Therefore, the tests that target such temperature-dependent defects must be applied at different temperatures appropriate for detecting them. Such multi-temperature testing scheme applies tests at different required temperatures. It is known that a test's power dissipation depends on the previously applied test. Therefore, the same set of tests when organized differently dissipates different amounts of power. The technique proposed in this paper organizes the tests efficiently so that the resulted power levels lead to the required temperatures. Consequently a rapid multi-temperature testing is achieved. Experimental studies demonstrate the efficiency of the proposed technique.

  • 12.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Heuristics for Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    High working temperature and process variation are undesirable effects for modern systems-on-chip. The high temperature should be taken care of during the test. On the other hand, large process variations induce rapid and large temperature deviations causing the traditional static test schedules to be suboptimal in terms of speed and/or thermal-safety. A remedy to this problem is an adaptive test schedule which addresses the temperature deviations by reacting to them. Our adaptive method is divided into a computationally intense offline-phase, and a very simple online-phase. In this paper, heuristics are proposed for the offline phase in which the optimized schedule tree is found. In the online-phase, based on the temperature sensor readings the appropriate path in the schedule tree is traversed. Experiments are made to tune the proposed heuristics and to demonstrate their efficiency.

  • 13.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Process-variation and Temperature Aware SoC Test Scheduling Technique2013In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 29, no 4, 499-520 p.Article in journal (Refereed)
    Abstract [en]

    High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.

  • 14.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Process-Variation Aware Multi-temperature Test Scheduling2014In: 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, IEEE conference proceedings, 2014, 32-37 p.Conference paper (Refereed)
    Abstract [en]

    Chips manufactured with deep sub micron technologies are prone to large process variation and temperature-dependent defects. In order to provide high test efficiency, the tests for temperature-dependent defects should be applied at appropriate temperature ranges. Existing static scheduling techniques achieve these specified temperatures by scheduling the tests, specially developed heating sequences, and cooling intervals together. Because of the temperature uncertainty induced by process variation, a static test schedule is not capable of applying the tests at intended temperatures in an efficient manner. As a result the test cost will be very high. In this paper, an adaptive test scheduling method is introduced that utilizes on-chip temperature sensors in order to adapt the test schedule to the actual temperatures. The proposed method generates a low cost schedule tree based on the variation statistics and thermal simulations in the design phase. During the test, a chip selects an appropriate schedule dynamically based on temperature sensor readings. A 23% decrease in the likelihood that tests are not applied at the intended temperatures is observed in the experimental studies in addition to 20% reduction in test application time.

  • 15.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Temperature-Gradient Based Burn-In for 3D Stacked ICs2013In: The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed)., 2013Conference paper (Other academic)
    Abstract [en]

    3D Stacked IC fabrication, using Through-Silicon-Vias, is a promising technology for future integrated circuits. However, large temperature gradients may exacerbate early-life-failures to the extent that the commercialization of 3D Stacked ICs is challenged. The effective detection of these early-life-failures requires that burn-in is performed when the IC’s temperatures comply with the thermal maps that properly specify the temperature gradients. In this paper, two methods that efficiently generate and maintain the specified thermal maps are proposed. The thermal maps are achieved by applying heating and cooling intervals to the chips under test through test access mechanisms. Therefore, no external heating system is required. The scheduling of the heating and cooling intervals is based on thermal simulations. The schedule generation is guided by functions that are derived from the temperature equations. Experimental results demonstrate the efficiency of the proposed method.

  • 16.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Temperature-Gradient Based Test Scheduling for 3D Stacked ICs2013In: 2013 IEEE International Conference on Electronics, Circuits, and Systems, IEEE conference proceedings, 2013, 405-408 p.Conference paper (Refereed)
    Abstract [en]

    Defects that are dependent on temperature-gradients (e.g., delay-faults) introduce a challenge for achieving an effective test process, in particular for 3D ICs. Testing for such defects must be performed when the proper temperature gradients are enforced on the IC, otherwise these defects may escape the test. In this paper, a technique that efficiently heats up the IC during test so that it complies with the specified temperature gradients is proposed. The specified temperature gradients are achieved by applying heating sequences to the cores of the IC under test trough test access mechanism; thus no external heating mechanism is required. The scheduling of the test and heating sequences is based on thermal simulations. The schedule generation is guided by functions derived from the IC's temperature equation. Experimental results demonstrate that the proposed technique offers considerable test time savings.

  • 17.
    Aghaee, Nima
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs2015In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, 2992-3005 p.Article in journal (Refereed)
    Abstract [en]

    Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3-D stacked ICs (3-D SICs) compared with 2-D ICs because of the larger temperature gradients in 3-D SICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high-power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. The experimental results demonstrate the efficiency of the proposed methods.

  • 18.
    Aghighi, Meysam
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Computational Complexity of some Optimization Problems in Planning2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Automated planning is known to be computationally hard in the general case. Propositional planning is PSPACE-complete and first-order planning is undecidable. One method for analyzing the computational complexity of planning is to study restricted subsets of planning instances, with the aim of differentiating instances with varying complexity. We use this methodology for studying the computational complexity of planning. Finding new tractable (i.e. polynomial-time solvable) problems has been a particularly important goal for researchers in the area. The reason behind this is not only to differentiate between easy and hard planning instances, but also to use polynomial-time solvable instances in order to construct better heuristic functions and improve planners. We identify a new class of tractable cost-optimal planning instances by restricting the causal graph. We study the computational complexity of oversubscription planning (such as the net-benefit problem) under various restrictions and reveal strong connections with classical planning. Inspired by this, we present a method for compiling oversubscription planning problems into the ordinary plan existence problem. We further study the parameterized complexity of cost-optimal and net-benefit planning under the same restrictions and show that the choice of numeric domain for the action costs has a great impact on the parameterized complexity. We finally consider the parameterized complexity of certain problems related to partial-order planning. In some applications, less restricted plans than total-order plans are needed. Therefore, a partial-order plan is being used instead. When dealing with partial-order plans, one important question is how to achieve optimal partial order plans, i.e. having the highest degree of freedom according to some notion of flexibility. We study several optimization problems for partial-order plans, such as finding a minimum deordering or reordering, and finding the minimum parallel execution length.

    List of papers
    1. Oversubscription planning: Complexity and compilability
    Open this publication in new window or tab >>Oversubscription planning: Complexity and compilability
    2014 (English)In: Proceedings of the Twenty-Eighth AAAI Conference on Artificial Intelligence, AI Access Foundation , 2014, Vol. 3, 2221-2227 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    Many real-world planning problems are oversubscription problems where all goals are not simultaneously achievable and the planner needs to find a feasible subset. We present complexity results for the so-called partial satisfaction and net benefit problems under various restrictions; this extends previous work by van den Briel et al. Our results reveal strong connections between these problems and with classical planning. We also present a method for efficiently compiling oversubscription problems into the ordinary plan existence problem; this can be viewed as a continuation of earlier work by Keyder and Geffner.

    Place, publisher, year, edition, pages
    AI Access Foundation, 2014
    National Category
    Computer and Information Science
    Identifiers
    urn:nbn:se:liu:diva-116727 (URN)2-s2.0-84908192348 (Scopus ID)9781577356790 (ISBN)
    Conference
    28th AAAI Conference on Artificial Intelligence, AAAI 2014, 26th Innovative Applications of Artificial Intelligence Conference, IAAI 2014 and the 5th Symposium on Educational Advances in Artificial Intelligence, EAAI 2014
    Available from: 2015-04-09 Created: 2015-04-02 Last updated: 2017-05-17
    2. Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs
    Open this publication in new window or tab >>Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs
    2015 (English)In: Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, AAAI Press, 2015Conference paper, Published paper (Refereed)
    Abstract [en]

    Causal graphs are widely used to analyze the complexity of planning problems. Many tractable classes have been identified with their aid and state-of-the-art heuristics have been derived by exploiting such classes. In particular, Katz and Keyder have studied causal graphs that are hourglasses (which is a generalization of forks and inverted-forks) and shown that the corresponding cost-optimal planning problem is tractable under certain restrictions. We continue this work by studying polytrees (which is a generalization of hourglasses) under similar restrictions. We prove tractability of cost-optimal planning by providing an algorithm based on a novel notion of variable isomorphism. Our algorithm also sheds light on the k-consistency procedure for identifying unsolvable planning instances. We speculate that this may, at least partially, explain why merge-and-shrink heuristics have been successful for recognizing unsolvable instances.

    Place, publisher, year, edition, pages
    AAAI Press, 2015
    Series
    Proceedings of the AAAI Conference on Artificial Intelligence, ISSN 2159-5399, E-ISSN 2374-3468
    Keyword
    automated planning, causal graph, polynomial-time algorithm, cost-optimal planning, polytree
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-118729 (URN)978-1-57735-703-2 (ISBN)
    Conference
    29th AAAI Conference on Artificial Intelligence (AAAI-15), January 25–30, Austin, TX, USA
    Funder
    CUGS (National Graduate School in Computer Science)
    Available from: 2015-06-03 Created: 2015-06-03 Last updated: 2017-05-17
    3. Cost-optimal and Net-benefit Planning--A Parameterised Complexity View
    Open this publication in new window or tab >>Cost-optimal and Net-benefit Planning--A Parameterised Complexity View
    2015 (English)In: 24th International Joint Conference on Artificial Intelligence (IJCAI-15), 2015Conference paper, Published paper (Refereed)
    Abstract [en]

    Cost-optimal planning (COP) uses action costs and asks for a minimum-cost plan. It is sometimes assumed that there is no harm in using actions with zero cost or rational cost. Classical complexity analysis does not contradict this assumption; planning is PSPACE-complete regardless of whether action costs are positive or non-negative, integer or rational. We thus apply parameterised complexity analysis to shed more light on this issue. Our main results are the following. COP is W[2]-complete for positive integer costs, i.e. it is no harder than finding a minimum-length plan, but it is para-NPhard if the costs are non-negative integers or positive rationals. This is a very strong indication that the latter cases are substantially harder. Net-benefit planning (NBP) additionally assigns goal utilities and asks for a plan with maximum difference between its utility and its cost. NBP is para-NP-hard even when action costs and utilities are positive integers, suggesting that it is harder than COP. In addition, we also analyse a large number of subclasses, using both the PUBS restrictions and restricting the number of preconditions and effects.

    National Category
    Transport Systems and Logistics
    Identifiers
    urn:nbn:se:liu:diva-128181 (URN)9781577357384 (ISBN)
    Conference
    24th International Joint Conference on Artificial Intelligence (IJCAI-15)
    Funder
    CUGS (National Graduate School in Computer Science), 1054Swedish Research Council, 621- 2014-4086
    Available from: 2016-05-20 Created: 2016-05-20 Last updated: 2017-10-06Bibliographically approved
    4. A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning
    Open this publication in new window or tab >>A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning
    2016 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    Aghighi and Bäckström have previously studied cost-optimal planning (COP) and net-benefit planning (NBP) for three action cost domains: the positive integers (Z_+), the non-negative integers (Z_0) and the positive rationals (Q_+). These were indistinguishable under standard complexity analysis for both problems, but separated for COP using parameterised complexity analysis. With the plan cost, k, as parameter, COP was W[2]-complete for Z_+, but para-NP-hard for both Z_0 and Q_+, i.e. presumably much harder. NBP was para-NP-hard for all three domains, thus remaining unseparable. We continue by considering combinations with several additional parameters and also the non-negative rationals (Q_0). Examples of new parameters are the plan length, l, and the largest denominator of the action costs, d. Our findings include: (1) COP remains W[2]-hard for all domains, even if combining all parameters; (2) COP for Z_0 is in W[2] for the combined parameter {k,l}; (3) COP for Q_+ is in W[2] for {k,d} and (4) COP for Q_0 is in W[2] for {k,d,l}. For NBP we consider further additional parameters, where the most crucial one for reducing complexity is the sum of variable utilities. Our results help to understand the previous results, eg. the separation between Z_+ and Q_+ for COP, and to refine the previous connections with empirical findings.

    Place, publisher, year, edition, pages
    AAAI Press, 2016
    Keyword
    cost-optimal planning, parameterised complexity, numeric domains
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-136278 (URN)9781577357575 (ISBN)
    Conference
    Twenty-Sixth International Conference on Automated Planning and Scheduling (ICAPS-16)
    Available from: 2017-04-05 Created: 2017-04-05 Last updated: 2017-10-06
    5. Plan Reordering and Parallel Execution -- A Parameterized Complexity View
    Open this publication in new window or tab >>Plan Reordering and Parallel Execution -- A Parameterized Complexity View
    2017 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    Bäckström has previously studied a number of optimization problems for partial-order plans, like finding a minimum deordering (MCD) or reordering (MCR), and finding the minimum parallel execution length (PPL), which are all NP-complete. We revisit these problems, but applying parameterized complexity analysis rather than standard complexity analysis. We consider various parameters, including both the original and desired size of the plan order, as well as its width and height. Our findings include that MCD and MCR are W[2]-hard and in W[P] when parameterized with the desired order size, and MCD is fixed-parameter tractable (fpt) when parameterized with the original order size. Problem PPL is fpt if parameterized with the size of the non-concurrency relation, but para-NP-hard in most other cases. We also consider this problem when the number (k) of agents, or processors, is restricted, finding that this number is a crucial parameter; this problem is fixed-parameter tractable with the order size, the parallel execution length and k as parameter, but para-NP-hard without k as parameter.

    Place, publisher, year, edition, pages
    AAAI Press, 2017
    Keyword
    Partially ordered plan, Parameterized complexity, Complexity of planning, Plan reordering, Parallel plan execution
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-136279 (URN)
    Conference
    Thirty-First AAAI Conference on Artificial Intelligence (AAAI-17)
    Available from: 2017-04-05 Created: 2017-04-05 Last updated: 2017-05-17Bibliographically approved
  • 19.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning2016Conference paper (Refereed)
    Abstract [en]

    Aghighi and Bäckström have previously studied cost-optimal planning (COP) and net-benefit planning (NBP) for three action cost domains: the positive integers (Z_+), the non-negative integers (Z_0) and the positive rationals (Q_+). These were indistinguishable under standard complexity analysis for both problems, but separated for COP using parameterised complexity analysis. With the plan cost, k, as parameter, COP was W[2]-complete for Z_+, but para-NP-hard for both Z_0 and Q_+, i.e. presumably much harder. NBP was para-NP-hard for all three domains, thus remaining unseparable. We continue by considering combinations with several additional parameters and also the non-negative rationals (Q_0). Examples of new parameters are the plan length, l, and the largest denominator of the action costs, d. Our findings include: (1) COP remains W[2]-hard for all domains, even if combining all parameters; (2) COP for Z_0 is in W[2] for the combined parameter {k,l}; (3) COP for Q_+ is in W[2] for {k,d} and (4) COP for Q_0 is in W[2] for {k,d,l}. For NBP we consider further additional parameters, where the most crucial one for reducing complexity is the sum of variable utilities. Our results help to understand the previous results, eg. the separation between Z_+ and Q_+ for COP, and to refine the previous connections with empirical findings.

  • 20.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Cost-optimal and Net-benefit Planning--A Parameterised Complexity View2015In: 24th International Joint Conference on Artificial Intelligence (IJCAI-15), 2015Conference paper (Refereed)
    Abstract [en]

    Cost-optimal planning (COP) uses action costs and asks for a minimum-cost plan. It is sometimes assumed that there is no harm in using actions with zero cost or rational cost. Classical complexity analysis does not contradict this assumption; planning is PSPACE-complete regardless of whether action costs are positive or non-negative, integer or rational. We thus apply parameterised complexity analysis to shed more light on this issue. Our main results are the following. COP is W[2]-complete for positive integer costs, i.e. it is no harder than finding a minimum-length plan, but it is para-NPhard if the costs are non-negative integers or positive rationals. This is a very strong indication that the latter cases are substantially harder. Net-benefit planning (NBP) additionally assigns goal utilities and asks for a plan with maximum difference between its utility and its cost. NBP is para-NP-hard even when action costs and utilities are positive integers, suggesting that it is harder than COP. In addition, we also analyse a large number of subclasses, using both the PUBS restrictions and restricting the number of preconditions and effects.

  • 21.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Plan Reordering and Parallel Execution -- A Parameterized Complexity View2017Conference paper (Refereed)
    Abstract [en]

    Bäckström has previously studied a number of optimization problems for partial-order plans, like finding a minimum deordering (MCD) or reordering (MCR), and finding the minimum parallel execution length (PPL), which are all NP-complete. We revisit these problems, but applying parameterized complexity analysis rather than standard complexity analysis. We consider various parameters, including both the original and desired size of the plan order, as well as its width and height. Our findings include that MCD and MCR are W[2]-hard and in W[P] when parameterized with the desired order size, and MCD is fixed-parameter tractable (fpt) when parameterized with the original order size. Problem PPL is fpt if parameterized with the size of the non-concurrency relation, but para-NP-hard in most other cases. We also consider this problem when the number (k) of agents, or processors, is restricted, finding that this number is a crucial parameter; this problem is fixed-parameter tractable with the order size, the parallel execution length and k as parameter, but para-NP-hard without k as parameter.

  • 22.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Jonsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ståhlberg, Simon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Analysing Approximability and Heuristics in Planning Using the Exponential-Time Hypothesis2016In: ECAI 2016: 22ND EUROPEAN CONFERENCE ON ARTIFICIAL INTELLIGENCE, IOS Press, 2016, Vol. 285, 184-192 p.Conference paper (Refereed)
    Abstract [en]

    Cost-optimal planning has become a very well-studied topic within planning. Needless to say, cost-optimal planning has proven to be computationally hard both theoretically and in practice. Since cost-optimal planning is an optimisation problem, it is natural to analyse it from an approximation point of view. Even though such studies may be valuable in themselves, additional motivation is provided by the fact that there is a very close link between approximability and the performance of heuristics used in heuristic search. The aim of this paper is to analyse approximability (and indirectly the performance of heuristics) with respect to lower time bounds. That is, we are not content by merely classifying problems into complexity classes - we also study their time complexity. This is achieved by replacing standard complexity-theoretic assumptions (such as P not equal NP) with the exponential time hypothesis (ETH). This enables us to analyse, for instance, the performance of the h(+) heuristic and obtain general trade-off results that correlate approximability bounds with bounds on time complexity.

  • 23.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Jonsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ståhlberg, Simon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Refining complexity analyses in planning by exploiting the exponential time hypothesis2016In: Annals of Mathematics and Artificial Intelligence, ISSN 1012-2443, E-ISSN 1573-7470, Vol. 78, no 2, 157-175 p.Article in journal (Refereed)
    Abstract [en]

    The use of computational complexity in planning, and in AI in general, has always been a disputed topic. A major problem with ordinary worst-case analyses is that they do not provide any quantitative information: they do not tell us much about the running time of concrete algorithms, nor do they tell us much about the running time of optimal algorithms. We address problems like this by presenting results based on the exponential time hypothesis (ETH), which is a widely accepted hypothesis concerning the time complexity of 3-SAT. By using this approach, we provide, for instance, almost matching upper and lower bounds onthe time complexity of propositional planning.

  • 24.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jonsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Oversubscription planning: Complexity and compilability2014In: Proceedings of the Twenty-Eighth AAAI Conference on Artificial Intelligence, AI Access Foundation , 2014, Vol. 3, 2221-2227 p.Conference paper (Refereed)
    Abstract [en]

    Many real-world planning problems are oversubscription problems where all goals are not simultaneously achievable and the planner needs to find a feasible subset. We present complexity results for the so-called partial satisfaction and net benefit problems under various restrictions; this extends previous work by van den Briel et al. Our results reveal strong connections between these problems and with classical planning. We also present a method for efficiently compiling oversubscription problems into the ordinary plan existence problem; this can be viewed as a continuation of earlier work by Keyder and Geffner.

  • 25.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jonsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ståhlberg, Simon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs2015In: Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, AAAI Press, 2015Conference paper (Refereed)
    Abstract [en]

    Causal graphs are widely used to analyze the complexity of planning problems. Many tractable classes have been identified with their aid and state-of-the-art heuristics have been derived by exploiting such classes. In particular, Katz and Keyder have studied causal graphs that are hourglasses (which is a generalization of forks and inverted-forks) and shown that the corresponding cost-optimal planning problem is tractable under certain restrictions. We continue this work by studying polytrees (which is a generalization of hourglasses) under similar restrictions. We prove tractability of cost-optimal planning by providing an algorithm based on a novel notion of variable isomorphism. Our algorithm also sheds light on the k-consistency procedure for identifying unsolvable planning instances. We speculate that this may, at least partially, explain why merge-and-shrink heuristics have been successful for recognizing unsolvable instances.

  • 26.
    Ahlgren, Simon
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Aini, Daniel
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Conversion and Analysis of Telemetric Data from the CCSDS Standard2017Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    When communicating with spacecrafts, the international standard is to use the protocols defined by CCSDS. In this study, the Space Packet Protocol from CCSDS is converted to the Digital Recording Standard used in aviation. The goal of the study is to find out in what way such a conversion can be made, as well as analyzing the efficiency of different packing methods for the Digital Recording Standard. An application is developed in order to perform the conversion, and the performance of said application is profiled using different packet sizes. In the end the results are evaluated and an optimal packet size is found in terms of runtime and memory usage. In the end we conclude that a packet size of 216 bytes is best when prioritizing speed, and a packet size of 219 bytes is best when prioritizing memory.

  • 27.
    Alesand, Alexander
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Emulating 3G Network Characteristics on WiFi Networks2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Mobile applications should work regardless of which type of wireless interface is used, and should be able to conceal unstable connections from the user to improve user experience. Therefore, network testing is important when developing mobile applications, but it is a challenge to reproduce network conditions when using real cellular networks since the test engineer has no control over the quality of the cellular network. Existing software tools can restrict bandwidth and add latency to the connection, but these tools do not accurately emulate cellular networks.

    This thesis proposes a system where it is possible to shape the network traffic for connected devices to mimic the network patterns of a real cellular connection when running on a WiFi connection. The design presented in this thesis is intended for testing mobile applications under diverse 3G connection parameters, such as latency, bandwidth and other characteristics.

    This thesis was conducted at Spotify, a company that provides a music streaming service which is a frequent user of network data traffic. The 3G emulator was evaluated using the Spotify Android application by measuring the correlation between packet traces from a real 3G connection and the 3G emulator. This correlation was compared to the correlation between packet traces from a real 3G connection and the current network emulator at Spotify. The evaluation shows that the proposed 3G emulator outperforms the current network emulator when performing tests on the Spotify application for Android. By using this emulator, we expect the network testing to become more effective as any 3G condition can be tested with repeatable results.

  • 28.
    Alesand, Alexander
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Vergara, Ekhiotz Jon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Nadjm-Tehrani, Simin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Communication Energy Evaluation for Mobile Applications: Emulating 3G over WiFi2016In: ProceedingENERGY-SIM '16 Proceedings of the 2nd International Workshop on Energy-Aware Simulation, ACM Digital Library, 2016Conference paper (Refereed)
    Abstract [en]

    Ubiquitous connectivity and massive use of mobile applications are currently hampered by fast battery drain of mobile devices. The communication energy of a mobile device is highly inuenced by the cellular operator conguration and the communication data pattern. Although testing the functionality and eciency of an application under diverse and realistic network settings is desirable, it is currently limited at the application developer test environment. It is generally hard to mimic di erent operator (infrastructure) settings that impact battery drain. In this paper we propose a system that creates a realistic cellular network testing environment for mobile applications on top of a WiFi network. A mobile device connects via WiFi to an emulator which shapes the uplink and downlink WiFi trac using real cellular operator conguration parameters. The system provides higher test repeatability compared to live networks and can be congured to emulate diverse cellular network parameters. These parameters, which determine the energy consumption, can be changed modularly and eciently. The evaluation of the resulting trac of the emulator compared to real cellular packet races from a streaming application shows a high correlation (0.97-0.98). The work has resulted in integration of the emulator within Spotify's test environment.

  • 29.
    Alfredsson, Marcus
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Lundmark, Eric
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Workflow graph editing and visualization in HTML5 and Javascript2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Being able to run applications written in a single language on multiple platforms is a strong incentive for migrating applications to the web. This along with the possibility to avoid the sometimes problematic procedure of installing software, makes the case even stronger. This thesis investigates how to migrate a workflow graph editing system into a web technology in order to publish it on the web. We will evaluate a number of different technologies such as WebGL, HTML5 canvas and SVG. SVG is deemed as the preferred technology due to its advantages when it comes to interaction. As it can leverage JavaScripts event system we get a potent way of handling events without writing a single line of code. When combining this with the framework D3JS we achieve a great tool for writing workflow management systems.

  • 30.
    Ali, Akhtar
    et al.
    Linköping University, The Institute of Technology.
    Dastgeer, Usman
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Kessler, Christoph
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    OpenCL for programming shared memory multicore CPUs2012In: Proceedings of the 5th Workshop on MULTIPROG2012 / [ed] E. Ayguade, B. Gaster, L. Howes, P. Stenström, O. Unsal, HiPEAC Network of Excellence , 2012Conference paper (Refereed)
    Abstract [en]

    Shared memory multicore processor technology is pervasive in mainstream computing. This new architecture challenges programmers to write code that scales over these many cores to exploit the full computational power of these machines. OpenMP and Intel Threading Building Blocks (TBB) are two of the popular frameworks used to program these architectures. Recently, OpenCL has been defined as a standard by Khronos group which focuses on programming a possibly heterogeneous set of processors with many cores such as CPU cores, GPUs, DSP processors. In this work, we evaluate the effectiveness of OpenCL for programming multicore CPUs in a comparative case study with OpenMP and Intel TBB for five benchmark applications: matrix multiply, LU decomposition,2D image convolution, Pi value approximation and image histogram generation. The evaluation includes the effect of compiler optimizations for different frameworks, OpenCL performance on different vendors’ platformsand the performance gap between CPU-specific and GPU-specific OpenCL algorithms for execution on a modern GPU. Furthermore, a brief usability evaluation of the three frameworks is also presented.

  • 31.
    Ali, Akhtar
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Dastgeer, Usman
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Kessler, Christoph
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    OpenCL for programming shared memory multicore CPUs2011In: Fourth Swedish Workshop on Multi-Core Computing MCC-2011: November 23-25, 2011, Linköping University, Linköping, Sweden / [ed] Christoph Kessler, Linköping: Linköping University , 2011, Vol. S. 65-70, 65-70 p.Conference paper (Other academic)
    Abstract [en]

    In this work, we evaluate the effectiveness of OpenCL for programming multicore CPUs in a comparative case study with OpenMP and Intel TBB for five benchmark applications: matrix multiply, LU decomposition, 2D image convolution, Pi value approximation and image histogram generation.

  • 32.
    Almquist, Mathias
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Almquist, Viktor
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    A study on Android games: 3G energy consumption, CPU-utilization and system calls2015Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    The popularity of mobile games has increased drastically during the recent years andmany people use them as their main source of entertainment. Mobile gamescommunicate with other devices over the network which consumes a lot of energy,especially when connected to cellular networks (e.g., 3G). This high energy expensecan feel unjustified to the player since always-on network connectivity is not requiredin order to play most games.Furthermore, the number of malware-infected applications in offical applicationstores has increased significantly in the recent years. These malware-infectedapplications can gain unrestricted access and control of users phones which can be athreat to security. Information about the behaviour characteristics of games can beused to develop or improve systems for detecting malware applications.In this thesis, 20 popular Android games are analysed with a focus on the datacommunication, CPU utilization and system call behaviour. The main subject of thedata communication study is the 3G communication energy consumed by games. Thesystem call study aims at quantifying the number and type of calls used by games.This may be useful in a further study of harmful behaviour by apps.The profiling results presented in this report show that the communication energyvaries drastically among games. Games with a very similar gameplay can consumevery different amounts of energy which indicates that there is room for improvementsin many of the games. Ad-free games consume significantly less energy than gamesthat use in-app advertisements. The results show that improving the advertisementfetching policy could reduce the energy consumption of these games. The majority ofthe games can be played without network connectivity and therefore thecommunication energy consumed could be completely avoided. The thesis alsoshows that games use a wide variety of system calls and that many of the system callsare common among the games.

  • 33.
    Almquist, Mathias
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, Faculty of Science & Engineering.
    Almquist, Viktor
    Linköping University, Department of Computer and Information Science. Linköping University, Faculty of Science & Engineering.
    Vergara Alonso, Ekhiotz Jon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Nadjm-Tehrani, Simin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Communication Energy Overhead of Mobiles Games2015In: MobiGames '15: Proceedings of the 2nd Workshop on Mobile Gaming, Association for Computing Machinery (ACM), 2015, 1-6 p.Conference paper (Other academic)
    Abstract [en]

    Although a significant proportion of the mobile apps are games there has been little attention paid to their specific characteristics with respect to communication energy. In this paper we select 20 mobile games among the top 100 free Android games, and study their data patterns and communication energy use over a total of 25 hours of playing. The analysis of the energy for communication over 3G networks indicates that there is a wide variation among the games, the largest footprint being 8 times higher than the lowest one. The results also indicates both app-specific and category-specific relations between data pattern and energy use, as well as variations in CPU utilisation.

  • 34.
    Alnervik, Erik
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Evaluation of the Configurable Architecture REPLICA with Emulated Shared Memory2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    REPLICA is a family of novel scalable chip multiprocessors with configurable emulated shared memory architecture, whose computation model is based on the PRAM (Parallel Random Access Machine) model.

    The purpose of this thesis is to, by benchmarking different types of computation problems on REPLICA, similar parallel architectures (SB-PRAM and XMT) and more diverse ones (Xeon X5660 and Tesla M2050), evaluate how REPLICA is positioned among other existing architectures, both in performance and programming effort. But it should also examine if REPLICA is more suited for any special kinds of computational problems.

    By using some of the well known Berkeley dwarfs, and input from unbiased sources, such as The University of Florida Sparse Matrix Collection and Rodinia benchmark suite, we have made sure that the benchmarks measure relevant computation problems.

    We show that today’s parallel architectures have some performance issues for applications with irregular memory access patterns, which the REPLICA architecture can solve. For example, REPLICA only need to be clocked with a few MHz to match both Xeon X5660 and Tesla M2050 for the irregular memory access benchmark breadth first search. By comparing the efficiency of REPLICA to a CPU (Xeon X5660), we show that it is easier to program REPLICA efficiently than today’s multiprocessors.

  • 35.
    Al-Omaishe, Allaa
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. 860418-9061.
    The impacts of adopting large touch screens and tablets with access  to electronic healthcare records2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In the last decade modern information technology systems have been introduced to healthcare in order to improve it. The aim of this study is to present the impact of such information system’s adoption on patient safety and efficiency within healthcare.

    Interviews, observations along with literature study were conducted in order to study the impact of the adoption on patient safety and efficiency at hospital’s wards where a new information system is implemented.

    The conclusion of this study is that such information technology systems can improve patient safety. However it is believed that the information technology system can improve efficiency in some aspects such as the communication among medical care personnel while other aspects within efficiency can be achieved if some improvements are made. Moreover the ability to access Electronic Healthcare Records is considered to be important to improve the medical care, which can increase patient safety. 

  • 36.
    Aminifar, Amir
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Analysis, Design, and Optimization of Embedded Control Systems2016Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Today, many embedded or cyber-physical systems, e.g., in the automotive domain, comprise several control applications, sharing the same platform. It is well known that such resource sharing leads to complex temporal behaviors that degrades the quality of control, and more importantly, may even jeopardize stability in the worst case, if not properly taken into account.

    In this thesis, we consider embedded control or cyber-physical systems, where several control applications share the same processing unit. The focus is on the control-scheduling co-design problem, where the controller and scheduling parameters are jointly optimized. The fundamental difference between control applications and traditional embedded applications motivates the need for novel methodologies for the design and optimization of embedded control systems. This thesis is one more step towards correct design and optimization of embedded control systems.

    Offline and online methodologies for embedded control systems are covered in this thesis. The importance of considering both the expected control performance and stability is discussed and a control-scheduling co-design methodology is proposed to optimize control performance while guaranteeing stability. Orthogonal to this, bandwidth-efficient stabilizing control servers are proposed, which support compositionality, isolation, and resource-efficiency in design and co-design. Finally, we extend the scope of the proposed approach to non-periodic control schemes and address the challenges in sharing the platform with self-triggered controllers. In addition to offline methodologies, a novel online scheduling policy to stabilize control applications is proposed.

  • 37.
    Aminifar, Amir
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Self-Triggered Controllers, Resource Sharing, and Hard Guarantees2016In: 2016 2ND INTERNATIONAL CONFERENCE ON EVENT-BASED CONTROL, COMMUNICATION, AND SIGNAL PROCESSING (EBCCSP), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    Today, many control applications in embedded and cyber-physical systems are implemented on shared platforms, alongside other hard real-time or safety-critical applications. Having the resource shared among several applications, to provide hard guarantees, it is required to identify the amount of resource needed for each application. This is rather straightforward when the platform is shared among periodic control and periodic real-time applications. In the case of event-triggered and self-triggered controllers, however, the execution patterns and, in turn, the resource usage are not clear. Therefore, a major implementation challenge, when the platform is shared with self-triggered controllers, is to provide hard and efficient stability and schedulability guarantees for other applications. In this paper, we identify certain execution patterns for self-triggered controllers, using which we are able to provide hard and efficient stability guarantees for periodic control applications.

  • 38.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bini, Enrico
    Scuola Super Sant Anna, Italy.
    Eles, Petru lon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Analysis and Design of Real-Time Servers for Control Applications2016In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, 834-846 p.Article in journal (Refereed)
    Abstract [en]

    Today, a considerable portion of embedded systems, e.g., automotive and avionic, comprise several control applications. Guaranteeing the stability of these control applications in embedded systems, or cyber-physical systems, is perhaps the most fundamental requirement while implementing such applications. This is different from the classical hard real-time systems where often the acceptance criterion is meeting the deadline. In other words, in the case of control applications, guaranteeing stability is considered to be a main design goal, which is linked to the amount of delay and jitter a control application can tolerate before instability. This advocates the need for new design and analysis techniques for embedded real-time systems running control applications. In this paper, the analysis and design of such systems considering a server-based resource reservation mechanism are addressed. The benefits of employing servers are manifold: providing a compositional and scalable framework, protection against other tasks misbehaviors, and systematic bandwidth assignment and co-design. We propose a methodology for designing bandwidth-optimal servers to stabilize control tasks. The pessimism involved in the proposed methodology is both discussed theoretically and evaluated experimentally.

  • 39.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bini, Enrico
    Lund University, Sweden.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees2014In: Design, Automation & Test in Europe, DATE 2014, IEEE Computer Society, 2014Conference paper (Refereed)
    Abstract [en]

    Many cyber-physical systems comprise several control applications implemented on a shared platform, for which stability is a fundamental requirement. This is as opposed to the classical hard real-time systems where often the criterion is meeting the deadline. However, the stability of control applications depends on not only the delay experienced, but also the jitter. Therefore, the notion of deadline is considered to be artificial for control applications that promotes the need for new techniques for designing cyber-physical systems. The approach in this paper is built on a server-based resource reservation mechanism, which provides compositionality, isolation, and the opportunity of systematic controller--server co-design. We address the controller--server co-design of such systems to obtain design solutions with the minimal bandwidth to guarantee stability.

  • 40.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bini, Enrico
    Lund University, Sweden.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Designing Bandwidth-Efficient Stabilizing Control Servers2013In: IEEE Real-Time Systems Symposium, RTSS 2013, IEEE , 2013, 298-307 p.Conference paper (Refereed)
    Abstract [en]

    Guaranteeing stability of control applications in embedded systems, or cyber-physical systems, is perhaps the alpha and omega of implementing such applications. However, as opposed to the classical real-time systems where often the acceptance criterion is meeting the deadline, control applications do not primarily enforce hard deadlines. In the case of control applications, stability is considered to be the main design criterion and can be expressed in terms of the amount of delay and jitter a control application can tolerate before instability. Therefore, new design and analysis techniques are required for embedded control systems. In this paper, the analysis and design of such systems considering server-based resource reservation mechanism are addressed. The benefits of employing servers are manifold: (1) providing a compositional framework, (2) protection against other tasks misbehaviors, and (3) systematic bandwidth assignment. We propose a methodology for designing bandwidth-efficient servers to stabilize control tasks.

  • 41.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jfair: A Scheduling Algorithm to Stabilize Control Applications2015In: 21st IEEE Real-Time and Embedded Technology and Applications Symposium, Cyber-Physical Systems Week, Seattle, WA, April 2015, IEEE Computer Society, 2015, 63-72 p.Conference paper (Refereed)
    Abstract [en]

    Control applications are considered to be among the core applications in cyber-physical and embedded realtime systems, for which jitter is typically an important factor. This paper investigates whether it is possible to guarantee certain amount of jitter for a given set of applications on a shared platform. The effect of jitter on the stability of control applications and its relation with the latency will be discussed. The importance arises from the fact that it is considerably easier to manage the constant part of the delay (known as latency), while the process of coping with the varying part of the delay (known as jitter) is more involved. The proposed solution guarantees certain jitter limits, and at the same time does not lead to overly pessimistic latency values. The results are later used in a design optimization problem to minimize the resource utilized.

  • 42.
    Aminifar, Amir
    et al.
    Embedded Systems Laboratory, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland..
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Optimization of Message Encryption for Real-Time Applications in Embedded Systems2017In: IEEE Transactions on Computers, ISSN 0018-9340Article in journal (Refereed)
    Abstract [en]

    Today, security can no longer be treated as a secondary issue in embedded and cyber-physical systems. Therefore, one of the main challenges in these domains is the design of secure embedded systems under stringent resource constraints and real-time requirements. However, there exists an inherent trade-off between the security protection provided and the amount of resources allocated for this purpose. That is, the more the amount of resources used for security, the higher the security, but the fewer the number of applications which can be run on the platform and meet their timing requirements. This trade-off is of high importance since embedded systems are often highly resource constrained. In this paper, we propose an efficient solution to maximize confidentiality, while also guaranteeing the timing requirements of real-time applications on shared platforms.

  • 43.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees2013In: Design, Automation & Test in Europe (DATE 2013), IEEE , 2013, 1093-1098 p.Conference paper (Refereed)
    Abstract [en]

    Many cyber-physical systems comprise several control applications sharing communication and computation resources. The design of such systems requires special attention due to the complex timing behavior that can lead to poor control quality or even instability. The two main requirements of control applications are: (1) robustness and, in particular, stability and (2) high control quality. Although it is essential to guarantee stability and provide a certain degree of robustness even in the worst-case scenario, a design procedure which merely takes the worst-case scenario into consideration can lead to a poor expected (average-case) control quality, since the design is solely tuned to a scenario that occurs very rarely. On the other hand, considering only the expected quality of control does not necessarily provide robustness and stability in the worst-case. Therefore, both the robustness and the expected control quality should be taken into account in the design process. This paper presents an efficient and integrated approach for designing high-quality cyber-physical systems with robustness guarantees.

  • 44.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Cervin, Anton
    Lund University, Sweden.
    Stability-Aware Analysis and Design of Embedded Control Systems2013In: Proceedings of the International Conference on Embedded Software (EMSOFT), 2013, IEEE conference proceedings, 2013, 1-10 p.Conference paper (Refereed)
    Abstract [en]

    Many embedded systems comprise several controllers sharing available resources. It is well known that such resource sharing leads to complex timing behavior that can jeopardize stability of control applications, if it is not properly taken into account in the design process, e.g., mapping and scheduling. As opposed to hard real-time systems where meeting the deadline is a critical requirement, control applications do not enforce hard deadlines. Therefore, the traditional real-time analysis approaches are not readily applicable to control applications. Rather, in the context of control applications, stability is often the main requirement to be guaranteed, and can be expressed as the amount of delay and jitter a control application can tolerate. The nominal delay and response-time jitter can be regarded as the two main factors which relate the real-time aspects of a system to control performance and stability. Therefore, it is important to analyze the impact of variations in scheduling parameters, i.e., period and priority, on the nominal delay and response-time jitter and, ultimately, on stability. Based on such an analysis, we address, in this paper, priority assignment and sensitivity analysis problems for control applications considering stability as the main requirement.

  • 45.
    Aminifar, Amir
    et al.
    Embedded Systems Laboratory, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland..
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Cervin, Anton
    Department of Automatic Control, Lund University, Sweden.
    Årzén, Karl-Erik
    Department of Automatic Control, Lund University, Sweden.
    Control-Quality Driven Design of Embedded Control Systems with Stability Guarantees2017In: IEEE design & test, ISSN 2168-2356, E-ISSN 2168-2364Article in journal (Refereed)
    Abstract [en]

    Today, the majority of control applications in embedded systems, e.g., in the automotive domain, are implemented as software tasks on shared platforms. Ignoring implementation impacts during the design of embedded control systems results in complex timing behaviors that may lead to poor performance and, in the worst case, instability of control applications. This article presents a methodology for implementation-aware design of high-quality and stable embedded control systems on shared platforms with complex timing behaviors.

  • 46.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Samii, Soheil
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, Software and Systems.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Designing High-Quality Embedded Control Systems with Guaranteed Stability2012In: 33rd IEEE Real-Time Systems Symposium (RTSS 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Many embedded systems comprise several controllers sharing available resources. It is well known that such resource sharing leads to complex timing behavior that degrades the quality of control, and more importantly, can jeopardize stability in the worst-case, if not properly taken into account during design. Although stability of the control applications is absolutely essential, a design flow driven by the worst-case scenario often leads to poor control quality due to the significant amount of pessimism involved and the fact that the worst-case scenario occurs very rarely. On the other hand, designing the system merely based on control quality, determined by the expected (average-case) behavior, does not guarantee the stability of control applications in the worst-case. Therefore, both control quality and worst-case stability have to be considered during the design process, i.e., period assignment, task scheduling, and control-synthesis. In this paper, we present an integrated approach for designing high-quality embedded control systems, while guaranteeing their stability.

  • 47.
    Aminifar, Amir
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Tabuada, Paulo
    University of California at Los Angeles, USA.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Self-Triggered Controllers and Hard Real-Time Guarantees2016In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), Institute of Electrical and Electronics Engineers (IEEE), 2016, 636-641 p.Conference paper (Refereed)
    Abstract [en]

    It is well known that event-triggered and self-triggered controllers implemented on dedicated platforms can provide the same performance as the traditional periodic controllers, while consuming considerably less bandwidth. However, since the majority of controllers are implemented by software tasks on shared platforms, on one hand, it might no longer be possible to grant access to the event-triggered controller upon request. On the other hand, due to the seemingly irregular requests from self-triggered controllers, other applications, while in reality schedulable, may be declared unschedulable, if not carefully analyzed. The schedulability and response-time analysis in the presence of self-triggered controllers is still an open problem and the topic of this paper.

  • 48.
    Amlinger, Anton
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    An Evaluation of Clustering and Classification Algorithms in Life-Logging Devices2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Using life-logging devices and wearables is a growing trend in today’s society. These yield vast amounts of information, data that is not directly overseeable or graspable at a glance due to its size. Gathering a qualitative, comprehensible overview over this quantitative information is essential for life-logging services to serve its purpose.

    This thesis provides an overview comparison of CLARANS, DBSCAN and SLINK, representing different branches of clustering algorithm types, as tools for activity detection in geo-spatial data sets. These activities are then classified using a simple model with model parameters learned via Bayesian inference, as a demonstration of a different branch of clustering.

    Results are provided using Silhouettes as evaluation for geo-spatial clustering and a user study for the end classification. The results are promising as an outline for a framework of classification and activity detection, and shed lights on various pitfalls that might be encountered during implementation of such service.

  • 49.
    Anders, Söderholm
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Justus, Sörman
    Linköping University, Department of Computer and Information Science, Software and Systems.
    GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework2016Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Today's computer systems often contains several different processing units aside from the CPU. Among these the GPU is a very common processing unit with an immense compute power that is available in almost all computer systems. How do we make use of this processing power that lies within our machines? One answer is the OpenCL framework that is designed for just this, to open up the possibilities of using all the different types of processing units in a computer system. This thesis will discuss the advantages and disadvantages of using the integrated GPU available in a basic workstation computer for computation of image processing and sorting algorithms. These tasks are computationally intensive and the authors will analyze if an integrated GPU is up to the task of accelerating the processing of these algorithms. The OpenCL framework makes it possible to run one implementation on different processing units, to provide perspective we will benchmark our implementations on both the GPU and the CPU and compare the results. A heterogeneous approach that combines the two above mentioned processing units will also be tested and discussed. The OpenCL framework is analyzed from a development perspective and what advantages and disadvantages it brings to the development process will be presented.

  • 50.
    Anderson, Jonathan
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Visualisation of data from IoT systems: A case study of a prototyping tool for data visualisations2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The client in this study, Attentec, has seen an increase in the demand for services connected to Internet of things systems. This study is therefore examining if there is a tool that can be a used to build fast prototype visualisations of data from IoT systems to use as a tool in their daily work.

    The study started with an initial phase with two parts. The first part was to get better knowledge of Attentec and derive requirements for the tool and the second part was a comparison of prototyping tools for aiding in development of data visualisations. Apache Zeppelin was chosen as the most versatile and suitable tool matching the criteria defined together with Attentec. Following the initial phase a pre-study containing interviews to collect empirical data on how visualisations and IoT projects had been implemented previously at Attentec were performed. This lead to the conclusion that geospatial data and NoSQL databases were common for IoT projects. A technical investigation was conducted on Apache Zeppelin to answer if there were any limits in using the tool for characteristics common in IoT system. This investigation lead to the conclusion that there was no support for plotting data on a map.

    The first implementation phase implemented support for geospatial data by adding a visualisation plug-in that plotted data on a map. The implementation phase was followed by an evaluation phase in which 5 participants performed tasks with Apache Zeppelin to evaluate the perceived usability of the tool. The evaluation was performed using a System Usability Scale and a Summed Usability Metric as well as interviews with the participants to find where improvements could be made. From the evaluation three main problems were discovered, the import and mapping of data, more feature on the map visualisation plug-in and the creation of database queries. The first two were chosen for the second iteration where a script for generating the code to import data was developed as well as improvements to the geospatial visualisation plug-in. A second evaluation was performed after the changes were made using similar tasks as in the first to see if the usability was improved between the two evaluations. The results of the Summed Usability Metric improved on all tasks and the System Usability Scale showed no significant change. In the interviews with the participants they all responded that the perceived usability had improved between the two evaluations suggesting some improvement.

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