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  • 1.
    Henriksson, Tomas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    VLSI Implementation of CRC-32 for 10 Gigabit Ethernet2001In: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, p. 1215-1218Conference paper (Refereed)
    Abstract [en]

    For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

  • 2.
    Henriksson, Tomas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Configurable Port Processor Increases Flexibility in the Protocol Processing Area2000In: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, p. 275-Conference paper (Other academic)
    Abstract [en]

    The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

    (...)

  • 3.
    Henriksson, Tomas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nordqvist, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Embedded Protocol Processor for Fast and Efficient Packet Reception2002In: International Conference on Computer Design,2002, 2002, p. 414-Conference paper (Refereed)
  • 4.
    Henriksson, Tomas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Specification of a configurable general-purpose protocol processor2000In: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, p. 284-289Conference paper (Other academic)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

  • 5.
    Henriksson, Tomas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Specification of a configurable general-purpose protocol processor2002In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 3, p. 198-202Article in journal (Refereed)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

  • 6.
    Liu, Dake
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Configuration-based architecture for high speed and general-purpose protocol processing1999In: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, p. 540-547Conference paper (Refereed)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

  • 7.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    A Programmable Network Interface Accelerator2003Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

    In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

    A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

    The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

    List of papers
    1. Configuration-based architecture for high speed and general-purpose protocol processing
    Open this publication in new window or tab >>Configuration-based architecture for high speed and general-purpose protocol processing
    1999 (English)In: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, p. 540-547Conference paper, Published paper (Refereed)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-100980 (URN)10.1109/SIPS.1999.822360 (DOI)
    Conference
    SIPS 1999, 20-22 October. Taipei, Taiwan
    Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2013-11-15
    2. CRC generation for protocol processing
    Open this publication in new window or tab >>CRC generation for protocol processing
    2000 (English)In: Proceedings of NORCHIP 2000, 2000, p. 288-293Conference paper, Published paper (Refereed)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-100981 (URN)
    Conference
    18th NORCHIP Conference, 6-7 November, 2000, Turku, Finland
    Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2014-12-19
    3. Packet Classification and Termination in a Protocol Processor
    Open this publication in new window or tab >>Packet Classification and Termination in a Protocol Processor
    2003 (English)Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-33275 (URN)19275 (Local ID)19275 (Archive number)19275 (OAI)
    Conference
    Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.
    Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
  • 8.
    Nordqvist, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    On protocol processing.2001In: Conference on Computer Science and Systems Engineering.,2001, 2001, p. 83-89Conference paper (Other academic)
  • 9.
    Nordqvist, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Power Efficient Packer Buffering in a Protocol Processor2003In: Swedish System-onChip Conference,2003, 2003Conference paper (Other academic)
  • 10.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Protocol processing in network terminals2004Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures dedicated for processing of packets and network protocols.

    In the emerging research area of protocol processing, there exist many hardware platform proposals. Most of them aim for router applications, not so many for terminals. As a starting point for terminal research this thesis explores a number of different router design alternatives and some common computer architecture concepts. These concepts and architectures have been examined and evaluated to see if some ideas apply also to protocol processing in network terminals.

    Requirements on protocol processors for terminals can be summarized as:

    • Low silicon area

    • Low power consumption

    • Low processing latency

    • High processing throughput

    • Flexible implementation

    Fulfilling these requirements while supporting offtoading of as much protocol processing as possible to the network interface is the key issue of this thesis. Off-loading means that the protocol processing can be executed in a special unit that does not need to execute the host applications as well. The protocol processor unit basically acts as a smart network interface card.

    A novel terminal platform solution is proposed in this thesis. The dual processor platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, which operate in parallel, to accelerate the platform in a configurable way. These hardware blocks have been selected and specified to fulfill requirements set by a number of common network protocols. To find these requirements, the protocol processing procedure has been investigated and divided into processing tasks. These different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in the other part of the platform which is a general purpose micro controller.

    The dedicated datapath, simplified control, and minimal usage of data buffers make the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled. Different implementation alternatives are provided in this thesis. Which one to select depends on what kind of terminal the platform is going to be used for. Further this thesis includes a discussion around how the ability to reassembly fragmented packets demands architectural modifications.

  • 11.
    Nordqvist, Ulf
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Henriksson, Tomas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Configurable CRC Generator2002In: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, p. 192-Conference paper (Refereed)
  • 12.
    Nordqvist, Ulf
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Henriksson, Tomas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    CRC generation for protocol processing2000In: Proceedings of NORCHIP 2000, 2000, p. 288-293Conference paper (Refereed)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

  • 13.
    Nordqvist, Ulf
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Comparative Study of Protocol Processors2002In: Conference on Computer Science and Systems Engineering,2002, 2002, p. 107-Conference paper (Refereed)
  • 14.
    Nordqvist, Ulf
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Control path in a protocol processor2003In: Midwest symposium on circuits and systems MWCAS,2003, 2003Conference paper (Refereed)
  • 15.
    Nordqvist, Ulf
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Packet Classification and Termination in a Protocol Processor2003Conference paper (Other academic)
    Abstract [en]

    This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

  • 16.
    Nordqvist, Ulf
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Packet classification and termination in a protocol processor2003In: Network processor design - Issues and practices, vol 2 / [ed] Mark A. Franklin, Patrick Crowley , Haldun Hadimioglu, Peter Z. Onufryk, Elsevier , 2003, 1, p. 159-180Chapter in book (Other academic)
    Abstract [en]

    Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. ·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

  • 17.
    Nordqvist, Ulf
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Power optimized packet buffering in a protocol processor2003In: International conference on electronic circuits and systems, ICECS,2003, 2003Conference paper (Refereed)
1 - 17 of 17
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