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  • 1.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Equation-Based Vdd-Aware Model for Resistive Bridge Behavior2010Inngår i: IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010., 2010, s. 34-39Konferansepaper (Fagfellevurdert)
  • 2.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Vdd-Aware Bridge Defect Model2010Inngår i: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)., 2010Konferansepaper (Annet vitenskapelig)
  • 3.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Vdd-Aware Model for the Voltage on Bridged Nodes2010Inngår i: Workshop track of the IEEE European Test Symposium (ETS 2010), Prague, Czech Republic, May 24-28, 2010., 2010Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Resistive bridge defects have Vdd dependent behavior, a fact that is not yet considered in commercial DfT tools. So far, all Vdd-aware models have relied on computationally intensive SPICE simulation to calculate the voltage on the bridged nodes. The computation time limits the use of such models on large designs. Therefore, Vdd-aware models should employ a simplified set of equations that does not require computationally intensive simulation. The observation that enables such a set of simplified equations is that less variables need to be taken into account for modeling bridge behavior compared to SPICE simulations, which need to consider all available variables to model a wide set of circuits and behaviors. Previous approaches to define simplified equations to replace SPICE simulation for modeling resistive bridge behavior are either inaccurate for recent IC technologies or have not explicitly taken Vdd into account. Therefore, this paper proposes simplified equations to model the voltage on the bridged nodes in a computationally efficient manner. The approach is to find accurate equations for the drain-source currents of transistors that are involved in determining the bridge behavior. This paper describes an algorithm for applying the model by calculating the voltage on the bridged nodes given the drain-source currents of the involved transistors. The model is demonstrated by comparing the results from the proposed approach with simulation results for two gate libraries.

  • 4.
    Ingelsson, Urban
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Chang, Shih-Yen
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Utbildningsvetenskap.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Measurement Point Selection for In-Operation Wear-Out Monitoring2011Inngår i: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., IEEE , 2011, s. 381-386Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

  • 5.
    Larsson, Anders
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Chakrabarty, Krishnendu
    Duke University, USA.
    Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs2010Inngår i: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 6.
    Larsson, Erik
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Zadegan, Farrokh Ghani
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Test scheduling on IJTAG2010Inngår i: Nordic Test Forum (NTF 2010), Drammen, Norway., 2010Konferansepaper (Fagfellevurdert)
  • 7.
    Majeed, Mudassar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ahlström, Daniel
    Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Efficient Embedding of Deterministic Test Data2010Inngår i: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Konferansepaper (Annet vitenskapelig)
  • 8.
    Majeed, Mudassar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ahlström, Daniel
    Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson AB BU Networks, Stockholm, Sweden.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Efficient Embedding of Deterministic Test Data2010Inngår i: 19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010., 2010, s. 159-162Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor technologies require not only manufacturing test, but also in-field test. Preferably, the same test set is utilized both at manufacturing test and in-field test. While deterministic test patterns provide high fault coverage, storing complete test vectors leads to huge memory requirements and inflexibility in applying tests. In an IEEE 1149.1 (Boundary scan) environment, this paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account. Instead of storing complete test vectors, the approach stores only commands and component-specific test sets per each unique component. Given a command, test vectors are created by a test controller during test application. The approach is validated on hardware and experiments on ITC’02 benchmarks and industrial circuits show that the memory requirement for storing the test data for a system is highly related to the number of unique components.

  • 9.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing2010Inngår i: Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010, IEEE , 2010, s. 281-285Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The probability for errors to occur in electronic systems is not known in advance, but depends on many factors including influence from the environment where the system operates. In this paper, it is demonstrated that inaccurate estimates of the error probability lead to loss of performance in a well known fault tolerance technique, Roll-back Recovery with checkpointing (RRC). To regain the lost performance, a method for estimating the error probability along with an adjustment technique are proposed. Using a simulator tool that has been developed to enable experimentation, the proposed method is evaluated and the results show that the proposed method provides useful estimates of the error probability leading to near-optimal performance of the RRC fault-tolerant technique.

  • 10.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization2011Inngår i: 5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011, IEEE , 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability that deadlines are met. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. First, we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed. Second, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal completion time satisfies a given level of confidence requirement. Third, we use the proposed framework to evaluate probabilistic guarantees for RRC optimization in non-real-time systems.

  • 11.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    On-line Techniques to Adjust and Optimize Checkpointing Frequency2010Inngår i: IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, 2010, s. 29-33Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Due to increased susceptibility to soft errors in recent semiconductor technologies, techniques for detecting and recovering from errors are required. Roll-back Recovery with Checkpointing (RRC) is one well known technique that copes with soft errors by taking and storing checkpoints during execution of a job. Employing this technique, increases the average execution time (AET), i.e. the expected time for a job to complete, and thus impacts performance. To minimize the AET, the checkpointing frequency is to be optimized. However, it has been shown that optimal checkpointing frequency depends highly on error probability. Since error probability cannot be known in advance and can change during time, the optimal checkpointing frequency cannot be known at design time. In this paper we present techniques that are adjusting the checkpointing frequency on-line (during operation) with the goal to reduce the AET of a job. A set of experiments have been performed to demonstrate the benefits of the proposed techniques. The results have shown that these techniques adjust the checkpointing frequency so well that the resulting AET is close to the theoretical optimum.

  • 12.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Study on the Level of Confidence for Roll-back Recovery with Checkpointing2011Inngår i: 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability of meeting given deadlines. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. Therefore, in this paper we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed.

  • 13.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Karlsson, Erik
    Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC2010Inngår i: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Konferansepaper (Annet vitenskapelig)
  • 14.
    Nikolov, Dimitar
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Väyrynen, Mikael
    Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Singh, Virendra
    Indian Institute of Science, India.
    Optimizing Fault Tolerance for Multi-Processor System-on-Chip2010Inngår i: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010, s. 578-Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 15. Petersen, Kim
    et al.
    Nikolov, Dimitar
    Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson AB, Linköping, Sweden.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
    An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment2012Inngår i: IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012, 2012Konferansepaper (Fagfellevurdert)
    Abstract [en]

    As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on fault injection and fault handling. Our MPSoC demonstrator consists of (1) an MPSoC model with a set of components (devices) each equipped with fault detection features, so called instruments, (2) an Instrument Access Infrastructure (IAI) based on IEEE P1687 that connects the instruments, (3) a Fault Indication and Propagation Infrastructure (FIPI) that propagates fault indications to system-level, (4) a Resource Manager (RM) to schedule jobs based on fault statuses, (5) an Instrument Manager (IM) connecting the IAI and the RM, and (6) a Fault Injection Manager (FIM) that inserts faults. The main goal of the demonstrator is to enable experimentation on different fault handling solutions. The novelty in this particular demonstrator is that it uses the existing test features, i.e. IEEE P1687 infrastructure, to assist fault handling. The demonstrator is implemented and a case study is performed.

  • 16.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Power Constrained Test Scheduling for 3D Stacked Chips: (poster)2010Inngår i: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA., 2010Konferansepaper (Fagfellevurdert)
  • 17.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2011Inngår i: Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, Washington, DC, USA: IEEE Computer Society , 2011, s. 72-77Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.

  • 18.
    Sengupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2012Inngår i: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, nr 1, s. 121-135Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.

  • 19.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Scheduling Tests for Stacked 3D Chips under Power Constraints2010Inngår i: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Konferansepaper (Annet vitenskapelig)
  • 20.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Test Planning for 3D Stacked ICs with Through-Silicon Vias2011Inngår i: 3D-TEST, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs and 3D TSV-SICs with two chips in the stack. We have implemented our techniques and experiments show significant reduction of test cost.

  • 21.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Test Planning for Core-based 3D Stacked ICs under Power Constraints2012Inngår i: RASDAT 2012, 2012Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.

  • 22.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias2012Inngår i: VLSI 2012, IEEE , 2012Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

  • 23.
    SenGupta, Breeta
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Test Scheduling for 3D Stacked ICs under Power Constraints2011Inngår i: 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

  • 24.
    Wang, Q.
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Wallin, A.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Izosimov, Viacheslav
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Ingelsson, Urban
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
    Test tool qualification through fault injection2012Inngår i: Test Symposium (ETS 2012), IEEE , 2012Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to detect faults that can lead to violation of functional safety requirements. We present a semi-automatic qualification method involving a monitor and fault injection that reduce cost in the qualification process. We experiment on a verification tool implemented in LabVIEW.

  • 25.
    Zadegan, Farrokh Ghani
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Design Automation for IEEE P16872011Inngår i: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, s. 1-6Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

  • 26.
    Zadegan, Farrokh Ghani
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Lund University, Sweden.
    Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P16872012Inngår i: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 29, nr 2, s. 79-88Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.

  • 27.
    Zadegan, Farrokh Ghani
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Test Time Analysis for IEEE P16872010Inngår i: Proceedings of the Asian Test Symposium, 2010, s. 455-460Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

  • 28.
    Zadegan, Farrokh Ghani
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ingelsson, Urban
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Larsson, Erik
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    A Study of Instrument Reuse and Retargeting in P16872011Inngår i: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011., 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Modern chips may contain a large number of embedded test, debug, configuration, and monitoring features, called instruments. An instrument and its instrument data, instrument access procedures, may be pre-developed and reused and instruments may be accessed in different ways through the life-time of the chip, which requires retargeting. To address instruments reuse and retargeting, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.

1 - 28 of 28
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