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  • 101.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences2006In: Asia Pacific Conference on Circuits and Systems,2006, IEEE , 2006Conference paper (Refereed)
    Abstract [en]

    A formulation based on multirate theory is introduced for analog-to-digital converters using parallel sigma-delta modulators in conjunction with modulation sequences. It is shown how the formulation can be used to analyze a system's sensitivity to channel mismatch errors by means of circulant and pseudo-circulant matrices. It is demonstrated how the time-interleaved-modulated (TIM), Hadamard-modulated (HM) and frequency-band decomposition (FBD) converters can be viewed as special cases of this more general description, and it is shown why the TIM and HM ADCs are sensitive to channel mismatch errors, whereas the FBD ADCs are not.

  • 102.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multirate formulation for mismatch sensitivity analysis of analog-to-digital converters that utilize parallel S?-modulators2008In: Eurasip Journal on Advances in Signal Processing, ISSN 1687-6172, Vol. 2008Article in journal (Refereed)
    Abstract [en]

    A general formulation based on multirate filterbanktheory for analog-to-digital converters using parallel sigmadeltamodulators in conjunction with modulation sequences ispresented. The time-interleaved modulators (TIMs), Hadamard modulators(HMs), and frequency-band decomposition modulators(FBDMs) can be viewed as special cases of the proposeddescription. The usefulness of the formulation stems from itsability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. BothNyquist-rate and oversampled systems are considered, and it isshown how the matching requirements between channels canbe reduced for oversampled systems. The new formulation isuseful also for the derivation of new modulation schemes, andan example is given of how it can be used in this context.

  • 103.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Design Trade-Offs for Linear-Phase FIR Decimation Filters and SD-Modulat ors2006In: 14th European Signal Processing Conference,2006, Wien, Austria: EURASIP , 2006Conference paper (Refereed)
    Abstract [en]

    In this paper we examine the relation between signal-to-noise-ratio, oversampling ratio, transition bandwidth, and filter order for some commonly used sigma-delta-modulators and corresponding decimation filters. The decimation filters are equi-ripple finite impulse response filters and it is demonstrated that, for any given filter order, there exists an optimum choice of the stopband ripple and stopband edge which minimizes the signal-to-noise-ratio degradation.

  • 104.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An RF sampling radio frontend based on sigmadelta-conversion.2006In: 24th Norchip Conference,2006, IEEE , 2006, p. 133-136Conference paper (Refereed)
  • 105.
    Boopal, Padma Prasad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Reconfigurable FFT Architecture for Variable-Length and Multi-Streaming OFDM Standards2013In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE , 2013, p. 2066-2070Conference paper (Refereed)
    Abstract [en]

    This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption. The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.

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  • 106.
    Boström, Henrik
    Linköping University, Department of Electrical Engineering, Electronics System.
    An FPGA implementation of a digital FM modulator.2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The increase in speed and density of programmable logic devices such as Field Programmable Gate Arrays (FPGA) enables ever more complex designs to be constructed within a short time frame. The flexibility of a programmable device eases the integration of a design with a wide variety of components on a single chip. Since Frequency Modulation (FM) is an analog modulation scheme, performing it in the digital domain introduces new challenges. The details of these challenges and how to deal with them are also explained. This thesis presents the design of a digital stereo FM modulator including necessary signal processing, such as filtering, waveform generation, stereo multiplexing etc. The solution is comprised of code written in Very high speed integrated circuit Hardware Description Language (VHDL) and a selection of free Intellectual Property (IP)-blocks and is intended for implementation on a Xilinx FPGA. The focus of the thesis lies on area efficiency and a number of suggestions are given to maximize the number of channels that can be modulated using a single FPGA chip. An estimation of how many channels that can be modulated usingthe provided FPGA, Xilinx XC6SXL100T, is also presented.

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  • 107.
    Butt, Hadiyah
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Padala, Manjularani
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer.

    Most electronic circuits encounter the problem of the clock skew. The clock Skew for a synchronous circuit is defined as the difference in the time of arrival between two sequentially adjacent registers. The registers and the flip-flops do not receive the clock at the same time. The clock signal in a normal circuit is generated with an oscillator, oscillator produces error, due to which there is a distortion from the expected time interval. The PLLs are used to address the problem. A phase-locked loop works to ensure the time interval seen at the clocks of various registers and the flip-flops match the time intervals generated by the oscillator. PLLs are trivial and an essential part of the micro-processors. Traditional PLLs are designed to work as an analog building block, but it is difficult to integrate them on a digital chip. Analog PLLs are less affected by noise and process variations. Digital PLLs allow faster lock time and are used for clock generation in high performance microprocessors. A digital PLL has more advantages as compared to an analog PLL. Digital PLLs are more flexible in terms of calibration, programability, stability and they are more immune to noise. The cost of a digital PLL is less as compared to its analog counter part.

    Digital PLLs are analogous to the analog PLLs, but the components used for implementing a digital PLL are digital. A digitally controlled oscillator (DCO) is utilized instead of a voltage controlled oscillator. A time to digital converter(TDC) is used instead of the phase frequency detector. The analog filter is replaced with a digital low pass filter. Phase-locked loop is a very good research topic in electronics. It covers many topics in the electrical systems such as communication theory, control systems and noise characterization.

    This project work describes the design and simulation of miscellaneous blocks of an all-digital PLL for the 60 GHz band. The reference frequency is 54 MHz and the DCO output frequency is 2 GHz to 3 GHz in a state-of the-art 65 nm process, with 1 V supply voltage. An all-digital PLL is composed of digital components such as a low pass filter, a sigma delta modulator and a fractional N /N +1 divider for low voltage and high speed operation. The all-digital PLL is implemented in MATLAB and then the filter, a sigma delta modulator and a fractional N /N +1 divider are implemented in MATLAB and Verilog-A code. The sub blocks i.e full adder, D flip-flop, a digital to digital converter, a main counter, a prescalar and a swallow counter are implemented in the transistor level using CMOS 65nm technology and functionality of each block is verified.

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  • 108.
    Carlsson, Jonas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Contributions to Asynchronous Communication Ports for GALS Systems2006Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Digital systems commonly use a single global clock signal to synchronize the whole system. This is not always possible and it can be more advantageously to divide the system into separate clock domains, where each clock domain can operate with its own clock frequency. Communication between the different clock domains are not trivial and must be handled with care. Several schemes can be used depending on the relation between the clock frequencies of the communicating clock domains. This thesis focuses on the Globally Asynchronous Locally Synchronous (GALS) scheme, in which all communications between clock domains are handled using dedicated communication channels. These communication channels use asynchronous handshaking protocols to transfer information between clock domains. No global clock signal is used and the clock signal is instead local for each clock domain.

    An efficient design flow for GALS system has been developed, which allows a designer to implement GALS systems without prior knowledge of asynchronous circuits. The GALS design flow starts with a high-level model of the system behavior and ends with an implementation in an FPGA or an ASIC. The design flow can also increase the design efficiency for GALS system since the flow alleviates the design and placement of the asynchronous circuits for the designer. A tool that handles the asynchronous circuits in the design flow has been developed.

    Two types of communication ports have been developed to handle the communication between clock domains. Both of these ports can be used in systems with static schedule or dynamic schedule of transactions. One of the communication ports can easily be migrated to a new CMOS process, since it only uses standard-cells that care provided by most vendors of CMOS processes. A clock gating circuit has been developed to allow a clock domain to use an external stable clock signal to create an internal stoppable clock signal. A stoppable local clock is used to eliminate problems with metastability when transferring data between clock domains with arbitrary clock frequencies.

    In order to validate the design flow and proposed circuitry, has an integrated circuit for 2-dimensional Discrete Cosine Transform been implemented using the GALS scheme and one of the proposed communication ports. The circuit has been implemented using a standard-cell library in a 0.35 mm CMOS process. A few possible improvements to the implementation are also discussed in the thesis.

    The GALS design flow with the asynchronous wrapper generation tool has been used to implement the digital baseband processing in the physical layer of the IEEE 802.11a transmitter. The transmitter is built using multiple clock domains. The transmitter has been implemented and tested in a Stratix II FPGA.

  • 109.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems2006In: IEEE NORCHIP,2006, 2006Conference paper (Refereed)
  • 110.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An 8-by-8 Point 2D DCT Processor Based on the GALS Approach2003In: IEEE NorChip Conf.,2003, 2003Conference paper (Refereed)
  • 111.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools2006In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 953-960Article in journal (Other academic)
  • 112.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    GALS Implementation of a 2-D DCT Processor2004In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
  • 113.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    GALS port implementation in FPGA2005In: National Conf. Radio Science RVK,2005, 2005Conference paper (Refereed)
  • 114.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Port controller for GALS with first come first served function2004In: TENCON 2004,2004, 2004Conference paper (Other academic)
  • 115.
    Carlsson, Jonas
    et al.
    Linköping University, Department of Electrical Engineering.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Port controllers for a GALS Implementation of a 2-D DCT Processor2004In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004, 2004Conference paper (Other academic)
  • 116.
    Carlsson, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Palmkvist, Kent
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems2006In: WSEAS Int. Conf. Circuits,2006, 2006Conference paper (Refereed)
  • 117.
    Castro, J.
    et al.
    Centro Nacional de Microelectronica, Universidad de Sevilla.
    Acosta, A.J.
    Centro Nacional de Microelectronica, Universidad de Sevilla.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Geometry optimization in basic CMOS cells for improved power, leakage, and noise performances2008In: Proc. Int. Conf. Advances in Electronics and Micro-electronics, ENICS'08, IEEE , 2008, p. 48-53Conference paper (Refereed)
    Abstract [en]

    The rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells.

  • 118.
    Chhetri, Dhurv
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Manyam, Venkata Narasimha
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Continuous-Time ADC and DSP for Smart Dust2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication.

    This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals.

    A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz.

    The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clockless transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed.

    Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment.

    The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

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  • 119.
    Chizarie, Anders
    Linköping University, Department of Electrical Engineering, Electronics System.
    Driving Implantable Circuits Without Internal Batteries2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis investigates how implantable devices can operate without the use of internal batteries. The idea is to be able to drive a circuit inside human tissue to i.e. monitor blood flow in patients. Methods such as harvesting energy from the environment to power up the devices and wireless energy transferring such as electromagnetic induction have been investigated. Implantable devices as this communicates wirelessly, this means that data will be transferred through the air. Sending data streams through air have security vulnerabilities. These vulnerabilities can be prevented and have been discussed. Measurements of the electromagnetic induction have been made with tissue-like material, to see how tissue affects the received signal strength indication levels. Optimization have been made to make printed inductors as efficient as possible by looking at the parameters that have an impact on it. This to get the most out of the inductor, while still keeping it small when it comes implantable devices. Smaller size is better for implantable device.

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  • 120.
    Ciobanu, Alexandru
    et al.
    McGill University, Canada .
    Hemati, Saied
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gross, Warren J.
    McGill University, Canada .
    Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes2013In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 61, no 16, p. 4100-4113Article in journal (Refereed)
    Abstract [en]

    We propose a non-binary stochastic decoding algorithm for low-density parity-check (LDPC) codes over GF(q) with degree two variable nodes, called Adaptive Multiset Stochastic Algorithm (AMSA). The algorithm uses multisets, an extension of sets that allows multiple occurrences of an element, to represent probability mass functions that simplifies the structure of the variable nodes. The run-time complexity of one decoding cycle using AMSA is O(q) for conventional memory architectures, and O(1) if a custom memory architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two (192,96) (2,4)-regular codes over GF(64) and GF(256), both achieving a maximum clock frequency of 108 MHz. The GF(64) decoder has a coded throughput of 65 Mb/s at E-b/N-0 = 2.4 dB when using conventional memory, while a decoder using the custom memory version can achieve 698 Mb/s at the same E-b/N-0. At a frame error rate (FER) of 2 x 10(-6) the GF(64) version of the algorithm is only 0.04 dB away from the floating-point SPA performance, and for the GF(256) code the difference is 0.2 dB. To the best of our knowledge, this is the first fully parallel non-binary LDPC decoder over GF(256) reported in the literature.

  • 121.
    Classon, Viktor
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Power Design Using RNS2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity.

    The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter.

    By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.

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  • 122.
    Croner, Len
    Linköping University, Department of Electrical Engineering, Electronics System.
    Utvärdering av MK F1500 testutrustning2010Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    SAAB Support & Services, a service centre for air plane components, perform most of their measurements manually. These measurements can sometimes take up to four days to perform. In 2007 an automatic concept for testing from MK Test systems was purchased in order to enhance the accuracy and increase the efficiency.

    In our thesis we have initially examined the automatic concept for testing and then developed standards for how to calibrate this equipment, standards that meets SAAB:s requirements. Thereafter we have developed specifications and instructions on how to use the equipment. During our work we have gathered information for an evaluation of how fitting it is to use the F1500 for testing air plane components.

    The main outcome of our work consists of three manuals for three different areas; calibration, harness test and a standard test for example panels and controller units.

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    FULLTEXT01
  • 123.
    Cushon, Kevin
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hemati, Saied
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. University of Idaho, USA.
    Mannor, Shie
    Technion, Israel.
    Gross, Warren J.
    McGill University, Canada.
    Energy-Efficient Gear-Shift LDPC Decoders2014In: PROCEEDINGS OF THE 2014 IEEE 25TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2014), IEEE , 2014, p. 219-223Conference paper (Refereed)
    Abstract [en]

    In this paper, we present LDPC decoder designs based on gear-shift algorithms, which can use multiple decoding algorithms or update rules over the course of decoding a single frame. By first attempting to decode using low-complexity algorithms, followed by high-complexity algorithms, we increase energy efficiency without sacrificing error correction performance. We present the GSP and IGSP algorithms, and ASIC designs of these algorithms for the 10 Gbps Ethernet (2048,1723) LDPC code. In 65nm CMOS, our pipelined GSP decoder achieves a core area of 5.29mm(2), throughput of 88.1 Gbps, and energy efficiency of 39.3 pJ/bit, while our IGSP decoder achieves a core area of 6.00mm(2), throughput of 100.3 Gbps, and energy efficiency of 14.6 pJ/bit. Both algorithms achieve error correction performance equivalent to the offset min-sum algorithm. The throughput per unit area and energy efficiency of these decoders improve upon state-of-the-art decoders with comparable error correction performance.

  • 124. Dempster, Andrew
    et al.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Coleman, Jeffrey
    Towards an Algorithm for Matrix Multiplier Blocks2003In: European Conference on Circuit Theory and Design,2003, Kraków: European Circuit Society , 2003, p. 25-Conference paper (Refereed)
    Abstract [en]

    The basic elements of an algorithm for designing multiplier blocks for matrices are presented. The new algorithm often produces results superior to the best of the older algorithms applied only to columns.

  • 125.
    Dogan, Rabia
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    System Level Exploration of RRAM for SRAM Replacement2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors.

    This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement.

    Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency.

    By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems.

    In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.

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  • 126. Order onlineBuy this publication >>
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Contributions to Flexible Multirate Digital Signal Processing Structures2009Licentiate thesis, monograph (Other academic)
    Abstract [en]

    A current focus among communication engineers is to design flexible radio systems in order to handle services among different telecommunication standards. Efficient support of dynamic interactive communication systems requires flexible and cost-efficient radio systems. Thus, low-cost multimode terminals will be crucial building blocks for future generations of multimode communication systems. Here, different bandwidths, from different telecommunication standards, must be supported and, thus, there is a need for a system which can handle a number of different bandwidths. This can be done using multimode transmultiplexers (TMUXs) which make it possible for different users to share a common channel in a time-varying manner. These TMUXs allow bandwidth-on-demand so that the resulting communication system has a dynamic allocation of bandwidth to users. Each user occupies a specific portion of the channel where the location and width of this portion may vary with time.

    Another focus among communication engineers is to provide various wideband services accessible to everybody everywhere. Here, satellites with high-gain spot beam antennas, on-board signal processing, and switching will be a major complementary part of future digital communication systems. Satellites provide a global coverage and if a satellite is in orbit, customers only need to install a satellite terminal and subscribe to the service. Efficient utilization of the available limited frequency spectrum, by these satellites, calls for on-board signal processing to perform flexible frequency-band reallocation (FFBR).

    Considering these two focuses in one integrated system where the TMUXs operate on-ground and FFBR networks operate on-board, one can conclude that successful design of dynamic communication systems requires high levels of flexibility in digital signal processing structures. In other words, there is a need for flexible digital signal processing structures that can support different telecommunication scenarios and standards. This flexibility (or reconfigurability) must not impose restrictions on the hardware and, ideally, it must come at the expense of simple software modifications. In other words, the system is based on a hardware platform and its parameters can easily be modified without the need for hardware changes.

    This thesis aims to outline flexible TMUX and FFBR structures which can allow dynamic communication scenarios with simple software reconfigurations on the same hardware platform. In both structures, the system parameters are determined in advance. For these parameters, the required filter design problems are solved only once. Dynamic communications, with users having different time-varying bandwidths, are then supported by adjusting some multipliers of the proposed multimode TMUXs and a simple software programming in the channel switch of the FFBR network. These do not require any hardware changes and can be performed online. However, the filter design problem is solved only once and offline.

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    Contributions to Flexible Multirate Digital
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  • 127. Order onlineBuy this publication >>
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Contributions to Reconfigurable Filter Banks and Transmultiplexers2010Doctoral thesis, monograph (Other academic)
    Abstract [en]

    A current focus among communication engineers is to design flexible radio systems to handle services among different telecommunication standards. Thus, lowcost multimode terminals will be crucial building blocks for future generations of multimode communications. Here,  different bandwidths, from different telecommunication standards, must be supported. This can be done using multimode transmultiplexers (TMUXs) which allow different users to share a common channel in a time-varying manner. These TMUXs allow bandwidth-on-demand. Each user occupies a specific portion of the channel whose location and width may vary with time.

    Another focus among communication engineers is to provide various wideband services accessible to everybody everywhere. Here, satellites with high-gain spot beam antennas, on-board signal processing, and switching will be a major complementary part of future digital communication systems. Satellites provide a global coverage and customers only need to install a satellite terminal and subscribe to the service. Efficient utilization of the available limited frequency spectrum, calls for on-board signal processing to perform flexible frequency-band reallocation (FFBR).

    This thesis outlines the design and realization of reconfigurable TMUX and FFBR structures which allow dynamic communication scenarios with simple software reconfigurations. In both structures, the system parameters are determined in advance. For these parameters, the required filter design problems are solved only once. Dynamic communications, with users having different time-varying bandwidths, are then supported by adjusting some multipliers, commutators, or a channel switch. These adjustments do not require hardware changes and can be performed online. However, the filter design problem is solved offline. The thesis provides various illustrative examples and it also discusses possible applications of the proposed structures in the context of other communication scenarios, e.g., cognitive radios.

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    Contributions to Reconfigurable Filter Banksand Transmultiplexers
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  • 128.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A class of reconfigurable and low-complexity two-stage Nyquist filters2014In: Signal Processing, ISSN 0165-1684, E-ISSN 1872-7557, Vol. 96, p. 164-172Article in journal (Refereed)
    Abstract [en]

    This paper introduces a class of reconfigurable two-stage Nyquist filters where the Farrow structure realizes the polyphase components of linear-phase finite-length impulse response (FIR) filters. By adjusting the variable predetermined multipliers of the Farrow structure, various linear-phase FIR Nyquist filters and integer interpolation/decimation structures are obtained, online. However, the filter design problem is solved only once, offline. Design examples, based on the reweighted l(1)-norm minimization, illustrate the proposed method. Savings in the arithmetic complexity are obtained when compared to the reconfigurable single-stage structures.

  • 129.
    Eghbali, Amir
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Complexity reduction in low-delay Farrow-structure-based variable fractional delay FIR filters utilizing linear-phase subfilters2012Conference paper (Refereed)
    Abstract [en]

    This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in all branches of the Farrow structure. The second case uses linear-phase FIR filters in every second branch. These branches have milder restrictions on the approximation error. Therefore, even with a reduced order, for these linear-phase FIR filters, the approximation error is not affected. However, the arithmetic complexity, in terms of the number of distinct multiplications, is reduced by an average of 30%. Design examples illustrate the method.

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  • 130.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On Efficient Design of High-Order Filters With Applications to Filter Banks and Transmultiplexers With Large Number of Channels2014In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 62, no 5, p. 1198-1209Article in journal (Refereed)
    Abstract [en]

    This paper proposes a method for designing high-order linear-phase finite-length impulse response (FIR) filters which are required as, e.g., the prototype filters in filter banks (FBs) and transmultiplexers (TMUXs) with a large number of channels. The proposed method uses the Farrow structure to express the polyphase components of the desired filter. Thereby, the only unknown parameters, in the filter design, are the coefficients of the Farrow subfilters. The number of these unknown parameters is considerably smaller than that of the direct filter design methods. Besides these unknown parameters, the proposed method needs some predefined multipliers. Although the number of these multipliers is larger than the number of unknown parameters, they are known a priori. The proposed method is generally applicable to any linear-phase FIR filter irrespective of its order being high, low, even, or odd as well as the impulse response being symmetric or antisymmetric. However, it is more efficient for filters with high orders as the conventional design of such filters is more challenging. For example, to design a linear-phase FIR lowpass filter of order 131071 with a stopband attenuation of about 55 dB, which is used as the prototype filter of a cosine modulated filter bank (CMFB) with 8192 channels, our proposed method requires only 16 unknown parameters. The paper gives design examples for individual lowpass filters as well as the prototype filters for fixed and flexible modulated FBs.

  • 131.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reconfigurable two-stage Nyquist filters utilizing the Farrow structure2012Conference paper (Refereed)
    Abstract [en]

    This paper introduces reconfigurable two-stage finite-length impulse response (FIR) Nyquist filters. In both stages, the Farrow structure realizes reconfigurable lowpass linear-phase FIR Nyquist filters. By adjusting the variable multipliers of the Farrow structure, various FIR Nyquist filters and integer interpolation/decimation structures are obtained, online. However, the filter design problem is solved only once, offline. Design examples illustrate the method.

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  • 132.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Savory, Seb J.
    UCL, England .
    Optimal Least-Squares FIR Digital Filters for Compensation of Chromatic Dispersion in Digital Coherent Optical Receivers2014In: Journal of Lightwave Technology, ISSN 0733-8724, E-ISSN 1558-2213, Vol. 32, no 8, p. 1449-1456Article in journal (Refereed)
    Abstract [en]

    This paper proposes optimal finite-length impulse response (FIR) digital filters, in the least-squares (LS) sense, for compensation of chromatic dispersion (CD) in digital coherent optical receivers. The proposed filters are based on the convex minimization of the energy of the complex error between the frequency responses of the actual CD compensation filter and the ideal CD compensation filter. The paper utilizes the fact that pulse shaping filters limit the effective bandwidth of the signal. Then, the filter design for CD compensation needs to be performed over a smaller frequency range, as compared to the whole frequency band in the existing CD compensation methods. By means of design examples, we show that our proposed optimal LS FIR CD compensation filters outperform the existing filters in terms of performance, implementation complexity, and delay.

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  • 133.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Class of Multimode Transmultiplexers Based on the Farrow Structure2012In: Circuits, systems, and signal processing, ISSN 0278-081X, E-ISSN 1531-5878, Vol. 31, no 3, p. 961-985Article in journal (Refereed)
    Abstract [en]

    This paper introduces multimode transmultiplexers (TMUXs) in which the Farrow structure realizes the polyphase components of general lowpass interpolation/decimation filters. As various lowpass filters are obtained by one set of common Farrow subfilters, only one offline filter design enables us to cover different integer sampling rate conversion (SRC) ratios. A model of general rational SRC is also constructed where the same fixed subfilters perform rational SRC. These two SRC schemes are then used to construct multimode TMUXs. Efficient implementation structures are introduced and different filter design techniques such as minimax and least-squares (LS) are discussed. By means of simulation results, it is shown that the performance of the transmultiplexer (TMUX) depends on the ripples of the filters. With the error vector magnitude (EVM) as the performance metric, the LS method has a superiority over the minimax approach.

  • 134.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A farrow-structure-based multi-mode transmultiplexer2008In: Proceedings of IEEE International Symposium on Circuits and Systems: Seattle, Washington, USA, May. 18-21, 2008, IEEE , 2008, Vol. June, p. 3114-3117Conference paper (Refereed)
    Abstract [en]

    This paper introduces a multi-mode transmultiplexer (TMUX) consisting of Farrow-based variable integer sampling rate conversion (SRC) blocks. The polyphase components of general interpolation/ decimation filters are realized by the Farrow structure making it possible to achieve different linear-phase finite-length impulse response (FIR) lowpass filters at the cost of a fixed set of subfilters and adjustable fractional delay values. Simultaneous design of the subfilters, to achieve overall approximately Nyquist (Mth-band) filters, are treated in this paper. By means of an example, it is shown that the subfilters can be designed so that for any desired range of integer SRC ratios, the TMUX can approximate perfect recovery as close as desired.

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  • 135.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Multimode Transmultiplexer Structure2008In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 55, no 3, p. 279-283Article in journal (Refereed)
    Abstract [en]

    This paper introduces a multimode transmultiplexer (TMUX) structure capable of generating a large set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow-based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design beforehand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow-based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system.

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  • 136.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    An arbitrary bandwidth transmultiplexer and its application to flexible frequency-band reallocation networks2007In: Proc. European Conf. Circuit Theory Design, Seville, Spain, Aug. 26-30, 2007, IEEE , 2007, p. 248-251Conference paper (Refereed)
    Abstract [en]

    In this paper, we introduce a non-uniform transmultiplexer capable of generating arbitrary-bandwidth user signals. The transmultiplexer consists of linear-phase finite-length impulse response (FIR) filters and Farrow structures for arbitrary-rate interpolation/decimation. By applying the FIR rational sampling rate conversion (SRC) equivalent of the Farrow structure, we model the behavior of the multiplexer and derive the conditions under which the system can approximate perfect reconstruction. Futhermore, we illustrate the functionality of the proposed transmultiplexer and we analyze the performance and functionality of a flexible frequency-band reallocation (FFBR) network using this transmultiplexer.

  • 137.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Flexible Frequency-Band Reallocation: Complex Versus Real2009In: Circuits, systems, and signal processing, ISSN 0278-081X, E-ISSN 1531-5878, Vol. 28, no 3, p. 409-431Article in journal (Refereed)
    Abstract [en]

    This paper discusses a new approach for implementing flexible frequency-band reallocation (FFBR) networks for bentpipe satellite payloads which are based on variable oversampled complex-modulated filter banks (FBs). We consider two alternatives to process real signals using real input/output and complex input/output FFBR networks (or simply real and complex FFBR networks, respectively). It is shown that the real case has a lower overall number of processing units, i.e., adders and multipliers, compared to its complex counterpart. In addition, the real system eliminates the need for two Hilbert transformers, further reducing the arithmetic complexity. An analysis of the computational workload shows that the real case has a smaller rate of increase in the arithmetic complexity with respect to the prototype filter order and number of FB channels. This makes the real case suitable for systems with a large number of users. Furthermore, in the complex case, a high efficiency in FBR comes at the expense of high-order Hilbert transformers; thus, trade-offs are necessary. Finally, the performance of the two alternatives based on the error vector magnitude (EVM) for a 16-quadrature amplitude modulation (QAM) signal is presented.

  • 138.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Flexible frequency-band reallocation MIMO networks for real signals2007In: Proc. Int. Symp. Image, Signal Processing, Analysis, Istanbul, Turkey, Sept. 27-29, 2007, IEEE , 2007, p. 75-80Conference paper (Refereed)
    Abstract [en]

    In this paper, alow-complexity approach to implement a class of flexible frequency-band reallocation (FFBR) multi-input multi-output (MIMO) networks, which use variable oversampled complex-modulated filter banks, is introduced. Two alternatives in processing real signals using real input/output and complex input/output FFBR networks (or simply, real and complex FFBR networks, respectively) are considered. It is shown that to process each sample, the real case requires less number of real operations compared to its complex counterpart. Furthermore, the real case has a smaller growth rate in the number of real operations with respect to the prototype filter order. In addition, the real FFBR network eliminates the need for two Hilbert transformers whereas in the complex FFBR case, to achieve high efficiency in FBR, there is a need for high-order Hilbert transformers.

  • 139.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the complexity of multiplierless direct and polyphase FIR filter structures2007In: Proc. Int. Symp. Image, Signal Processing, Analysis, Istanbul, Turkey, Sept. 27-29, 2007, 2007, p. 200-205Conference paper (Refereed)
    Abstract [en]

    This paper discusses the complexity trend in different finite length impulse response (FIR) filter structures when using multiplierless (shift-and-add) realization. We derive the total number of adders required by the transposed direct form, polyphase, and reduced-complexity polyphase FIR filter structures. A comparison of the arithmetic complexities of these structures for different filter characteristics is performed. The simulation results show that considering both the high level structure and the algorithm used to realize the subfilters gives a more accurate measure of complexity comparison between different FIR filter structures.

  • 140.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the filter design for a class of multimode transmultiplexers2009In: Proceedings - IEEE International Symposium on Circuits and Systems, 2009, p. 89-92Conference paper (Refereed)
    Abstract [en]

    This paper discusses some issues related to the filter design in a class of multimode transmultiplexers (TMUXs). These TMUXs cover a large set of frequency division multiplexed (FDM) scenarios with simple reconfigurations. The reconfiguration is performed by changing the values of some multipliers. The paper outlines a direct filter design to decrease the level of inter-symbol and inter-carrier interference by the use of time-varying periodic filters. These time-varying periodic filters are derived from the known FDM scenarios and they are included as additional constraints in the filter design. Both minimax and constrained least-squares approaches are treated and it is shown that by including the additional constraints, the level of the TMUX noise can be reduced. This results in a better approximation of perfect reconstruction and makes the filter design direct.

  • 141.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reconfigurable nonuniform transmultiplexers based on uniform filter banks2010Conference paper (Refereed)
    Abstract [en]

    This paper introduces reconfigurable nonuniform transmultiplexers (TMUXs) based on uniform modulated filter banks (FBs). Polyphase components, of any user, are processed by a number of synthesis FB and analysis FB branches of a uniform TMUX. One branch, of the TMUX, represents one granularity band and any user occupies integer multiples of a granularity band. By adjusting the number of branches, assigned to each user, a nonuniform TMUX is obtained. This only requires adjustable commutators which add no extra arithmetic complexity. The application of both cosine modulated and modified discrete Fourier transform FBs are considered and the formulations related to the appropriate choice of parameters are outlined. Examples are provided for illustration.

  • 142.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reconfigurable Nonuniform Transmultiplexers Using Uniform Modulated Filter Banks2011In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN 1549-8328, Vol. 58, no 3, p. 539-547Article in journal (Refereed)
    Abstract [en]

    This paper introduces reconfigurable nonuniform transmultiplexers (TMUXs) based on fixed uniform modulated filter banks (FBs). The TMUXs use parallel processing where polyphase components, of any user, are processed by a number of synthesis FB and analysis FB branches. One branch represents one granularity band, and any user can occupy integer multiples of a granularity band. The proposed TMUX also requires adjustable commutators so that any user occupies any portion of the frequency spectrum. The location and width of this portion can be modified without additional arithmetic complexity or filter redesign. This paper considers both cosine modulated and modified discrete Fourier transform FBs. It discusses the filter design, TMUX realization, and the parameter selection. It is shown that one can indeed decrease the arithmetic complexity by proper choice of system parameters. For the critically sampled case and if the number of channels is higher than necessary, we can reduce the arithmetic complexity. In case of an oversampled system, the arithmetic complexity can be reduced by proper choice of the number of channels and the roll-off factor of the prototype filter. The proposed TMUX is compared to existing reconfigurable TMUXs, and examples are provided for illustration.

  • 143.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Göckler, Heinz G
    Ruhr-Universität Bochum, Germany.
    Dynamic Frequency-Band Reallocation and Allocation: from Satellite-Based Communication Systems to Cognitive Radios2011In: Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, ISSN 0922-5773, E-ISSN 1573-109X, Vol. 62, no 2, p. 187-203Article in journal (Refereed)
    Abstract [en]

    This paper discusses two approaches for the baseband processing part of cognitive radios. These approaches can be used depending on the availability of (i) a composite signal comprising several user signals or, (ii) the individual user signals. The aim is to introduce solutions which can support different bandwidths and center frequencies for a large set of users and at the cost of simple modifications on the same hardware platform. Such structures have previously been used for satellite-based communication systems and the paper aims to outline their possible applications in the context of cognitive radios. For this purpose, dynamic frequencyband allocation (DFBA) and reallocation (DFBR) structures based on multirate building blocks are introduced and their reconfigurability issues with respect to the required reconfigurability measures in cognitive radios are discussed.

  • 144.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Saramaki, Tapio
    Tampere University of Technology, Finland .
    A method for the design of Farrow-structure based variable fractional-delay FIR filters2013In: Signal Processing, ISSN 0165-1684, E-ISSN 1872-7557, Vol. 93, no 5, p. 1341-1348Article in journal (Refereed)
    Abstract [en]

    This paper proposes a method to design variable fractional-delay (FD) filters using the Farrow structure. In the transfer function of the Farrow structure, different subfilters are weighted by different powers of the FD value. As both the FD value and its powers are smaller than 0.5, our proposed method uses them as diminishing weighting functions. The approximation error, for each subfilter, is then increased in proportion to the power of the FD value. This gives a new distribution for the orders of the Farrow subfilters which has not been utilized before. This paper also includes these diminishing weighting functions in the filter design so as to obtain their optimal values, iteratively. We consider subfilters of both even and odd orders. Examples illustrate our proposed method and comparisons, to various earlier designs, show a reduction of the arithmetic complexity.

  • 145.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Saramäki, Tapio
    Tampere University of Technology, Finland.
    A new structure for reconfigurable two-stage Nyquist pulse shaping filters2011In: Circuits and Systems (MWSCAS), 2011, Piscataway, NJ, United States: IEEE , 2011, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper introduces a new structure for reconfigurable two-stage finite-length impulse response (FIR) Nyquist filters using the Farrow structure. The Nyquist filter is split into two equal and linear-phase FIR spectral factors. In the first stage, the Farrow structure realizes reconfigurable lowpass linear-phase FIR interpolation/decimation filters whereas the second stage is composed of a fixed lowpass linear-phase FIR filter. By adjusting the variable multipliers of the Farrow structure, the overall filter can be modified. Hence, various FIR Nyquist filters and integer interpolation/decimation structures are obtained. However, the filter design problem is solved only once and offline. Design examples illustrate the method.

  • 146.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Saramäki, Tapio
    Tampere University of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the design of adjustable fractional delay FIR filters using digital differentiators2010In: Proc. IEEE Int. Conf. Green Circuits Syst., IEEE , 2010, p. 289-292Conference paper (Refereed)
    Abstract [en]

    This paper proposes a systematic method to design adjustable fractional delay (FD) filters using the Farrow structure. The Farrow structure has even-order subfilters and the maximum magnitude approximation error determines the number of these subfilters. In the Farrow structure, different powers of the FD value are multiplied by the subfilters. As both the FD value and its powers are smaller than unity, they are considered as weighting functions. The approximation error for each subfilter can then increase in proportion to the power of the FD value. With the proposed design method, the first Farrow subfilter is a pure delay whereas the remaining subfilters are digital differentiators. Examples illustrate the proposed design method and comparison to some earlier designs shows an average reduction of 20% in arithmetic complexity.

  • 147.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Saramaki, T.
    Tampere University of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On two-stage Nyquist pulse shaping filters2012In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 60, no 1, p. 483-488Article in journal (Refereed)
    Abstract [en]

    This correspondence outlines a method for designing two-stage Nyquist filters. The Nyquist filter is split into two equal and linear-phase finite-length impulse response spectral factors. The per-time-unit multiplicative complexity, of the overall structure, is included as the objective function. Examples are then provided where Nyquist filters are designed so as to minimize the multiplicative complexity subject to the constraints on the overall Nyquist filter. In comparison to the single-stage case, the two-stage realization reduces the multiplicative complexity by an average of 48%. For two-stage sampling rate conversion (SRC), the correspondence shows that it is better to have a larger SRC ratio in the first stage. © 2006 IEEE.

  • 148.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Saramaki, Tapio
    Tampere University of Technology, Finland .
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Conditions for Lth-band filters of order 2N as cascades of identical linear-phase FIR spectral factors of order N2014In: Signal Processing, ISSN 0165-1684, E-ISSN 1872-7557, Vol. 97, no AprilArticle in journal (Refereed)
    Abstract [en]

    This paper presents formulas for the number of optimization parameters (degrees of freedom) when designing Type I linear-phase finite-length impulse response (FIR) Lth-band filters of order 2N as cascades of identical linear-phase FIR spectral factors of order N. We deal with two types of degrees of freedom referred to as (i) the total degrees of freedom D-T, and (ii) the remaining degrees of freedom D-R. Due to the symmetries or antisymmetries in the impulse responses of the spectral factors, D-T roughly equals N/2. Some of these parameters are specifically needed to meet the Lth-band conditions because, in an Lth-band filter, every Lth coefficient is zero and the center tap equals 1/L. The remaining D-R parameters can then be used to improve the stopband characteristics of the overall Lth-band filter. We derive general formulas for D-R with given pairs of L and N. It is shown that for a fixed L, the choices of N, in a close neighborhood, may even decrease D-R despite increasing the arithmetic complexity, order, and the delay.

  • 149.
    Eklund, Anders
    et al.
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Ohlsson, Henrik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Andersson, Mats
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Rydell, Joakim
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Ynnerman, Anders
    Linköping University, Department of Science and Technology, Media and Information Technology. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Knutsson, Hans
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization, CMIV. Linköping University, The Institute of Technology.
    Balancing an Inverted Pendulum by Thinking A Real-Time fMRI Approach2009Conference paper (Other academic)
    Abstract [en]

    We present a method for controlling a dynamical system using real-time fMRI. The objective for the subject in the MR scanner is to balance an inverse pendulum by activating the left or right hand or resting. The brain activity is classified each second by a neural network and the classification is sent to a pendulum simulator to change the force applied to the pendulum. The state of the inverse pendulum is shown to the subject in a pair of VR goggles. The subject was able to balance the inverse pendulum both with real activity and imagined activity. The developments here have a potential to aid people with communication disabilities e.g., locked in people. It might also be a tool for stroke patients to be ableto train the damaged brain area and get real-time feedback of when they do it right.

    Download full text (pdf)
    Balancing an Inverted Pendulum by Thinking A Real-Time fMRI Approach
  • 150.
    Elangovan, Vivek
    Linköping University, Department of Electrical Engineering, Electronics System.
    Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

    Download full text (pdf)
    fulltext
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