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  • 101.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmailzadeh Najari, Omid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

  • 102.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An RF sampling radio frontend based on sigmadelta-conversion.2006In: 24th Norchip Conference,2006, IEEE , 2006, p. 133-136Conference paper (Refereed)
  • 103. Bornefalk, H.
    et al.
    Xu, C.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Danielsson, M.
    Simulation study of an energy sensitive photon counting silicon strip detector for computed tomography: identifying strenghts and weaknesses and developing work-arounds2010Conference paper (Refereed)
  • 104.
    Bornefalk, Hans
    et al.
    AlbaNova University Centre, Sweden .
    Persson, Mats
    AlbaNova University Centre, Sweden .
    Xu, Cheng
    AlbaNova University Centre, Sweden .
    Karlsson, Staffan
    AlbaNova University Centre, Sweden .
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Danielsson, Mats
    AlbaNova University Centre, Sweden .
    Effect of Temperature Variation on the Energy Response of a Photon Counting Silicon CT Detector2013In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 60, no 2, p. 1442-1449Article in journal (Refereed)
    Abstract [en]

    The effect of temperature variation on pulse height determination accuracy is determined for a photon counting multibin silicon detector developed for spectral CT. Theoretical predictions of the temperature coefficient of the gain and offset are similar to values derived from synchrotron radiation measurements in a temperature controlled environment. By means of statistical modeling, we conclude that temperature changes affect all channels equally and with separate effects on gain and threshold offset. The combined effect of a 1 degrees C temperature increase is to decrease the detected energy by 0.1 keV for events depositing 30 keV. For the electronic noise, no statistically significant temperature effect was discernible in the data set, although theory predicts a weak dependence. The method is applicable to all x-ray detectors operating in pulse mode.

  • 105.
    Bornefalk, Hans
    et al.
    Royal Institute Technology.
    Xu, Cheng
    Royal Institute Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Danielsson, Mats
    Royal Institute Technology.
    Design considerations to overcome cross talk in a photon counting silicon strip detector for computed tomography2010In: NUCLEAR INSTRUMENTS and METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, ISSN 0168-9002, Vol. 621, no 1-3, p. 371-378Article in journal (Refereed)
    Abstract [en]

    This article presents a Monte Carlo simulation of the detector energy response in the presence of pileup in a segmented silicon microstrip detector designed for high flux spectral computed tomography with sub-millimeter pixel size. Currents induced on the collection electrode of a pixel segment are explicitly modeled and signals emanating from events in neighboring pixels are superimposed together with electronic noise before the entire pulse train is processed by a model of the readout electronics to obtain the detector energy response function. The article shows how the lower threshold and the time constant of the electronic filters need to be set in order to minimize the detrimental influence of cross talk from neighboring pixel segments, an issue that is aggravated by the sub-millimeter pixel size and the proposed segmented detector design.

  • 106.
    Caputa, Peter
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Efficient high-speed on-chip global interconnects2006Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.

    In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.

    To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.

    In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

    List of papers
    1. Low-Power, Low-Latency Global Interconnect
    Open this publication in new window or tab >>Low-Power, Low-Latency Global Interconnect
    2002 (English)In: Proceedings of the IEEE ASIC/SOC Conference, Rochester, USA, 2002, p. 394-398Conference paper, Published paper (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13906 (URN)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
    2. High Bandwidth, Low-Latency Global Interconnect
    Open this publication in new window or tab >>High Bandwidth, Low-Latency Global Interconnect
    2003 (English)In: VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May, 2003, p. 126-134Conference paper, Published paper (Other academic)
    Abstract [en]

    Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320µm wide bus with a capacity of 160Gb/s in a nearly standard 0.18µm process.

    Keywords
    interconnect, low latency, high bandwidth, global
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13907 (URN)10.1117/12.499957 (DOI)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-06-05
    3. A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
    Open this publication in new window or tab >>A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
    Show others...
    2004 (English)In: Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium, 2004, p. 475-477Conference paper, Published paper (Other academic)
    Keywords
    global interconnect, low-swing signalling
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13908 (URN)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
    4. An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
    Open this publication in new window or tab >>An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
    Show others...
    2004 (English)In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004, p. 849-858Conference paper, Published paper (Other academic)
    Keywords
    Transition energy cost model, power estimation, on-chip interconnect
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13909 (URN)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2019-09-05
    5. High-Speed On-Chip Interconnect Modeling for Circuit Simulation
    Open this publication in new window or tab >>High-Speed On-Chip Interconnect Modeling for Circuit Simulation
    2004 (English)In: Proceedings of the Norchip Conference, Oslo, Norway, November, 2004, p. 143-146Conference paper, Published paper (Other academic)
    Keywords
    on-chip interconnect modeling, global interconnect, lossy trnsmission lines, signal integrity
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13910 (URN)10.1109/NORCHP.2004.1423843 (DOI)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2019-09-05
    6. Well-Behaved Global On-Chip Interconnect
    Open this publication in new window or tab >>Well-Behaved Global On-Chip Interconnect
    2005 (English)In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1057-7122, Vol. 52, no 2, p. 318-323Article in journal (Refereed) Published
    Abstract [en]

    Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.

    Keywords
    interconnect, global interconnect, interconnect delay, on-chip bus, upper-level metal
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13911 (URN)10.1109/TCSI.2004.840483 (DOI)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2010-03-16
    7. A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
    Open this publication in new window or tab >>A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
    2006 (English)In: Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India, 2006, p. 117-122Conference paper, Published paper (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13912 (URN)
    Available from: 2006-07-18 Created: 2006-07-18
    8. Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
    Open this publication in new window or tab >>Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
    2005 (English)In: Proceedings of the 23rd Norchip Conference, Oulu, Finland, 2005, p. 281-284Conference paper, Published paper (Other academic)
    Abstract [en]

    We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18μm CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.

    Keywords
    CMOS integrated circuits, circuit simulation, crosstalk, integrated circuit interconnections, integrated circuit modelling, 0.18 micron, CMOS process, capacitive crosstalk effects, circuit simulations, data-rate, on-chip interconnect latencies, power dissipation, wave pipelining
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13913 (URN)10.1109/NORCHP.2005.1597044 (DOI)
    Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-25
    9. An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
    Open this publication in new window or tab >>An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
    2006 (English)In: International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006Conference paper, Published paper (Other academic)
    Abstract [en]

    A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.

    Keywords
    CMOS integrated circuits, delays, integrated circuit design, integrated circuit interconnections, synchronisation, 0.18 micron, 5.4 mm, CMOS process, data synchronization, data-clock skew, global clock skew, multicycle communication, on-chip global wire delays, synchronous latency-insensitive design
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-13914 (URN)10.1109/ISSCC.2006.1696233 (DOI)1-4244-0079-1 (ISBN)
    Available from: 2006-07-18 Created: 2006-07-18
  • 107.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Speed On-Chip Interconnect Modeling for Circuit Simulation2004In: Proceedings of the Norchip Conference, Oslo, Norway, November, 2004, p. 143-146Conference paper (Other academic)
  • 108.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering.
    Anders, Mark A.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, Ram K.
    Borkar, Shekhar
    A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies2004In: Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium, 2004, p. 475-477Conference paper (Other academic)
  • 109.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An extended transition energy cost model for buses in deep submicron technologies2004In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings / [ed] Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, p. 849-858Chapter in book (Refereed)
    Abstract [en]

    In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

  • 110.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies2004In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004, p. 849-858Conference paper (Other academic)
  • 111.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency2006In: Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India, 2006, p. 117-122Conference paper (Other academic)
  • 112.
    Caputa, Peter
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 3Gb/s/wire, 5mm Long, Low Latency, Global On-Chip Bus in 0.18µm CMOS.2005In: SSoCC 2005,2005, 2005Conference paper (Other academic)
  • 113.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme2006In: International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006Conference paper (Other academic)
    Abstract [en]

    A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.

  • 114.
    Caputa, Peter
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Low power, low latency global interconnect.2002In: Swedish System-on-Chip,2002, 2002Conference paper (Other academic)
  • 115.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power, Low-Latency Global Interconnect2002In: Proceedings of the IEEE ASIC/SOC Conference, Rochester, USA, 2002, p. 394-398Conference paper (Other academic)
  • 116.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Well-Behaved Global On-Chip Interconnect2005In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1057-7122, Vol. 52, no 2, p. 318-323Article in journal (Refereed)
    Abstract [en]

    Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.

  • 117.
    Carlsson, Ingvar
    et al.
    EK. ISY, LiU.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Natarajan, S
    MoSys.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A high density, low leakage, 5T SRAM for embedded caches2004In: ESSCIRC 2004,2004, Leuven: IEEE, Inc. , 2004, p. 215-Conference paper (Refereed)
  • 118.
    Carlsson, Mats
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Utilizing FPGAs for data acquisition at high data rates2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with RocketTMIO GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz.

  • 119.
    Chen, J.
    et al.
    Ericsson Research.
    Ze, H.
    Chalmers University of Technology.
    Bao, L.
    Ericsson Research.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Li, Y.
    Ericsson Research.
    Gunnarsson, S.
    SiversIMA AB.
    Stoij, C.
    SiversIMA AB.
    Zirath, H.
    Chalmers University of Technology.
    10 Gbps 16QAM Transmission over a 70/80 GHz (E-band) Radio Test-bed2012In: 2012 7th European Microwave Integrated Circuit Conference, IEEE , 2012, p. 556-559Conference paper (Refereed)
    Abstract [en]

    A millimeter-wave radio test-bed is implemented which demonstrates 16QAM transmission over 70/80 GHz band for data rate up to 10 Gbps. Performance of the 16QAM transmitter and receiver is evaluated in a loop-back lab set-up. With the proposed 10 Gbps on single carrier system architecture, it is possible to achieve 40 Gbps over a 5 GHz bandwidth when combined with polarization and spatial multiplexing.

  • 120.
    Chen, T.
    et al.
    Intel Corp., USA.
    Hazucha, P.
    Intel Corp., USA.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Karnik, T.
    Intel Corp., USA.
    Chen, C.
    Intel Corp., USA.
    Measuring power supply stability.2003Patent (Other (popular science, discussion, etc.))
  • 121.
    Cherukumudi, Dinesh
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ultra-Low Noise and Highly Linear Two-Stage Low Noise Amplifier (LNA)2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    An ultra-low noise two-stage LNA design for cellular basestations using CMOS is proposed in this thesis work.  This thesis is divided into three parts. First, a literature survey which intends to bring an idea on the types of LNAs available and their respective outcomes in performances, thereby analyze how each design provides different results and is used for different applications. In the second part, technology comparison for 0.12µm, 0.18µm, and 0.25µm technologies transistors using the IBM foundry PDKs are made to analyze which device has the best noise performance. Finally, in the third phase bipolar and CMOS-based two-stage LNAs are designed using IBM 0.12µm technology node, decided from the technology comparison. In this thesis a two-stage architecture is used to obtain low noise figure, high linearity, high gain, and stability for the LNA. For the bipolar design, noise figure of 0.6dB, OIP3 of 40.3dBm and gain of 26.8dB were obtained. For the CMOS design, noise figure of 0.25dB, OIP3 of 46dBm and gain of 26dB were obtained. Thus, the purpose of this thesis is to analyze the LNA circuit in terms of design, performance, application and various other parameters. Both designs were able to fulfill the design goals of noise figure < 1 dB, OIP3 > 40 dBm, and gain >18 dB.

  • 122.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A/D and D/A data conversion for wireless communications transceivers2011In: Digital Front-End in Wireless Communications and Broadcasting: circuits and signal processing / [ed] Fa-Long Luo, Cambridge University Press, 2011, p. 380-412Chapter in book (Other academic)
    Abstract [en]

    Covering everything from signal processing algorithms to integrated circuit design, this complete guide to digital front-end is invaluable for professional engineers and researchers in the fields of signal processing, wireless communication and circuit design. Showing how theory is translated into practical technology, it covers all the relevant standards and gives readers the ideal design methodology to manage a rapidly increasing range of applications. Step-by-step information for designing practical systems is provided, with a systematic presentation of theory, principles, algorithms, standards and implementation. Design trade-offs are also included, as are practical implementation examples from real-world systems. A broad range of topics is covered, including digital pre-distortion (DPD), digital up-conversion (DUC), digital down-conversion (DDC) and DC-offset calibration. Other important areas discussed are peak-to-average power ratio (PAPR) reduction, crest factor reduction (CFR), pulse-shaping, image rejection, digital mixing, delay/gain/imbalance compensation, error correction, noise-shaping, numerical controlled oscillator (NCO) and various diversity methods.

  • 123.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    BiST model for IC RF-transceiver front-end.2003In: IEEE Int. Symposium on Defect and Fault Tolerance in VLSI systems.,2003, Piscataway: IEEE Computer Society , 2003, p. 295-Conference paper (Refereed)
  • 124.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    DfT and BiST Techniques for RF Integrated Circuits.2007Other (Other (popular science, discussion, etc.))
  • 125.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Efficient post-layout timing verification via RLC trees and explicit PWL timing integration.2002In: ICECS 2002,2002, 2002, p. 689-Conference paper (Refereed)
  • 126.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fast BER Test for Digital RF Transceivers2009In: 14th IEEE European Test Symposium, Sevilla, Spain, May 25-29, 2009Conference paper (Refereed)
    Abstract [en]

    The paper presents a fast bit-error-rate (BER) test suitable for digital receivers or transceivers. The test technique makes use of an elevated BER which can be achieved by geometrical translation of the signal constellation points on the IQ plane. As the elevated BER requires much less bits (or symbols) to be measured, significant savings in the test time can be anticipated. Also a maximum sensitivity to impairments in the noise factor is obtained in this way. To develop an effective elevated-BER test for a device in mass production a careful characterization procedure must be carried out, followed by a fine tuning procedure aimed at improving the test resolution and thereby the test coverage. The technique is supported by a simple statistical model and illustrated by a simulation example of a 4QAM receiver.

  • 127.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Fault Modeling of RF blocks based on noise analysis.2004In: 2004 IEEE ISCAS,2004, Piscataway: IEEE Corp. , 2004, p. 513-Conference paper (Refereed)
  • 128.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Loopback BiST for RF front-ends in digital transceivers.2003In: International Symposium on System-on-Chip,2003, Piscataway: Institute of Electrical and Electronic Engineers , 2003, p. 143-Conference paper (Refereed)
  • 129.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    On-chip test for RF IC transceivers2010In: European Microwave Week Workshop, 2010, p. 16-30Conference paper (Refereed)
    Abstract [en]

    Over the years, production test of digital ICs has reached a significant degree of maturity. This progress has been enabled by several techniques, such as fault simulation, test-pattern generation and the built-in-self-test (BiST). Unlike this, much less success has been achieved in the analog/RF and mixed-signal ICs domain, where functional testing has been widely used and the major advances have been in the capabilities of expensive automatic test equipment (ATE). At present, the advancing complexity and performance of mixed-signal and RF ICs are pushing functional test methods and the ATE to the edge of their limits. In this context, alternative approaches based on analog fault modeling, design for testability (DfT), and BiST, so far not appreciated by industry, can largely alleviate the problem and cut the test costs.In this tutorial the essentials of the on-chip test for IC RF transceivers will be presented. The available on chip baseband DSP can serve as a tester while the RF front-end is reconfigured for test. The basic test setup is a loopback, enabled by a test attenuator and in some cases by an offset mixer, too. Different variants of this setup adopt the bypassing technique to boost testability. Also the observability blocks (RF detectors) can be incorporated. The existing limitations and tradeoffs in terms of test feasibility, controllability and observability versus the chip performance will be discussed. The fault-oriented approach and the sensitization techniques will be emphasized. Implementation examples in CMOS technology will be included as well.

  • 130.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    RF on-chip test by reconfiguration technique.2006In: WSEAS International Conference.,2006, 2006Conference paper (Refereed)
    Abstract [en]

      

  • 131.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Konopacki, J.
    Silesian University of Technology, Gliwice, Poland.
    SC Filter Design for RF Applications2006In: Mixed design of integrated circuits and systems MIXDES 2006,2006, Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz, Poland , 2006, p. 341-Conference paper (Refereed)
  • 132.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Gonzales, Javier
    EK, ISY, LiU.
    Mixed loopback BiST for RF digital transceivers.2004In: DFT ´04,2004, Piscataway: IEEE, Corp. , 2004, p. 220-Conference paper (Refereed)
  • 133.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Gonzalez Bayon, Javier
    Techniques for Sensitizing RF Path under SER Test.2005In: ISCAS,2005, Galena, Il, USA: Gerard Enteprises, LLC , 2005, p. 4843-Conference paper (Refereed)
  • 134.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Li, Lin
    EK, ISY, LiU.
    Signal path sensitization for built-in-self-test in integrated RF transceivers.2004In: DDECS,2004, Bratislava: Institute of Informatics, SAS , 2004, p. 59-Conference paper (Refereed)
  • 135.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Boosting SER Test for RF Transceivers by Simple DSP Technique2007In: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007., IEEE , 2007, p. 1-6Conference paper (Refereed)
    Abstract [en]

    The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.

  • 136.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Built-in Loopback Test for IC RF Transceivers2010In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 6, p. 933-946Article in journal (Refereed)
    Abstract [en]

    The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

  • 137.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Rashad, Ramzan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Offset Loopback Test For IC RF Transceivers2006In: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2006, p. 583-586Conference paper (Refereed)
    Abstract [en]

    In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade

  • 138.
    Danielsson, M.
    et al.
    Royal Institute of Technology, AlbaNova University Center.
    Bornefalk, H.
    Royal Institute of Technology, AlbaNova University Center.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Improving image quality in photon counting-mode detector systems2012Patent (Other (popular science, discussion, etc.))
  • 139.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of Low Noise  Transconductance Amplifier for Current-Mode Wideband RF Frontend2011In: Swedish System-on-Chip Conference (SSOCC), Varberg, Sweden: IEEE Solid-State Circuits Society, 2011Conference paper (Other academic)
  • 140.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 825-828Conference paper (Refereed)
    Abstract [en]

    A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 - 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 <; -14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

  • 141.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design and Analysis of High Speed Capacitive Pipeline DACs2014In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed)
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

  • 142.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Highly linear open-loop output driver design for high speed capacitive DACs2013In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

  • 143.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Dabrowski, Jerzy J.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Focused Calibration for Advanced RF Test with Embedded RF Detectors2013In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

  • 144.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy J.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    On-chip IP3 IP2 RF Advanced Test and Calibration Technique with Embedded RF Detectors2013Conference paper (Other academic)
  • 145.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wideband RF Detector Design for High Performance On-Chip Test2012In: NORCHIP 2012, IEEE , 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

  • 146.
    Duppils, Mattias
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Challenges in analog VLSI.2001In: Conference on Computer Science and Systems Engineering.,2001, 2001, p. 249-252Conference paper (Other academic)
  • 147.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    MERC (Microelectronics Research Center), Ericsson Components, Kista, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications1999In: Proceedings of ICECS '99. The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, 1999, p. 1197-1200Conference paper (Refereed)
    Abstract [en]

    A mixed analog/digital (MAD) multiply-accumulate (MAC) unit, implemented with switched-capacitor (SC) technique is presented. The MAC unit consist of a programmable capacitor array (PCA) for coefficient representation, and an integrator for accumulation. A coefficient compensation technique to neutralize the non-ideal MAC properties due to finite opamp gain is introduced. The MAD-MAC unit is a new concept for effective mapping of signal processing tasks on SC technique; in particular high-order fully programmable narrow-band FIR filter applications. The utilization of the MAD-MAC unit concept is shown with a simulation of a decimated 400-tap narrow-band FIR filter

  • 148.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    Ericsson Components AB, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A study of the non-ideal properties of sample-and-hold circuits with respect to the analog bandwidth1999In: Proc. of 3rd IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, 1999, p. 119-121Conference paper (Refereed)
    Abstract [en]

    The fast evolving communication market demands decreased fabrication cost, which will be met by highly integrated circuit solutions. In the near future, we will see system-on-a-chip solutions in CMOS technology, where transceivers will be integrated on a single chip preferably, also with digital circuitry. Receiver topologies with A/D conversion at higher frequencies are interesting from an integration point of view. Therefore, a deeper understanding of the A/D converter limitations to cope with high-frequency signals is needed. This paper will highlight the track-and-hold circuit linearity, which is a frequency dependent fundamental limit on the A/D conversion accuracy

  • 149.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Analog MAC unit with digital coefficients suitable for IF filtering and demodulationManuscript (preprint) (Other academic)
    Abstract [en]

    A digitally programmable analog interface for communication applications is presented. The interface consists of a sampler, an analog multiplier, and an analog accumulator; where the analog multiplier features signed 8-bit coefficient resolution. The interface is implemented with switched-capacitor technique and is demonstrated with a test chip, fabricated using a low-cost 0.6)μm CMOS process.The interface is shown to be able to combine a programmable band-pass filter of FIR type with a demodulator for quadrature modulation. The bandwidth and center frequency of this filter is programmable with a fixed clock frequency, which is a useful property in multi-standard receivers. As a demonstration, the interface is controlled, in real-time by digital control stimuli, to act as sampler and combined 27th-order FIR filter and demodulator at three different frequencies; 1.43MHz, 2.50MHz, and 3.57MHz. The test chip clock frequency is fixed to 10MHz. The test chip hence samples, filters, and demodulates a 357kSymbol/s QPSK modulated waveform with carrier frequency 1.43MHz, 2.50MHz, or 3.57MHz, and with power -61dBm. The measured ultimate rejection of the 27th-order FIR filter is measured to 25dB, and the noise figure is measured to 29dB.

  • 150.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low power mixed analog-digital signal processing2000In: ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design, New York, USA: Association for Computing Machinery (ACM), 2000, p. 61-66Conference paper (Refereed)
    Abstract [en]

    The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumulaðtions, is analyzed. An implementation is proposed, composed of switched-capacitor mixed analog/digital multiply accumulate units in the analog front-end, followed by an A/D converter. This impleðmentation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed A/D converter in the front-end, to execute signal processing tasks that include decimation. The power savings are only due to relaxed requirement on A/D conversion rate, as a direct consequence of the decimation. In a case study of a narrowband FIR filter, realized with four multiply accumulate units, and with a decimation factor of 100; power saving is 54 times. Implementation details are given, the power consumption, and the thermal noise are analyzed.

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