An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.
Canonic signed-digit code representation of multiplier coefficients is often used in digital filters to reduce the required amount of hardware resources. Another approach taken in this paper is to use canonic signed-digit coded coefficients to increase the throughput of the multiplier. We show how the suggested approach applies to serial/parallel multipliers with fixed coefficients. A max¬imally fast implementation of a digital filter is further used as an example to demonstrate the use of the multi¬pliers in recursive digital filters. The resulting bit-serial filters yield a throughput comparable to bit-parallel implemen¬tations, while using only a fractional amount of hardware resources. The filters can be used directly in high-speed applications or in low-power applications after supply voltage scaling.
In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier.
Algorithms for full-precision computation of squares and products are derived. The algorithms yield minimum bit-serial latency. We present logic realizations for the algorithms based on shift accumulators. The realizations have been partitioned into regular bit-slices suitable for hardware implementation.
A method for handling overflow and quantization in recursive digital filters is described. The method merges the sign-extension required for a serial/parallel multiplier with the required truncation in the bit-serial loops. The method works with maximally fast implementations, i.e., implementations for which the minimum sample period is used as sample period. The method is first described using a first-order recursive filter, and then applied to a third-order bireciprocal lattice wave digital filter.
Inaccurate matching of the analog sources in a D/A converter causes a signal-dependent error in the output. This distortion can be transformed into noise by assigning the digital control to the analog sources randomly, which is a technique referred to as dynamic element matching. In this paper, we present a dynamic element matching technique where the scrambling is restricted such that the glitches in the converter are minimized. By this, both the distortion due to glitches is reduced, and the signal-dependent error due to matching is suppressed. A hardware structure is proposed that implements the approach, and the operation of the hardware is described. Simulation results indicate that the method has a potential of yielding as good reduction of glitches as the optimal thermometer-coded converter and a signal-dependent error level that is almost as low as achieved with prior dynamic element matching techniques.
We evaluate the performance of flash D/A converters designed with a new approach based on linear coding of the weights. The evaluation is performed by estimating the relative performance of the new, linear-coded converter compared with thermometer coded, binary-scaled, and segmented converters. As a measure of performance we use glitch noise, which is of importance in high-speed D/A converter operation. We also consider linearity measures such as the differential and integral nonlinearities to illustrate the typical impact of matching errors in the different converter types. A bound is given on the converter size at which the glitch performance becomes better for the linear-coded than for the segmented D/A converter
A linear increase of the source weights in a flash D/A converter has earlier been suggested to reduce the level of glitches associated with the code transitions. However, a limitation with this approach was that a straightforward conversion from an offset-binary number to a linear-coded number required a large amount of hardware. In this work, we present a new method that yields a more hardware efficient encoder. We also compare the proposed encoder with other encoders in terms of design complexity and glitch performance.
To design a high-speed flash D/A converter with high resolution we need to keep the glitch noise within acceptable levels. The current practice is to use a segmented converter structure where we can trade off hardware complexity and glitch performance by selecting a proper number of most significant bits to be thermometer coded. For the remaining least significant bits (LSB) binary-scale are used. A recently proposed alternative to this method is to design a converter with linearly increasing weights, i.e., 1 LSB, 2 LSB, 3 LSB,... . In this paper, we propose two new converter structures that both have a dual linear-coded source matrix operating in parallel with the original linear-coded source matrix. Simulations show that we can expect up to 30% better glitch performance for one of the proposed structures, assuming signals with moderate transitions. However, for signals with large transitions there is no significant improvement.
We evaluate the performance of flash D/A converters designed with a new approach based on linear coding of the weights. The evaluation is performed by estimating the relative performance of the new, linear-coded converter compared with thermometer coded, binary-scaled, and segmented converters. As a measure of performance we use glitch noise, which is of importance in high-speed D/A converter operation. We also consider linearity measures such as the differential and integral nonlinearities to illustrate the typical impact of matching errors in the different converter types. A bound is given on the converter size at which the glitch performance becomes better for the linear-coded than for the segmented D/A converter.
An object of the present invention is to provide a D/A conversion method and a D/A converter that reduce glitching noise and yet are less complex than the prior art.
In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion based on linear coding of the weights (1, 2, 3,…). The new method improves the glitch performance and reduces the hardware complexity for high resolution converters. An algorithm for converting the digital binary-coded input word into a digital word controlling the linear weights is given. In an example, the linear-coded weights are applied to a current-steering D/A converter. We discuss properties such as layout properties, device matching, and mixed-signal issues.
We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.