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  • 101.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    On Lifting-Based Fixed-Point Complex Multiplications and Rotations2017Inngår i: Proceedings 24th IEEE Symposium on Computer Arithmetic 24–26 July 2017 London, United Kingdom / [ed] Neil Burgess, Javier Bruguera and Florent de Dinechin, Institute of Electrical and Electronics Engineers (IEEE), 2017, s. 43-49Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Lifting-based complex multiplications and rotations are integer invertible, i.e., an integer input value is mapped to the same integer output value when rotating forward and backward. This is an important aspect for lossless transform-based source coding, but since the structure only require three real-valued multiplications and three real-valued additions it is also a potentially attractive way to perform complex multiplications when the coefficient has unity magnitude. In this work, we consider two aspects of these structures. First, we show that both the magnitude and angular error is dependent on the angle of input value and derive both exact and approximated expressions for these. Second, we discuss how to design such structures without the typical separation into three subsequent matrix multiplications. It is shown that the proposed design method allows many more values which are integer invertible, but can not be separated into three subsequent matrix multiplications with fixed-point values. The results show good correspondence between the error approximations and the actual error as well as a significantly increased design space.

  • 102.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Bertilsson, Erik
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Klasson, Johannes
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Ingemarsson, Carl
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Approximate Neumann Series or Exact Matrix Inversion for Massive MIMO? (Invited Paper)2017Inngår i: Proceedings 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), London, UK, 24-26 July 2017 / [ed] Neil Burgess, Javier Bruguera, and Florent de Dinechin, Institute of Electrical and Electronics Engineers (IEEE), 2017, s. 62-63Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Approximate matrix inversion based on Neumann series has seen a recent increased interest motivated by massive MIMO systems. There, the matrices are in many cases diagonally dominant, and, hence, a reasonable approximation can be obtained within a few iterations of a Neumann series. In this work, we clarify that the complexity of exact methods are about the same as when three terms are used for the Neumann series, so in this case, the complexity is not lower as often claimed. The second common argument for Neumann series approximation, higher parallelism, is indeed correct. However, in most current practical use cases, such a high degree of parallelism is not required to obtain a low latency realization. Hence, we conclude that a careful evaluation, based on accuracy and latency requirements must be performed and that exact matrix inversion is in fact viable in many more cases than the current literature claims.

  • 103.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Low-complexity general FIR filters based on Winograd's inner product algorithm2013Konferansepaper (Annet vitenskapelig)
  • 104.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Johansson, Håkan
    Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem. Linköpings universitet, Tekniska högskolan.
    Decimation Filters for High-Speed Delta-Sigma Modulators With Passband Constraints: General Versus CIC-Based FIR Filters2015Inngår i: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE conference proceedings, 2015, s. 2205-2208Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For high-speed delta-sigma modulators the decimation filters are typically polyphase FIR filters as the recursive CIC filters can not be implemented because of the iteration period bound. In addition, the high clock frequency and short input word length make multiple constant multiplication techniques less beneficial. Instead a realistic complexity measure in this setting is the number of non-zero digits of the FIR filter tap coefficients. As there is limited control of the passband approximation error for CIC-based filters these must in most cases be compensated to meet a passband specification. In this work we investigate the complexity of decimation filters meeting CIC-like stopband behavior, but with a well defined passband approximation error. It is found that the general approach can in many cases produce filters with much smaller passband approximation error at a similar complexity.

  • 105.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. ISY .
    Johansson, Håkan
    Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem. Linköpings universitet, Tekniska högskolan. ISY .
    Wanhammar, Lars
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    MILP design of frequency-response masking FIR filters with few SPT terms2004Inngår i: First International Symposium on Control, Communications and Signal Processing, 2004, Tunisia: IEEE , 2004, s. 405-408Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this work we formulate a mixed integer linear programming (MILP) problem that minimizes the number of signed-power-of- two (SPT) terms given a filter specification for linear-phase frequency-response masking (FRM) filters. The proposed method designs the filters in two steps. The model filter and the masking filters are designed separately, but subject to each other. Hence, it is not guaranteed that the global minimum is obtained. However, each solution is optimal given the other filter(s), and iteration may improve the overall solution. The filter design problems are formulated using normalized peak ripple magnitude (NPRM), which for FRM filters introduces some implications, which is also discussed in this work.

  • 106.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Ohlsson, Henrik
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wanhammar, Lars
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Improved multiple constant multiplication using minimum spanning trees2004Inngår i: Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004,  Volume 1 / [ed] Michael B. Matthews, IEEE , 2004, s. 63-66Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Recently, a novel technique for the multiple constant multiplication (MCM) problem using minimum spanning trees (MSTs) has been proposed. The approach works by finding simple differences between the coefficients to realize and then applying the same method to the differences (which is an MCM problem as well). Each iteration is divided into two steps. First, finding a minimum spanning tree in the graph describing the differences between the coefficients. Second, as each edge in the graph may correspond to more than one difference, one difference is selected for each edge in the MST. Generally, both these stages have multiple solutions. The aim of this work is to more closely study how the MST and the differences should be selected to give better total results. It is also discussed how the two stages in each iteration may be joined into one problem.

  • 107.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wanhammar, Lars
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Arithmetic2013Inngår i: Handbook of signal processing systems / [ed] Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, New York: Springer, 2013, s. 593-637Kapittel i bok, del av antologi (Fagfellevurdert)
  • 108.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Wanhammar, Lars
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Basic Arithmetic Circuits2017Inngår i: Arithmetic Circuits for DSP Applications / [ed] Pramod Kumar Meher, Thanos Stouraitis, John Wiley & Sons, 2017, s. 1-32Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    General‐purpose DSP processors, application‐specific processors, and algorithm‐specific processors are used to implement different types of DSP systems or subsystems. They are typically used in applications involving complex and irregular algorithms while application‐specific processors provide lower unit cost and higher performance for a specific application, particularly when the volume of production is high. Most DSP applications use fractional arithmetic instead of integer arithmetic. Multimedia and communication applications involve real‐time audio and video/image processing which very often require sum‐of‐products (SOP) computation. The need of computing non‐linear functions arises in many different applications. The straightforward method of approximating an elementary function is to just store the values in a look‐up table typically leads to large tables, even though the resulting area from standard cell synthesis grows slower than the number of memory bits. It is of interest to find ways to approximate elementary functions using a trade‐off between arithmetic operations and look‐up tables.

  • 109.
    Gustafsson, Viktor
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Waller, Calle
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Usage of Bluetooth Low Energy for Weather Measurements2018Independent thesis Basic level (university diploma), 10,5 poäng / 16 hpOppgave
    Abstract [en]

    For every year the importance of lowering energy consumptionof our devices gets more important. Wireless devicesget smaller which leads to the fact that they need smallerbatteries than earlier versions. At the same time the customersstill have high requirements on the battery time. So what followsis that new technologies are needed to meet the customerrequirements by lowering the energy consumption for the devicesto maintain the same battery time as earlier.Today it is very common that these wireless devices makesuse of the wireless Bluetooth protocol in order to communicatewith other devices, for example with a mobile application.Bluetooth is in many cases more energy consuming thannecessary. In this report the wireless Bluetooth Low Energyprotocol will be tested and evaluated to see if the energy consumptionof a battery driven ground station for weather measurementscan be reduced.

  • 110.
    Gustavsson, Mikael
    et al.
    SP Devices AB.
    Ul Amin, Farooq
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Bjorklid, Anders
    SP Devices AB.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Xu, Cheng
    Royal Institute of Technology.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography2012Inngår i: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 59, nr 1, s. 30-39Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    We describe a high-rate energy-resolving photon-counting ASIC aimed for spectral computed tomography. The chip has 160 channels and 8 energy bins per channel. It demonstrates a noise level of ENC= electrons at 5 pF input load at a power consumption of andlt;5mW/channel. Maximum count rate is 17 Mcps at a peak time of 40 ns, made possible through a new filter reset scheme, and maximum read-out frame rate is 37 kframe/s.

  • 111.
    Han, Dapeng
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    FPGA Implementation of an AC3 Decoder2017Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The aim of this thesis is to explore the possibility of integrating an AC3 audio de- coding module into the company’s current product. Due to limited left resources on the FPGA chip in the company’s current product, the focus of this thesis is to be resource efficient. In this thesis, a system for AC3 audio decoding is designed and implemented. In order to use less logic on FPGA, PicoBlaze soft processor is used to control the whole processing flow. The system is designed and synthe- sized for a Spartan-6 FPGA which can be easily ported to the company’s current platform. 

  • 112.
    Haque, Muhammad Fahim Ul
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Pulse-Width Modulated RF Transmitters2017Doktoravhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    The market for wireless portable devices has grown signicantly over the recent years.Wireless devices with ever-increased functionality require high rate data transmissionand reduced costs. High data rate is achieved through communication standards such asLTE and WLAN, which generate signals with high peak-to-average-power ratio (PAPR),hence requiring a power amplier (PA) that can handle a large dynamic range signal. Tokeep the costs low, modern CMOS processes allow the integration of the digital, analogand radio functions on to a single chip. However, the design of PAs with large dynamicrange and high eciency is challenging due to the low voltage headroom.

    To prolong the battery life, the PAs have to be power-ecient as they consume a sizablepercentage of the total power. For LTE and WLAN, traditional transmitters operatethe PA at back-o power, below their peak efficiency, whereas pulse-width modulation(PWM) transmitters use the PA at their peak power, resulting in a higher efficiency.PWM transmitters can use both linear and SMPAs where the latter are more power efficient and easy to implement in nanometer CMOS. The PWM transmitters have a higher efficiency but suffer from image and aliasing distortion, resulting in a lower dynamic range,amplitude and phase resolution.

    This thesis studies several new transmitter architectures to improve the dynamicrange, amplitude and phase resolution of PWM transmitters with relaxed filtering requirements.The architectures are suited for fully integrated CMOS solutions, in particular forportable applications.

    The first transmitter (MAF-PWMT) eliminates aliasing and image distortions whileallowing the use of SMPAs by combining RF-PWM and band-limited PWM. The transmittercan be implemented using all-digital techniques and exhibits an improved linearity and spectral performance. The approach is validated using a Class-D PA based transmitter where an improvement of 10.2 dB in the dynamic range compared to a PWM transmitter for a 1.4 MHz of LTE signal is achieved.

    The second transmitter (AC-PWMT) compensates for aliasing distortion by combining PWM and outphasing. It can be used with switch-mode PAs (SMPAs) or linear PAs at peak power. The proposed transmitter shows better linearity, improved spectral performanceand increased dynamic range as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. The idea is validated using push-pull PAs and the proposed transmitter shows an improvement of 9 dB in the dynamic rangeas compared to a PWM transmitter using digital pulse-width modulation for a 1.4 MHzLTE signal.

    The third transmitter (MD-PWMT) is an all-digital implementation of the second transmitter. The PWM is implemented using a Field Programmable Gate Array(FPGA) core, and outphasing is implemented as pulse-position modulation using FPGA transceivers, which drive two class-D PAs. The digital implementation offers the exibility to adapt the transmitter for multi-standard and multi-band signals. From the measurement results, an improvement of 5 dB in the dynamic range is observed as compared to an all-digital PWM transmitter for a 1.4 MHz LTE signal.

    The fourth transmitter (EP-PWMT) improves the phase linearity of an all-digital PWM transmitter using PWM and asymmetric outphasing. The transmitter uses PWM to encode the amplitude, and outphasing for enhanced phase control thus doubling the phase resolution. The measurement setup uses Class-D PAs to amplify a 1.4 MHz LTEup-link signal. An improvement of 2.8 dB in the adjacent channel leakage ratio is observed whereas the EVM is reduced by 3.3 % as compared to an all-digital PWM transmitter.

    The fifth transmitter (CRF-ML-PWMT) combines multilevel and RF-PWM, whereas the sixth transmitter (CRF-MP-PMWT) combines multiphase PWM and RF-PWM. Both transmitters have smaller chip area as compared to the conventional multiphase and multilevel PWM transmitters, as a combiner is not required. The proposed transmitters also show better dynamic range and improved amplitude resolution as compared to conventional RF-PWM transmitters.

    The solutions presented in this thesis aims to enhance the performance and simplify the digital implementation of PWM-based RF transmitters.

    Delarbeid
    1. Combined RF and Multilevel PWM Switch Mode Power Amplifier
    Åpne denne publikasjonen i ny fane eller vindu >>Combined RF and Multilevel PWM Switch Mode Power Amplifier
    2013 (engelsk)Inngår i: Norchip Conference, IEEE , 2013, s. 1-4Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    This paper presents a novel power amplifier (PA) architecture based on the combination of radio frequency pulse width modulation (RFPWM) and multilevel PWM. The architecture provides better dynamic range at high carrier frequency compared to RFPWM. The benefits of this architecture over multilevel PWM are that it only requires a single PA and no combiner. The average efficiency for an 802.11g baseband signal is better than multilevel PWM. Our results also shows that the proposed technique exhibit a constant dynamic range at carrier frequency of 3, 4 and 5 GHz, in contrast to RFPWM which shows a decrease in dynamic range for increase in carrier frequency.

    sted, utgiver, år, opplag, sider
    IEEE, 2013
    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-102929 (URN)10.1109/NORCHIP.2013.6702010 (DOI)978-1-4799-1647-4 (ISBN)
    Konferanse
    NORCHIP 2013; NOV 11-12, 2013, Vilnius, Lithuania
    Tilgjengelig fra: 2014-01-08 Laget: 2014-01-08 Sist oppdatert: 2019-01-04
    2. Combined RF and Multiphase PWM Transmitter
    Åpne denne publikasjonen i ny fane eller vindu >>Combined RF and Multiphase PWM Transmitter
    2015 (engelsk)Inngår i: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, s. 264-267Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

    sted, utgiver, år, opplag, sider
    IEEE, 2015
    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-122703 (URN)10.1109/ECCTD.2015.7299999 (DOI)000380498200001 ()978-1-4799-9877-7 (ISBN)
    Konferanse
    2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, August 24-26, 2015
    Tilgjengelig fra: 2015-11-16 Laget: 2015-11-16 Sist oppdatert: 2017-01-18bibliografisk kontrollert
  • 113.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Combined RF and Multilevel PWM Switch Mode Power Amplifier2013Inngår i: Norchip Conference, IEEE , 2013, s. 1-4Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a novel power amplifier (PA) architecture based on the combination of radio frequency pulse width modulation (RFPWM) and multilevel PWM. The architecture provides better dynamic range at high carrier frequency compared to RFPWM. The benefits of this architecture over multilevel PWM are that it only requires a single PA and no combiner. The average efficiency for an 802.11g baseband signal is better than multilevel PWM. Our results also shows that the proposed technique exhibit a constant dynamic range at carrier frequency of 3, 4 and 5 GHz, in contrast to RFPWM which shows a decrease in dynamic range for increase in carrier frequency.

  • 114.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Combined RF and Multiphase PWM Transmitter2015Inngår i: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, s. 264-267Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

  • 115.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Combined RF and Multiphase PWM Transmitter2015Konferansepaper (Annet vitenskapelig)
  • 116.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Modified Band-limited Pulse-Width Modulated Polar Transmitter2015Konferansepaper (Annet vitenskapelig)
  • 117.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Modified Multilevel PWM Switch Mode Power Amplifier2014Konferansepaper (Annet vitenskapelig)
  • 118.
    Haque, Muhammad Fahim Ul
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Pasha, Muhammad Touqir
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Aliasing-Compensated Polar PWM Transmitter2017Inngår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 64, nr 8, s. 912-916Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

  • 119.
    Hedin, Adam
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Konstruktion av styrelektronik till testfixtur2015Independent thesis Basic level (degree of Bachelor), 10 poäng / 15 hpOppgave
    Abstract [en]

    The focus of this thesis is primarily in electronic construction and describes the design process for a microcontroller circuit board from concept development to prototyping. The client develops test fixtures for automated testing of products within the electronics industry and needs a new controller circuit for the test fixtures that can handle controls and basic testing. An investigation into the needs of such a system is conducted and a prototype printed circuit board assembly is manufactured.

    The prototype is developed with focus on protection against electrostatic discharges and overvoltage. Among the functions that are included are voltage measurements, communication interfaces and control of input and output currents. Firmware for the prototype is developed and configured to communicate with a PC through USB interface for control and collecting of measurements.

  • 120.
    Hedin, Alexander
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Testing and evaluation of the integratability of the Senior processor2011Independent thesis Advanced level (professional degree), 20 poäng / 30 hpOppgave
    Abstract [en]

    The first version of the Senior processor was created as part of a thesis projectin 2007. This processor was completed and used for educational purposes atLinköpings University. In 2008 several parts of the processor were optimized andthe processor expanded with additional functionality as part of another thesisproject. In 2009 an EU funded project called MULTI-BASE started, in which theComputer Division at the Department of Electrical Engineering participated in.For their part of the MULTI-BASE project, the Senior processor was selected tobe used. After continuous revision and development, this processor was sent formanufacturing.

    The assignment of this thesis project was to test and verify the different func-tions implemted in the Senior processor. To do this a PCB was developed fortesting the Senior processor together with a Virtex-4 FPGA. Extensive testingwas done on the most important functions of the Senior processor. These testsshowed that the manufactured Senior processor works as designed and that it alonecan perform larger calculations and use external hardware accelerators with thehelp of its various interfaces.

  • 121.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Hardware Architecture for Protocol Processing2001Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.

    There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.

    I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.

    Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.

    Delarbeid
    1. Configurable Port Processor Increases Flexibility in the Protocol Processing Area
    Åpne denne publikasjonen i ny fane eller vindu >>Configurable Port Processor Increases Flexibility in the Protocol Processing Area
    2000 (engelsk)Inngår i: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, s. 275-Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

    (...)

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100437 (URN)
    Konferanse
    COOLChips III An International Symposium on Low-Power and High-Speed Chips. Kikai-Shinko-Kaikan, Tokyo, Japan. April 24-25. 2000
    Tilgjengelig fra: 2013-11-07 Laget: 2013-11-07 Sist oppdatert: 2013-11-07
    2. Specification of a configurable general-purpose protocol processor
    Åpne denne publikasjonen i ny fane eller vindu >>Specification of a configurable general-purpose protocol processor
    2000 (engelsk)Inngår i: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, s. 284-289Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100439 (URN)
    Konferanse
    Second International Symposium on Communication Systems, Networks and Digital Signal Processing. Bournemouth, UK. July 19-20. 2000
    Tilgjengelig fra: 2013-11-07 Laget: 2013-11-07 Sist oppdatert: 2013-11-07
    3. VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
    Åpne denne publikasjonen i ny fane eller vindu >>VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
    Vise andre…
    2001 (engelsk)Inngår i: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, s. 1215-1218Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33606 (URN)10.1109/ICECS.2001.957433 (DOI)19640 (Lokal ID)19640 (Arkivnummer)19640 (OAI)
    Konferanse
    The 8th IEEE Internationa Conference on Electronics, Circuits and Systems, Malta, September 2-5, 2001
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-07
    4. Specification of a configurable general-purpose protocol processor
    Åpne denne publikasjonen i ny fane eller vindu >>Specification of a configurable general-purpose protocol processor
    2002 (engelsk)Inngår i: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, nr 3, s. 198-202Artikkel i tidsskrift (Fagfellevurdert) Published
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33567 (URN)10.1049/ip-cds:20020443 (DOI)19599 (Lokal ID)19599 (Arkivnummer)19599 (OAI)
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2017-12-13
  • 122.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    In-Line CRC Calculation and Scheduling for 10 Gigabit Ethernet Transmission2002Inngår i: Swedish System-on-Chip Conference,2002, 2002Konferansepaper (Annet vitenskapelig)
  • 123.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Eriksson, Henrik
    Computer Engineering Chalmers tekniska högskola.
    Larsson-Edefors, Per
    Computer Engineering Chalmers tekniska högskola.
    Full Custom vs. Standard Cell Based Design - an Adder Comparison2002Inngår i: Swedish System-on-Chip Conference,2002, 2002Konferansepaper (Annet vitenskapelig)
  • 124.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Eriksson, Henrik
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Larsson-Edefors, Per
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    VLSI Implementation of CRC-32 for 10 Gigabit Ethernet2001Inngår i: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, s. 1215-1218Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

  • 125.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implementation of Fast CRC Calculation2003Inngår i: Asia South Pacific Design Automation Conference,2003, 2003, s. 563-Konferansepaper (Fagfellevurdert)
  • 126.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Novel ASIP and Processor Architecture for Packet Decoding2002Inngår i: Workshop of Application Specific Processors Digest,2002, 2002, s. 25-Konferansepaper (Fagfellevurdert)
  • 127.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Configurable Port Processor Increases Flexibility in the Protocol Processing Area2000Inngår i: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, s. 275-Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

    (...)

  • 128.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nordqvist, Ulf
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Embedded Protocol Processor for Fast and Efficient Packet Reception2002Inngår i: International Conference on Computer Design,2002, 2002, s. 414-Konferansepaper (Fagfellevurdert)
  • 129.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Specification of a configurable general-purpose protocol processor2000Inngår i: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, s. 284-289Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

  • 130.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Specification of a configurable general-purpose protocol processor2002Inngår i: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, nr 3, s. 198-202Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

  • 131.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Persson, Niclas
    Linköpings universitet, Institutionen för systemteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    VLSI Implementation of Internet Checksum Calculation for 10 gigabit Ethernet2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 114-Konferansepaper (Fagfellevurdert)
  • 132.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Pettersson, Magnus
    Gustafsson, Fredrik
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska högskolan.
    An Investigation of the Longitudinal Dynamics of a Car, especially Air Drag and Rolling Resistance1993Rapport (Annet vitenskapelig)
  • 133.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Verbauwhede, Ingrid
    EE Dept UCLA.
    Fast IP address lookup engine for SoC integration2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 200-Konferansepaper (Fagfellevurdert)
  • 134.
    Henriksson, Tomas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    VLSI implementation of a switch for on-chip networks2003Inngår i: Int workshop on Design and diagnostics of electronic circuits and systems DDECS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 135.
    Hjelmberg, Eric
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Rowell, Henrik
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Persondetektering i inomhusmiljö med enkla sensorer2015Independent thesis Basic level (university diploma), 20 poäng / 30 hpOppgave
    Abstract [sv]

    Denna rapport syftar till att beskriva arbetet kring att kunna detektera närvaro i ett rum medhjälp av så enkla sensorer som möjligt, kopplade till en Arduino. Samtidigt som detta skerså används också systemet till att med samma sensorer visa klimatet i rummet. Läsaren fåren inblick i problematiken med att detektera människor samt inom funktionen av de valdasensorerna. Utöver detta studeras energiförbrukningen i systemet. Rapportenmynnar ut i enslutsats där en procentuell chans för närvaro presenteras via en internetuppkoppling medhjälp av en omfattande testning av sensorernas beteende.

  • 136.
    Huang, Yulin
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    VLSI Implementation of Key Components in A Mobile Broadband Receiver2009Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.

  • 137.
    Hussain, Sajid
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Verification and FPGA implementation of a floating point SIMD processor for MIMO processing2010Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The rapidly increasing capabilities of digital electronics have increased the demand of Software Defined Radio (SDR), which were not possible in the special purpose hardware. These enhanced capabilities come at the cost of time due to complex operations involved in multi-antenna wireless communications, one of those operations is complex matrix inversion.

    This thesis presents the verification and FPGA implementation of a SIMD processor, which was developed at Computer Engineering division of Linköping university, Sweden. This SIMD processor was designed specifically for performing complex matrix inversion in an efficient way, but it can also be reused for other operations. The processor is fully verified using all the possible combinations of instructions.

    An optimized firmware for this processor is implemented for efficiently inverting 4×4 matrices. Due to large number of subtractions involved in direct analytical approach, it losses stability for 4×4 matrices. Instead of this, a blockwise subdivision is used, in which 4×4 matrix is subdivided into four 2×2 matrices. Based on these 2×2 matrices, the inverse of 4×4 matrix is computed using the direct analytical approach and some other computations.

    Finally, the SIMD processor is integrated with Senior processor (a controlprocessor) and synthesized on Xilinx, Virtex-4 FPGA. After this, the performance of the proposed architecture is evaluated. A firmware is implemented for the Senior which uploads and downloads data/program into the SIMD unit using both I/O and DMA.

  • 138.
    Hägglund, Erik
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design of a DVB-T Receiver: For SFN on a DSP-Processor2012Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The goal of this thesis was to implement a DVB-T receiver on Coresonic’s DSP-processor and attempt to evaluate how to design a receiver that is robust against very strong echoes with a long delay. Long delayed echoes is very common in Single Frequency Networks (SFN) which is why focus was put on finding algorithms that work well in SFN.The thesis involved analyzing different algorithms involved in making a DVB-T receiver where the focus was to find a good channel estimation algorithm. The thesis also included programming the DSP-processor and making some smaller modifications to their hardware solution to integrate their error correction hardware. After finding relevant articles with promising algorithms a small transmitter, channel and receiver was modeled in Matlab in order to try the different algorithms. After testing the different algorithms some of the simpler ones were first implemented to quickly get a working receiver. The implementation was however time consuming and all of the most appropriate algorithms to better avert the effects of long and strong echoes where not implemented. This means some algorithms where only analyzed and discussed.The receiver performance is tested and simulated in Coresonic’s DSP simulator. The receiver does not fully meet the requirements set by NorDig when it comes to handling long delay spread echoes with a magnitude of 0db when tested in the DSP processor simulator. The receiver is however able to handle the Ricean channel at a SNR of 19 Db and Rayleigh channel at an SNR of 24 Db.This report is the result of the final thesis of a Master of Science in Computer Engineering at Linköpings Tekniska Högskola. The thesis was performed at Coresonic AB in Mjärdevi Linköping.

  • 139.
    Hällman, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Institutionen för datavetenskap.
    DC Charging of Heavy Commercial Plug-in Hybrid Electric Vehicles2015Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    A solution to reduce exhaust emissions from heavy commercial vehicles are to haul the vehicles completely or partially electric. This means that the vehicle must contain a significant electric energy source. The large capacity of the energy source causes the vehicle to either sacrifice a large part of its up time to charge the source or apply a higher charge power at the cost of power losses and lifetime of the energy source. This thesis contains a pre-study of high-power DC-charge of hybrid batteries from existing infrastructure suited to electric hybrid cars. Following parts are included in the thesis: modeling of a battery pack and a DC-DC converter, formulation of a MPC controller for the battery pack, analysis of charging strategies and battery restrictions through simulations. The thesis results shows that a longer charging time increases the energy efficiency and reduces the degradation in the battery. It also shows that a charging strategy similar to constant-current-constant-voltage charging should be used for a full charge of an empty battery.

  • 140.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Hardware Architecture for Positive Definite Matrix Inversion Based on LDL Decomposition and Back-Substitution2016Inngår i: 2016 50TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, IEEE COMPUTER SOC , 2016, s. 859-863Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we propose an efficient hardware architecture for computation of matrix inversion of positive definite matrices. The algorithm chosen is LDL decomposition followed directly by equation system solving using back substitution. The architecture combines a high throughput with an efficient utilization of its hardware units. We also report FPGA implementation results that show that the architecture is well tailored for implementation in real-time applications.

  • 141.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    On fixed-point implementation of symmetric matrix inversion2015Inngår i: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ, USA: IEEE , 2015, s. 440-443Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.

  • 142.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    On fixed-point implementation of symmetric matrix inversion2015Inngår i: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ, USA: IEEE , 2015, s. 1-4Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.

  • 143.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture2018Inngår i: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 90, nr 11, s. 1583-1592Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, a fast Fourier transform (FFT) hardware architecture optimized for field-programmable gate-arrays (FPGAs) is proposed. We refer to this as the single-stream FPGA-optimized feedforward (SFF) architecture. By using a stage that trades adders for shift registers as compared with the single-path delay feedback (SDF) architecture the efficient implementation of short shift registers in Xilinx FPGAs can be exploited. Moreover, this stage can be combined with ordinary or optimized SDF stages such that adders are only traded for shift registers when beneficial. The resulting structures are well-suited for FPGA implementation, especially when efficient implementation of short shift registers is available. This holds for at least contemporary Xilinx FPGAs. The results show that the proposed architectures improve on the current state of the art.

  • 144.
    Ingemarsson, Carl
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Källström, Petter
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Qureshi, Fahad
    Not Found:Linkoping Univ, Dept Elect Engn, SE-58183 Linkoping, Sweden; Tampere University of Technology, Finland.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Efficient FPGA Mapping of Pipeline SDF FFT Cores2017Inngår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 25, nr 9, s. 2486-2497Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

  • 145.
    Isaksson, Johan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL2017Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    High Level Synthesis (HLS) is a new method for developing applications for use on FPGAs. Instead of the classic approach using a Hardware Descriptive Language (HDL), a high level programming language can be used. HLS has many perks, including high level debugging and simulation of the system being developed. This shortens the development time which in turn lowers the development cost. In this thesis an evaluation is made regarding the feasibility of using SDAccel as the HLS tool in the OpenCL environment. Two image processing algorithms are implemented using OpenCL C and then synthesized to run on a Kintex Ultrascale FPGA. The implementation focuses both on low latency and throughput as the target environment is a video distribution network used in vehicles. The network provides the driver with video feeds from cameras mounted on the vehicle. Finally the test result of the algorithm runs are presented, displaying how well the HLS tool has preformed in terms of system performance and FPGA resource utilization.

  • 146.
    Isberg Martinsson, Linus
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Modulariserbar operatörspanel baserad på ett CAN-buss gränssnitt2015Independent thesis Basic level (degree of Bachelor), 10,5 poäng / 16 hpOppgave
    Abstract [sv]

    För att styra utrustningen i olika fordon inom industrin används olika typer av strömbrytare som sitter monterade på en operatörspanel. Från dessa går det ofta individuella signalkablar fram till enheterna som ska styras. Ett alternativ för att att slippa den störa mängden kablar detta kan leda till är att istället koppla strömbrytarna till en mikrokontroller, denna vidarebefodrar sedan signalerna via en CAN-buss till en ECU som styr alla enheter från en central position i fordonet.

    Under detta examensarbete, som har utförts hos Syncore Technologies AB, har därför en operatörspanelsplattform, både hård- och mjukvara, utvecklats för att uppnå en minimal NRE-kostnad för varje ny kundkonfiguration som inkluderar olika bestyckningar av strömbrytare samt beteenden för dessa.

  • 147.
    Jakobsson, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska fakulteten. Atlas Copco Rock Drills AB, Örebro, Sweden.
    Frisk, Erik
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska fakulteten.
    Pettersson, Robert
    Atlas Copco Rock Drills AB, Örebro, Sweden.
    Krysander, Mattias
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Data driven modeling and estimation of accumulated damage in mining vehicles using on-board sensors2017Inngår i: PHM 2017. Proceedings of the Annual Conference of the Prognostics and Health Management Society 2017, St. Petersburg, Florida, USA, October 2–5, 2017 / [ed] Anibal Bregon and Matthew J. Daigle, phmSociety , 2017, s. 98-107Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The life and condition of a MT65 mine truck frame is to a large extent related to how the machine is used. Damage from different stress cycles in the frame are accumulated over time, and measurements throughout the life of the machine are needed to monitor the condition. This results in high demands on the durability of sensors used. To make a monitoring system cheap and robust enough for a mining application, a small number of robust sensors are preferred rather than a multitude of local sensors such as strain gauges. The main question to be answered is whether a low number of robust on-board sensors can give the required information to recreate stress signals at various locations of the frame. Also the choice of sensors among many different locations and kinds are considered. A final question is whether the data could also be used to estimate road condition. By using accelerometer, gyroscope and strain gauge data from field tests of an Atlas Copco MT65 mine truck, coherence and Lasso-regression were evaluated as means to select which signals to use. ARX-models for stress estimation were created using the same data. By simulating stress signals using the models, rain flow counting and damage accumulation calculations were performed. The results showed that a low number of on-board sensors like accelerometers and gyroscopes could give enough information to recreate some of the stress signals measured. Together with a linear model, the estimated stress was accurate enough to evaluate the accumulated fatigue damage in a mining truck. The accumulated damage was also used to estimate the condition of the road on which the truck was traveling. To make a useful road monitoring system some more work is required, in particular regarding how vehicle speed influences damage accumulation.

  • 148.
    Jang, Jeong Keun
    et al.
    Dongbu Hitek, South Korea.
    Kim, Ho Keun
    Ajou University, South Korea.
    Sunwoo, Myung Hoon
    Ajou University, South Korea.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Area-efficient scheduling scheme based FFT processor for various OFDM systems2018Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    This paper presents an area-efficient fast Fouriertransform (FFT) processor for orthogonal frequency-division multiplexing systems based on multi-path delay commutator architecture. This paper proposes a data scheduling scheme to reduce the number of complex constant multipliers. The proposed mixed-radix multi-path delay commutator FFT processor can support 128-, 256-, and 512-point FFT sizes. The proposed processor was synthesized using the Samsung 65-nm CMOS standard cell library. The proposed processor with eight parallel data paths can achieve a high throughput rate of up to 2.64 GSample/s at 330 MHz.

  • 149.
    Jang, Jeong Keun
    et al.
    Dongbu Hitek, South Korea.
    Kim, Ho Keun
    Ajou Univ, South Korea.
    Sunwoo, Myung Hoon
    Ajou Univ, South Korea.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Area-Efficient Scheduling Scheme Based FFT Processor for Various OFDM Systems2018Inngår i: 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), IEEE , 2018, s. 338-341Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents an area-efficient fast Fourier transform (FFT) processor for orthogonal frequency-division multiplexing systems based on multi-path delay commutator architecture. This paper proposes a data scheduling scheme to reduce the number of complex constant multipliers. The proposed mixed-radix multi-path delay commutator FFT processor can support 128-, 256-, and 512-point FFT sizes. The proposed processor was synthesized using the Samsung 65-nm CMOS standard cell library. The proposed processor with eight parallel data paths can achieve a high throughput rate of up to 2.64 GSample/s at 330 MHz.

  • 150.
    Jian, Wang
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Yan, Xie
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Behavior Modeling of a Digital Video Broadcasting System and the Evaluation of its Equalization Methods2010Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    In this thesis, a single carrier ATSC DTV baseband transmitter, part of the receiver(including channel estimator and channel equalizer), were modeled. Since multi-pathinduced ISI (inter symbol interference) is the most significant impact on theperformance of single carrier DTV reception, modeling and implementation of singlecarrier channel estimator and channel equalizer have been the focus of the thesis. Westarted with the investigation of channel estimation methods. Afterwards, severalchannel estimators and equalizers were modeled and the performance of each channelequalization methods in different scenarios was evaluated. Our results show that thefrequency domain equalizer can achieve low computing cost and handle long delaypaths. Another important issue to be considered in block equalization is Inter-BlockInterference (IBI). The impact of IBI was investigated via behavior modeling. In lastpart of our thesis, two methods for IBI cancellation are compared and the proposal forhardware implementation was given.

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