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  • 151. Elias, Elizabeth
    et al.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Design of M-channel tree-structured filter banks with very low-complexity analysis filters2000In: IEEE International Conference on Electronics Circuits and Systems,2000, IEEE , 2000, p. 87-90 vol.1Conference paper (Refereed)
    Abstract [en]

    A class of M-channel tree-structured digital filter banks is considered with half-band IIR analysis filters and FIR synthesis filters. The filter banks approximate perfect reconstruction with an exact linear phase response and zero aliasing. This particular configuration has a very low-complexity analysis filter bank. In this paper we address the problem of minimizing the synthesis filter complexity, given the minimum-complexity analysis filters. The filter banks are designed using linear and nonlinear programming

  • 152. Elias, Elizabeth
    et al.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    M-channel tree-structured IIR/FIR filter banks with low-complexity analysis filters2000In: IEEE Nordic Signal Processing Symposium,2000, 2000Conference paper (Refereed)
  • 153. Elias, Elizabeth
    et al.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Tree-structured IIR/FIR octave-band filter banks with very low-complexity analysis filters2001In: IEEE International Symposium on Circuits and Systems,2001, 2001, p. 533-536Conference paper (Refereed)
    Abstract [en]

    A class of tree-structured octave-band digital filter banks is introduced. The filter banks make use of half-band IIR filters in the analysis bank and FIR filters in the synthesis bank which results in very low-complexity analysis filters. Further, the overall complexity is lower than, or comparable to, that of conventional filter banks. The overall filter banks approximate perfect reconstruction in the following sense. The distortion function is a linear-phase function approximating one in magnitude whereas the aliasing terms approximate zero. The filter banks are designed using linear and nonlinear programming. Design examples are included demonstrating the properties of the new filter banks

  • 154. Elias, Elizabeth
    et al.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Tree-structured IIR/FIR uniform-band and octave-band filter banks with very low-complexity analysis or synthesis filters2003In: Signal Processing, ISSN 0165-1684, E-ISSN 1872-7557, Vol. 83, no 9, p. 1997-2009Article in journal (Refereed)
    Abstract [en]

    This paper introduces new tree-structured uniform-band and octave-band digital filter banks (FBs). These FBs make use of half-band IIR filters in the analysis FBs and FIR filters in the synthesis FBs. The resulting FBs are asymmetric in the sense that the analysis FB has a very low arithmetic complexity whereas that in the synthesis FB is higher. However, compared with other asymmetric FBs, the proposed ones have in many cases a lower overall arithmetic complexity and delay. The proposed FBs have magnitude distortion but no phase distortion, further, the aliasing components are either zero (uniform-band case) or approximately zero (octave-band case). The FBs are designed using linear and nonlinear programming. Design examples are included demonstrating the properties of the proposed filters banks. ⌐ 2003 Published by Elsevier B.V.

  • 155. Elias, Elizabeth
    et al.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Two-channel IIR/FIR filter banks with very low-complexity analysis or synthesis filters: finite wordlength effects2001In: IEEE Midwest Symposium on Circuits and Systems,2001, 2001, p. 126-129Conference paper (Refereed)
    Abstract [en]

    A new class of two-channel IIR/FIR filter banks was introduced by the authors in 2000 with half-band IIR analysis filters and FIR synthesis filters. This type of filter bank features very low-complexity analysis filters and simultaneously a low overall complexity. In this paper, we consider finite-wordlength effects of these filter banks

  • 156.
    Eliasson, Viktor
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Digital videoregistrering2013Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    This Bachelor thesis examines the possibility of replacing an outdated, analog video recording system to a digital counterpart. It is key that the video and audio signals remain synchronized, generator locked and time stamped. It is up to nine different video sources and a number of audio sources to be recorded and treated in such a manner which enables synchronized playback. The  different video sources do not always follow a universal standard, and differ from format as well as resolution. This thesis aims to compare a number of state of the art commercial of the shelf solutions with proprietary hardware. Great emphasis is placed on giving a functional view over the system features and to evaluate different compression methods. The report also discusses different transmission, storage and playback options. The report culminates in a series of proposed solutions to sub problems which are solved and treated separately, leading to a final proposal from the author. The final draft set how well the system meets pre-set requirements to price.

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    fulltext
  • 157.
    Engström, Hampus
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ring, Christoffer
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Jämförelse av off-the-shelf-hårdvara för realtidsapplikationer2013Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [sv]

    Vid implementering av realtidsapplikationer krävs det att man kan använda hårdvaran på ett deterministiskt vis. En realtidsapplikation ställer stora krav på körtider och hur applikationen schemaläggs. Det är därför av största vikt att kontrollera om de uppfyller dessa krav. I detta examensarbete har tre system för realtidsapplikationer jämförts och en analys av framförallt sina beräkningsförmågor och hur pass deterministiskt de uppför sig gällande körtider har gjorts. Även andra aspekter så som utvecklingsmiljöer för mjukvara, tillbehör och effektförbrukning har jämförts. 

    Download full text (pdf)
    exjobb
  • 158.
    Eriksson, Johan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Nilsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Batterilös strömförsörjning av strömsnål granatelektronik2013Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    This bachelor thesis has been performed at Saab Dynamics AB (SBD) in Karlskoga, with the purpose to examine old designs of set-back-generators. A set-back-generator (SBG) shall provide instantaneous energy during firing of a projectile by a magnet moving through a coil. Previous designs of SBG:s is not providing enough energy to power electronics. New types of magnets have the potential to increase the energy yield significantly.

    SBD has a number of older SBG's and the work is based on these to examine the possibility to extract more energy by exchanging magnet. Other important parameters for an SBG's function has also been studied and tested in different configurations in the hope of further improvements. Expected results has then been analyzed and compared with the measurement results. On this basis suggestions and recommendations on a new SBG design has been delivered.

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    SBG
  • 159.
    Eriksson, Mattias
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and Implementation of a Real-Time FFT-core for Frequency Domain Triggering2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    To efficiently capture signal events when performing analog measurements, a competent toolbox is required. In this master thesis, a system for frequency domain triggering is designed and implemented. The implemented system provides advanced frequency domain trigger conditions, in order to ease the capture of a desired signal event. A real-time 1024-point pipelined feedforward FFT-core is implemented to transform the signal from the time domain to the frequency domain. The system is designed and synthesized for a Virtex-6 FPGA (XC6VLX240T) and is integrated into SP Devices’ digitizer ADQ1600. The implemented system is able to handle a continuous stream of 1.6GS/s at 16-bit. A small software API is developed that provides runtime configuration of the Triggering conditions.

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    fulltext
  • 160.
    Faust, M
    et al.
    Nanyang Technology University.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Chang, C-H
    Nanyang Technology University.
    Fast and VLSI efficient binary-to-CSD encoder using bypass signal2011In: ELECTRONICS LETTERS, ISSN 0013-5194, Vol. 47, no 1, p. 18-19Article in journal (Refereed)
    Abstract [en]

    The generation of a canonical signed digit representation from a binary representation is revisited. Based on the property that each nonzero digit is surrounded by a zero digit, a hardware-efficient conversion method using bypass instead of carry propagation is proposed. The proposed method requires less area per digit and the required bypass signal can be generated or propagated with only a single NOR gate. It is shown that the proposed converter outperforms previous converters and a look-ahead circuitry to speed up the generation of bypass signals is also proposed.

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    FULLTEXT01
  • 161.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, J.
    University of Politecn Madrid, Spain .
    Continuous-flow variable-length memoryless linear regression architecture2013In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 49, no 24, p. 1567-1568Article in journal (Refereed)
    Abstract [en]

    A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.

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    fulltext
  • 162.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, J
    University of Politecn Madrid, Spain .
    Sanchez, M A.
    University of Politecn Madrid, Spain .
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Pipelined Radix-2(k) Feedforward FFT Architectures2013In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 21, no 1, p. 23-32Article in journal (Refereed)
    Abstract [en]

    The appearance of radix-2(2) was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2(2) was extended to radix-2(k). However, radix-2(k) was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2(k) feedforward (MDC) FFT architectures. In feedforward architectures radix-2(k) canbe used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2(k) feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2(k) feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

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    fulltext
  • 163.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, Jesus
    University of Politecn Madrid.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Optimum Circuits for Bit Reversal2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 657-661Article in journal (Refereed)
    Abstract [en]

    This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

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    fulltext
  • 164.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, Jesus
    University of Politecn Madrid.
    Accurate Rotations Based on Coefficient Scaling2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 662-666Article in journal (Refereed)
    Abstract [en]

    This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.

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    fulltext
  • 165.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Qureshi, Fahad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 7, p. 2002-2012Article in journal (Refereed)
    Abstract [en]

    This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.

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    fulltext
  • 166.
    Gebreyohannes, Fikre Tsigabu
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Wireless Sensor Networks have found diverse applications from health to agriculture and industry. They have a potential to profound social changes, however, there are also some challenges that have to be addressed. One of the problems is the limited power source available to energize a sensor node. Longevity of a node is tied to its low power design. One of the areas where great power savings could be made is in nodal communication. Different schemes have been proposed targeting low power communication and short network latency. One of them is the introduction of ultra-low power wake-up receiver for monitoring the channel. Although it is a recent proposal, there has been many works published. In this thesis work, the focus is study and comparison of architectures for a wake-up receiver. As part of this study, an envelope detector based wake-up receiver is designed in 130nm CMOS Technology. It has been implemented in schematic and layout levels. It operates in the 2.4GHz ISM band and consumes a power consumption of 69µA at 1.2V supply voltage. A sensitivity of -52dBm is simulated while receiving 100kb/s OOK modulated wake-up signals.

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    Thesis report on ultra-low power wake-up receiver design
  • 167.
    Gundala, JayaKrishna
    Linköping University, Department of Electrical Engineering, Electronics System.
    A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. To achieve this, we use a noise-shaping loop between the first and later stages so that the input word length for the later stages remains smaller than in the case where we do not use the noise-shaping loop. However, the performance (SNR/ Noise-level) level should remain the same in both cases. This thesis aims at analyzing the implications of using a noise-shaping loop in between the decimation stages of a Δ-Σ ADC and also finding the appropriate decimation filter types that could be used in such a decimation system. This thesis also tries to compare the complexity introduced by using the noise-shaping loop with the reduction achieved in the later decimation stages in terms of the input word length. Filter required in the system will also be optimized using minimax optimization technique.

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    TQET30_Report_ES_JK
  • 168.
    Gustafsson, Andreas
    et al.
    FOI, Linköping.
    Folkesson, Kalle
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ohlsson, Henrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A simulation environment for integrated frequency and time domain simulations of a radar receiver.2001In: Swedish National Symposium on GigaHerz Electronics.,2001, 2001Conference paper (Other academic)
  • 169.
    Gustafsson, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Hir, Danijel
    Linköping University, Department of Electrical Engineering, Electronics System.
    High precision frequency synchronization via IP networks2010Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This  report  is  a  part  of  a  master  thesis  project  done  at  Ericsson  Linköping  incooperation with Linköpings Tekniska Högskola (LiTH). This project is divided intwo different parts.  The first part is to create a measurement node that collectsand processes data from network time protocol servers.   It is used to determinethe  quality  of  the  IP  network  at  the  node  and  detect  potential  defects  on  usedtimeservers or nodes on the networks.The second assignment is to analyze the collected data and further improve theexisting synchronization algorithm.  Ip communication is not designed to be timecritical and therefore the NTP protocol needs to be complemented with additionalsignal processing to achieve required accuracy.  Real time requirements limit thecomputational complexity of the signal processing algorithm.

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    FULLTEXT01
  • 170.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A difference based adder graph heuristic for multiple constant multiplication problems2007In: IEEE International Symposium on Circuits and Systems,2007, Piscataway: IEEE , 2007, p. 1097-Conference paper (Refereed)
  • 171.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Comments on `A 70 MHz multiplierless FIR Hilbert transformer in 0.35 $\mu$m standard CMOS library'2008In: IEICE transactions on fundamentals of electronics, communications and computer sciences, ISSN 1745-1337, Vol. E91-A, no 3, p. 899-900Article in journal (Refereed)
  • 172.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Graph-based code word selection for memoryless low power bus coding2004In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 40, no 24, p. 1531-1532Article in journal (Refereed)
  • 173.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Graph-based codeword selection for memoryless low-power bus coding2004In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 40, no 24, p. 1531-1532Article in journal (Refereed)
    Abstract [en]

    The problem of selecting codewords for memoryless low-power bus coding is considered. A graph-based procedure is proposed to obtain a subset of all possible codewords with minimum average energy consumption. The procedure can be applied to arbitrary cost models.

  • 174.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Lower bounds for constant multiplication problems2007In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 54, no 11, p. 974-978Article in journal (Refereed)
    Abstract [en]

    Lower bounds for problems related to realizing multiplication by constants with shifts, adders, and subtracters are presented. These lower bounds are straightforwardly calculated and have applications in proving the optimality of solutions obtained by heuristics.

  • 175.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Towards optimal multiple constant multiplication: a hypergraph approach2008In: Conference Record of the Asilomar Conference on Signals Systems and Computers, Piscataway, NJ: IEEE , 2008, p. 1805-1809Conference paper (Refereed)
    Abstract [en]

    In this work a novel approach to the multiple constant multiplication problem, i.e., finding a realization of a number of constant multiplications by using shift and addition with a minimum number of additions, is presented. By using a directed hypergraph, the problem comes down to finding a Steiner hypertree in the graph. The proposed formulation can guarantee an optimal solution, given that an optimal Steiner hypertree is found. However, finding a Steiner tree in a hypergraph is an NP-hard problem. Therefore, we present algorithms for different partial problems and discuss how they can be used to solve the whole problem. An integer linear programming model is used to solve the Steiner hypertree problem. The model can also include additional constraints such as adder depth and fan-out.

  • 176.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Coleman, J.O
    Dempster, A.G
    Macleod, M.D
    Low-complexity hybrid form FIR filters using matrix multiple constant multiplication2004In: Asilomar Conf. Signals, Syst., Comp,2004, 2004Conference paper (Other academic)
  • 177.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    DeBrunner, Linda
    Department of Electrical and Computer Engineering Florida State University.
    DeBrunner, Victor
    Department of Electrical and Computer Engineering Florida State University.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    On the design of sparse half-band like FIR filters2007In: Asilomar Conference on Signals, Systems, and Computers,2007, Monterey, CA: IEEE , 2007Conference paper (Refereed)
  • 178.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew G.
    University of Westminster, London, UK.
    On the use of multiple constant multiplication in polyphase FIR filters and filter banks2004In: Proceedings of the 6th Nordic Signal Processing Symposium, 2004. NORSIG 2004, IEEE , 2004, p. 53-56Conference paper (Other academic)
    Abstract [en]

    Multiple constant multiplication (MCM) has been shown to be an efficient way to reduce the number of additions and subtractions in FIR filter implementations. However, for polyphase decomposed FIR filters and filter banks, the problem can be formulated in three different ways. Eitheras one MCM block with all coefficients, one MCM block for each subfilter, or as a matrix MCM block. In this work we compare the approaches in terms of complexity, both for the MCM blocks and for the remaining hardware, suchas structural additions and delay elements.

  • 179.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Dempster, Andrew G.
    Macleod, M.D
    Comparison of graphical and sub-expression elimination methods for design of efficient multipliers2004In: Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004, Volume 1, IEEE , 2004, p. 72-76Conference paper (Other academic)
    Abstract [en]

    Relationships are examined between two traditional strategies used to design "multiplier blocks": graphical methods and common subexpression elimination (CSE), four applications: single multipliers, multiplier blocks (several products of a single multiplicand), FIR filters and matrix multipliers are compared. A new representation shows how graphical designs can be extracted from CSE designs. Algorithms for both approaches are compared. A new graphical algorithm for FIR filter design and new results for CSE in the multiple product case are presented so comparison can be made for all applications. We conclude that for simpler problems, graphical methods are best, while CSE works better for the more complex problems

  • 180.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Dempster, Andrew G.
    University of Westminster, London, UK.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multiplier blocks using carry-save adders2004In: Proceedings of the 2004 International Symposium on  Circuits and Systems, 2004. ISCAS '04, Volume 2, 2004, p. 473-476Conference paper (Refereed)
    Abstract [en]

    Multiplier blocks have been shown to require a small number of adders for multiplying one data sample with multiple, constant, coefficients. The previously proposed multiplier block algorithms have been using carry-propagation adders. However, for high-speed applications carry-save adders are a better choice. Although it is possible to map carry-save adders to carry-propagation adders, it is shown that this mapping is inconsistent in the number of carry-save adders required for a given number of carry-propagation adders for multiplier blocks. Therefore, a multiplier block algorithm for carry-save adders is proposed. It is shown that the proposed algorithm is producing multiplier blocks with consistently fewer carry-save adders compared with starting with a carry-propagation multiplier block and mapping it to carry-save adders. Further, it is shown that the proposed algorithm produces multiplier blocks with fewer carry-save adders than algorithms based on subexpression sharing

  • 181.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Macleod, Malcolm
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Simplified Design of Constant Coefficient Multipliers2006In: Circuits, systems, and signal processing, ISSN 0278-081X, E-ISSN 1531-5878, Vol. 25, no 2, p. 225-251Article in journal (Refereed)
    Abstract [en]

    In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.

  • 182.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Extended results for minimum-adder constant integer multipliers2002In: IEEE International Symposium on Circuits and Systems,2002, Piscataway, NJ: IEEE , 2002, p. I/73-Conference paper (Refereed)
    Abstract [en]

    By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits. The average savings are more than 25% for 19 bits compared with CSD multipliers. The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets. Thus, fewer graphs need to be evaluated. A classification of the graphs reduces the effort to search the coefficient space further.

  • 183.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Low-complexity general FIR filters based on Winograd's inner product algorithm2013Conference paper (Other academic)
  • 184.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Complexity comparison of linear-phase half-band and general FIR filters2006In: IEEE Asia Pacific Conference on Circuits and Systems,2006, Piscataway: IEEE , 2006Conference paper (Refereed)
  • 185.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Complexity comparison of linear-phase Mth-band and general FIR filters2007In: IEEE International Symposium on Circuits and Systems,2007, Piscataway: IEEE , 2007, p. 2335-Conference paper (Refereed)
  • 186.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Efficient implementation of FIR filter based rational sampling rate converters using constant matrix multiplication2006In: Asilomar Conference on Signals, Systems, and Computers,2006, Piscataway: IEEE , 2006Conference paper (Refereed)
  • 187.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Single Filter Frequency Masking High-Speed Recursive Digital Filters2003In: Circuits, systems, and signal processing, ISSN 0278-081X, E-ISSN 1531-5878, Vol. 22, no 2, p. 219-238Article in journal (Refereed)
    Abstract [en]

    For recursive filter the maximal sample frequency is bounded by the recursive loops in the filter. [In this paper, it is understood that recursive filters are infinite-length impulse response (IIR) filters.] In this work, a filter structure based on the use of the frequency masking approach is presented that increases the maximal sample frequency for narrowband and wideband filters by introducing more delay elements in the recursive loops. By using identical subfilters (except for the periods), the subfilters can be mapped using folding to a single pipeline/interleaved arithmetic structure yielding an area-efficient implementation. The filters are potentially suitable for low-power implementation by using power supply voltage scaling techniques. In this work, the design of the filters is discussed and estimations of the ripples are derived. Two examples show the viability of the proposed method.

  • 188.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Single filter frequency-response masking FIR filters2003In: Journal of Circuits, Systems and Computers, ISSN 0218-1266, Vol. 12, no 5, p. 601-630Article in journal (Refereed)
    Abstract [en]

    In this work filter structures that decrease the required number of multipliers and adders for implementation of linear-phase FIR filters using frequency-response masking techniques are introduced. The basic idea of the proposed structures is that identical subfilters are used. This leads to the same arithmetic structure can be multiplexed in the implementation, reducing the number of required multipliers and adders. The subfilters are mapped using the folding transformation to obtain an area-efficient time-multiplexed (or pipeline/interleaved) implementation. Both narrow-band and wide-band frequency-response masking as well as arbitrary bandwidth frequency-response masking techniques are considered. The filter design is discussed and for each filter structure the limits on the specifications are derived. Designed examples show the usefulness of the proposed structures.

  • 189.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An empirical study on standard cell synthesis of elementary function look-up tables2008In: Conference Record - Asilomar Conference on Signals, Systems and Computers, Piscataway, NJ: IEEE , 2008, p. 1810-1813Conference paper (Refereed)
    Abstract [en]

    When hardware for implementing elementary functions is discussed it is often stated that for "small enough" tables it is possible to just synthesize the HDL description to standard cells. In this work we investigate this fact and show that the resulting cell area primarily depends on the smallest of the number of input and output bits, while the contribution of the larger of the two bit-widths is significantly smaller.

  • 190.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multiplierless piecewise linear approximation of elementary functions2006In: Asilomar Conference on Signals, Systems, and Computers,2006, Piscataway: IEEE , 2006Conference paper (Refereed)
  • 191.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of polyphase decomposed FIR filters for interpolation and decimation using multiple constant multiplication techniques2006In: IEEE Asia Pacific Conference on Circuits and Systems,2006, Piscataway: IEEE , 2006, p. 924-927Conference paper (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. Almost all work has been focused on single rate FIR filters. However, for polyphase interpolation and decimation FIR filters there are two different implementation alternatives. For interpolation, direct form subfilters lead to fewer registers as they can be shared among the subfilters. The arithmetic part corresponds to a matrix vector multiplication. Using transposed direct form subfilters, the registers can not be shared, while the arithmetic part has the same input to all coefficients, and, hence, the redundancy between the coefficients is expected to be higher. For decimation filters the opposite holds for direct form and transposed direct form subfilters. In this work we discuss the trade-off between adders/subtracters and registers, and present implementation results for area, speed, and power for different realizations

  • 192.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Optimization and Quantization Effects for Sine and Cosine Computation Using a Sum of Bit-Products2005In: Asilomar Conference on Signals, Systems, and Computers,2005, Piscataway, NJ: IEEE , 2005, p. 1347­-Conference paper (Refereed)
    Abstract [en]

    Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products is used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The objective of this work is to study the effects of this removal and also the finite wordlength representation of the weights. Furthermore, optimization problems are formulated that can be used to minimize the maximum absolute error, the average absolute error, and the mean square error for the output values, respectively, as well as implementation complexity under error constraints.

  • 193.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Khursheed, Khursheed
    Mittuniversitetet.
    Imran, Muhammad
    Mittuniversitetet.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Generalized overlapping digit patterns for multi-dimensional sub-expression sharing2010In: 1st International Conference on Green Circuits and Systems, ICGCS 2010, 2010, p. 65-68Conference paper (Refereed)
    Abstract [en]

    Sub-expression sharing is a technique that can be applied to reduce the complexity of linear time-invariant non-recursive computations by identifying common patterns. It has recently been proposed that it is possible to improve the performance of single and multiple constant multiplication by identifying overlapping digit patterns. In this work we extend the concept of overlapping digit patterns to arbitrary shift dimensions, such as shift in time (FIR filters). © 2010 IEEE.

  • 194.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Ohlsson, Henrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Low Power Decimation Filter Architecture for High-Speed Single-Bit Sigma-Delta Modulation2005In: IEEE International Symposium on Circuits and Systems,2005, Piscataway, NJ: IEEE , 2005, p. 1453-Conference paper (Refereed)
    Abstract [en]

    In this work a novel architecture suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation is proposed. By using efficient data and coefficient representation the total number of partial products is reduced leading to low power consumption. The work is focused on filters designed based on cascaded comb filters, although the approach is applicable to any FIR filter.

  • 195.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ohlsson, Henrik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Improved multiple constant multiplication using minimum spanning trees2004In: Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004,  Volume 1 / [ed] Michael B. Matthews, IEEE , 2004, p. 63-66Conference paper (Other academic)
    Abstract [en]

    Recently, a novel technique for the multiple constant multiplication (MCM) problem using minimum spanning trees (MSTs) has been proposed. The approach works by finding simple differences between the coefficients to realize and then applying the same method to the differences (which is an MCM problem as well). Each iteration is divided into two steps. First, finding a minimum spanning tree in the graph describing the differences between the coefficients. Second, as each edge in the graph may correspond to more than one difference, one difference is selected for each edge in the MST. Generally, both these stages have multiple solutions. The aim of this work is to more closely study how the MST and the differences should be selected to give better total results. It is also discussed how the two stages in each iteration may be joined into one problem.

  • 196.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ohlsson, Henrik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-complexity constant coefficient matrix multiplication using a minimum spanning tree approach2004In: Proceedings of the 6th Nordic Signal Processing Symposium, 2004. NORSIG 2004, IEEE , 2004, p. 141-144Conference paper (Refereed)
    Abstract [en]

    In this paper a novel approach for realizing constant coefficient matrix multiplication using few additions and subtractions is proposed. This method is applicable in, e.g., FIR filter banks, transforms, and polyphase form FIR filters for sample rate changes. Examples show that the proposed method yields good results compared to realizing the matrix multiplication by utilizing multiple coefficient multiplication techniques for the rows or columns separately.

  • 197.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Olofsson, Mikael
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Data Transmission.
    Complexity reduction of constant matrix computations over the binary field2007In: International Workshop on the Arithmetic of Finite Fields,2007, Heidelberg: Springer , 2007, p. 103-Conference paper (Refereed)
  • 198.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Qureshi, Fahad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication2010In: IEEE Signal Processing Letters, ISSN 1070-9908, E-ISSN 1558-2361, Vol. 17, no 2, p. 173-176Article in journal (Refereed)
    Abstract [en]

    Multiplication by constants can be efficiently realized using shifts, additions, and subtractions. In this work we consider how to select a fixed-point value for a real valued, rational, or floating-point coefficient to obtain a low-complexity realization. It is shown that the process, denoted addition aware quantization, often can determine coefficients that has as low complexity as the rounded value, but with a smaller approximation error by searching among coefficients with a longer wordlength.

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  • 199.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Tahmasbi Oskuii, Saeeid
    Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Kjeldsberg, Per Gunnar
    Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
    Switching activity reduction of MAC-based FIR filters with correlated input data2007In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2007, Heidelberg: Springer , 2007, p. 526-Conference paper (Refereed)
  • 200.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A novel approach to multiple constant multiplication using minimum spanning trees2002In: Midwest Symposium on Circuits and Systems,2002, Piscataway, NJ: IEEE , 2002, p. 652-Conference paper (Refereed)
    Abstract [en]

    In this work a novel approach to multiple constant multiplication based on minimum spanning trees is proposed. Each required coefficient is assigned to a vertex in a graph. The vertices are connected with weighted edges, where each edge weight corresponds to the number of adders required to derive one of the coefficient from the previous. The graph can be used to solve for the minimum spanning tree, which leads to a realization with a small number of adders. The optimal minimum spanning tree can be found in polynomial time. It is also possible to add extra constraints to the spanning tree, such as limited out-degree (corresponds to fan-out) and limited tree height (corresponds to delay). These problems are harder to solve, but there are good heuristics available. It is shown by simulation that the performance of the proposed algorithm is comparable with recently published algorithms.

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