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  • 151.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sampling and analog despreading of a DS/SS modulated signal directly on the IF waveformManuscript (preprint) (Other academic)
    Abstract [en]

    This paper introduces a method how to interpret the user data directly from a direct-sequence spread quaternary-phase-shift keyed (DS/QPSK) modulated wave-form without first demodulate nor digitize the waveform. The Methos is to sample the waveform, to weight each individual sample with -1, 0, or +1 according to the spreading code, and finally to accumulate these weighted samples. The wave-form carrier frequency is chosen as a multiple of the chop rate. This demonstrated with a 0.6μm CMOS test chip that is fed with a 2Mchip/s DS/QPSK modulated signal, shaped with a Root-Nyquist filter. The measurement result cerifies correct interpreting of transmitted data symbols (user data) represented over seven chips. The test chip further exhibit a measured noise figure 16.2dB at a bandwidth expansion of 7.

  • 152.
    Duppils, Mattias
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    MERC (Microelectronics Research Center), Ericsson Components AB, Kista, Sweden.
    Realization of fully programmable narrow-band FIR filters with SC technique1999In: 42nd Midwest Symposium on Circuits and Systems, 1999, 1999, p. 464-468Conference paper (Refereed)
    Abstract [en]

    A methodology to implement fully programmable narrow-band FIR filters with switched capacitor (SC) technique is presented. The SC implementation, which offers a fixed order of complexity, is suitable for high-order FIR filter realizations followed by decimation. The filter performance and the requirements are analyzed

  • 153.
    Dussarrat, Johann
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Balondrade, Gael
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of a Test Bench for Battery Management2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The report deals with energy conservation, mainly in the field of portable energy, which is asubject that today raises questions around the world. This report describes the design and theimplementation of a Battery Management System on the platform NI ELVIS II+ managed bythe software Labview. The first aim has been on finding information about the design of theBattery Management System that corresponds to the choice of the battery itself. The systemwas designed completely independent with different charging methods, simulations ofdischarge, and its own cell balancing, as a 3 cells battery pack was used. The battery chosenwas the lithium-ion technology that has the most promising battery chemistry and is the fastestgrowing. Several experimentations and simulations have been done, with and without cellbalancing that permited to highlight that the cell balancing is mandatory in a Batterymanagement System. Furthermore, a simulation of use of the battery in an Electrical Vehiclewas made, which can lead to conclude that the Lithium-Ion battery must be manageddifferently to be used in the application of an Electrical Vehicle.

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    Design of a Test Bench for Battery Management
  • 154.
    Ebrahimi Mehr, Golnaz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

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    fulltext
  • 155.
    Eckerbert, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers.
    Cycle-true leakage current modeling for CMOS gates.2001In: IEEE International Symposium on Circuits and Systems ISCAS,2001, Piscataway: IEEE , 2001, Vol. 5, p. 507-510Conference paper (Refereed)
    Abstract [en]

    This paper addresses cycle-true leakage current modeling for static CMOS gates. An approach to leakage power estimation is suggested which deals with some of the issues associated with the complex dynamic behavior of the gate. The paper discusses problems with defining gate leakage power. It then suggests a modeling approach, which separates the static leakage from the dynamic switch and short-circuit power. The model is used to achieve cycle-true leakage power estimation which is important as 20% of the power consumption in the designs of today can be leakage power. The importance of leakage power modeling will continue to grow as leakage power scales exponentially with reduced VT

  • 156.
    Eckerbert, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers.
    Interconnect-driven short-circuit power modeling.2001In: Euromicro Symposium on Digital Systems Design.,2001, 2001, p. 414-Conference paper (Refereed)
  • 157.
    Edman, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Björklid, Anders
    Saab Dynamics.
    Söderquist, Ingemar
    Saab Dynamics.
    A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters1998In: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers, 1998, p. 54-55Conference paper (Refereed)
    Abstract [en]

    This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

  • 158.
    Edman, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Christensen, J
    Emrich, A.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, p. 258-265Article in journal (Refereed)
    Abstract [en]

    The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

  • 159.
    Edman, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Timing closure through a globally synchronous, timing partitioned design methodology.2004In: DAC,2004, New York: ACM, Inc. , 2004, p. 71-Conference paper (Refereed)
  • 160.
    Edman, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Synchronous Latency-Insensitive Design for Multiple Clock Domain2005In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), IEEE Explore , 2005, p. 83-86Conference paper (Refereed)
    Abstract [en]

    Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.

  • 161.
    Eidenvall, Per
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Gran, Nils
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    High Level Ultra Low Power Transmitters for the MICS Standard2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids anddrug delivery systems are increasinglymore important and frequently used in the health caresystem. This type of devices have historically used inductive coupling as communicationmedium. Newdemands on accessibility and increased performance in technology drives newresearch toward using radio communications. The FCCMICS radio standard are specificallydevoted for implantable devices.Basically all published research on transmitters in this area are using frequency shift keying(FSK) modulation. The purpose of this thesis is to explore the viability of using phase shiftkeying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.

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    FULLTEXT01
  • 162.
    Eklund, Jan-Erik
    et al.
    Infineon Techn. Linköping.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Influence of metastability errors on SNR in successive-approximation A/D converters.2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, p. 191-198Article in journal (Refereed)
  • 163.
    Ekstrand, Jan
    et al.
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Health Sciences.
    Hägglund, Martin
    Linköping University, Department of Medical and Health Sciences, Division of Physiotherapy. Linköping University, Faculty of Health Sciences.
    Tornqvist, Henrik
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Health Sciences.
    Kristenson, Karolina
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Health Sciences.
    Bengtsson, Håkan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Magnusson, Henrik
    Linköping University, Department of Medical and Health Sciences, Division of Physiotherapy. Linköping University, Faculty of Health Sciences.
    Waldén, Markus
    Linköping University, Department of Medical and Health Sciences, Social Medicine and Public Health Science. Linköping University, Faculty of Health Sciences.
    Upper extremity injuries in male elite football players2013In: Knee Surgery, Sports Traumatology, Arthroscopy, ISSN 0942-2056, E-ISSN 1433-7347, Vol. 21, no 7, p. 1626-1632Article in journal (Refereed)
    Abstract [en]

    To investigate the epidemiology of upper extremity injuries in male elite football players and to describe their characteristics, incidence and lay-off times. less thanbrgreater than less thanbrgreater thanBetween 2001 and 2011, 57 male European elite football teams (2,914 players and 6,215 player seasons) were followed prospectively. Time-loss injuries and exposure to training and matches were recorded on individual basis. less thanbrgreater than less thanbrgreater thanIn total, 11,750 injuries were recorded, 355 (3 %) of those affected the upper extremities giving an incidence of 0.23 injuries/1,000 h of football. The incidence in match play was almost 7 times higher than in training (0.83 vs. 0.12 injuries/1,000 h, rate ratio 6.7, 95 % confidence interval 5.5-8.3). As much as 32 % of traumatic match injuries occurred as a result of foul play situations. Goalkeepers had a significantly higher incidence of upper extremity injuries compared to outfield players (0.80 vs. 0.16 injuries/1,000 h, rate ratio 5.0, 95 % confidence interval 4.0-6.2). The average absence due to an upper extremity injury was 23 +/- A 34 days. less thanbrgreater than less thanbrgreater thanUpper extremity injuries are uncommon among male elite football players. Goalkeepers, however, are prone to upper extremity injury, with a five times higher incidence compared to outfield players. less thanbrgreater than less thanbrgreater thanII.

  • 164.
    Eriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Henriksson, Tomas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Larsson-Edefors, Per
    Chalmers.
    Full-custom vs standard-cell based design - An adder comparison.2002In: Swedish System-on-Chip conference.,2002, 2002Conference paper (Other academic)
  • 165.
    Eriksson, Henrik
    et al.
    Dept of Computer Engineering Chalmers tekniska högskola.
    Henriksson, Tomas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Larsson-Edefors, Per
    Dept of Computer Engineering Chalmers tekniska högskola.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study2003In: Asia South Pacific Design Automation Conference,2003, 2003, p. 507-Conference paper (Refereed)
  • 166.
    Eriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.2001In: IEEE International Symposium on Circuits and Systems ISCAS.,2001, Piscataway: IEEE , 2001, Vol. 4, p. 84-87Conference paper (Refereed)
    Abstract [en]

    A fast and area-efficient 32-b Manchester carry-bypass adder with low energy-delay product is presented in this paper. The high speed is achieved by the use of optimized bypass circuitry and fast repeater elements in the carry path. The fabricated adder has a measured worst-case delay of 2.8 ns and consumes 30 μW/MHz

  • 167.
    Eriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers.
    Marnane, W.P.
    A regular parallel multiplier which utilizes multiple carry-propagate adders.2001In: IEEE International Symposium on Circuits and Systems ISCAS.,2001, Piscataway: IEEE , 2001, Vol. 4, p. 166-169Conference paper (Refereed)
    Abstract [en]

    A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers

  • 168.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A Study and Implementation of On-Chip EMC Techniques2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    ElectroMagnetic Interferences (EMI) are emerging problems in today's high speed circuits. There are several examples that these interferences affected the circuits and systems. This work tries to reduce the abovementioned problems in synchronous systems by modifying the clock signal such that it produces less interferers.

    In this thesis first EMI and its sources and related definitions are studied in Chap.1 and then a theoretical background is presented in Chap.2, finally Chap.3 and Chap.4 are dedicated to circuit implementation and simulation results, respectively.

    A novel multi-segment clocking scheme is presented in this thesis. An analytical methods for formal verification of advantages of this clocking method is presented in Chap.2. Chap.3 and Chap.4 also are devoted to implementation, simulation and comparison of proposed clocking method versus other methods.

    Since proposed clocking method does not set any constraint on timing (speed of the circuit) and does not impose very high extra power consumption on the circuit, compared to the conventional clocking, this method could be used to reduce interferences in system.

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    FULLTEXT01
  • 169.
    Farahini, N.
    et al.
    Kungl. Tekniska högskolan, KTH, Sweden.
    Hemani, A.
    Kungl. Tekniska högskolan, KTH, Sweden.
    Lansner, A.
    Kungl. Tekniska högskolan, KTH, Sweden.
    Clermidy, F.
    Kungl. Tekniska högskolan, KTH, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain2014In: Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, IEEE , 2014, p. 578-585Conference paper (Refereed)
    Abstract [en]

    A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

  • 170. Order onlineBuy this publication >>
    Fazli Yeknami, Ali
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power Delta-Sigma Modulators for Medical Applications2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Biomedical electronics has gained significant attention in healthcare. A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and communication subsystem, each of which must be designed for minimum energy consumption to adhere to the stringent energy constraint.

    The ADC is a key building block in the sensing stage of the implantable biomedical devices. To lower the overall power consumption and allow full integration of a complete biomedical sensor interface, it is desirable to integrate the entire analog front-end, back-end ADC and digital processor in a single chip. While digital circuits benefit substantially from the technology scaling, it is becoming more and more difficult to meet the stringent requirements on linearity, dynamic range, and power-efficiency at lower supply voltages in traditional ADC architectures. This has recently initiated extensive investigations to develop low-voltage, lowpower, high-resolution ADCs in nanometer CMOS technologies. Among different ADCs, the ΔΣ converter has shown to be most suitable for high-resolution and low-speed applications due to its high linearity feature.

    This thesis investigates the design of high-resolution and power-efficient ΔΣ modulators at very low frequencies. In total, eight discrete-time (DT) modulators have been designed in a 65nm CMOS technology: two active modulators, two hybrid active-passive modulators, two ultra-low-voltage modulators operated at 270mV and 0.5V supply voltages, one fully passive modulator, and a dual-mode ΔΣ modulator using variable-bandwidth amplifiers.

    The two active modulators utilize traditional feedback architecture. The first design presents a simple and robust low-power second-order ΔΣ modulator for accurate data conversion in implantable rhythm management devices such as cardiac pacemakers. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-Vth devices in analog circuits and switches. An 80dB SNR (13-bit) was achieved at the cost of 2.1μW power in 0.033mm2 chip core area. The second design introduces a third-order modulator adopting the switched-opamp and partially body-driven gain-enhanced techniques in the OTAs for low-voltage and low-power consumption. The modulator achieves 87dB SNDR over 500Hz signal bandwidth, consuming 0.6μW at 0.7V supply.

    The two hybrid modulators were designed using combined SC active and passive integrators to partially eliminate the analog power associated with the active blocks. The first design employs an active integrator in the 1st stage and a passive integrator in the less critical 2nd stage. A 73.5dB SNR (12-bit) was achieved at the cost of 1.27μW power in a 0.059mm2 chip core area. The latter modulator utilizes a fourth-order active-passive loop filter with only one active stage. The input-feedforward architecture is used to improve the voltage swing prior to the comparator of the traditional passive modulators, which enables a simpler comparator design without requiring a preamplifier. It also allows the use of three successive passive filters to obtain a higher-order noise shaping. The modulator attains 84dB SNR while dissipating 0.4μW power at a 0.7V supply.

    Two ultra-low-voltage DT modulators operating at 0.5V and the state-of-the-art 270mV power supplies were proposed. The former modulator employs fully passive loop filter followed by a 0.5V preamplifier and dynamic comparator, whereas the latter one exploits the inverter-based integrators combined with clock boosting scheme for adequate switches overdrive voltage. The first design incorporates a gain-boosted scheme using charge redistribution amplification in the passive filter as well as a body-driven gain-enhanced preamplifier prior to the comparator in order to compensate for the gain shortage. It attains 75dB SNR consuming 250nW power, which is a record amongst the state-of-the-art ultra-lowpower ΔΣ modulators. The second design uses feedforward architecture that suggests low integrators swing, enabling ultra-low-voltage operation. The degraded gain, GBW and SR of the inverter amplifiers operating at such a low voltage are enhanced by a simple current-mirror output stage. The attained FOM is 0.31pJ/step.

    A fully passive DT modulator was presented aiming for analog power reduction, the dominant part of the power in the active modulators. A careful analysis of the non-idealities in the passive filter, including the noise, parasitic effect, and integrator’s leakage were essential to meet the performance requirement necessary for an implantable device. The chip was tested simultaneously with its active counterpart, showing significant power reduction at the cost of 4× core area and 12dB SNR loss.

    The designed dual-mode modulator employs variable-bandwidth amplifiers in combination with oversampling ratio to provide tunable resolution. This work presents the design, implementation, and test results of a two-stage amplifier using the second stage replica, that provides tunable GBW with consistent DC gain.

    List of papers
    1. A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
    Open this publication in new window or tab >>A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
    2013 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, p. 69-78Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

    Place, publisher, year, edition, pages
    Springer, 2013
    Keywords
    Analog-to-digital converter (ADC), Delta-sigma modulator, Operational transconductance amplifier (OTA), Medical implant device Load-compensated two-stage amplifier
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-100027 (URN)10.1007/s10470-013-0087-x (DOI)000324828000007 ()
    Conference
    The 30th NORCHIP conference, November 12, Copenhagen, Denmark
    Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2019-09-05Bibliographically approved
    2. Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications
    Open this publication in new window or tab >>Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications
    2010 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2010, p. 229-232Conference paper, Published paper (Refereed)
    Abstract [en]

    High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

    Place, publisher, year, edition, pages
    IEEE, 2010
    Keywords
    CMOS integrated circuits, bioelectric phenomena, biomedical electronics, biomolecular electronics, low-power electronics, operational amplifiers, sigma-delta modulation
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-65455 (URN)978-1-4244-5307-8 (ISBN)
    Conference
    IEEE International Conference on Signal and Electronic Systems, September 7-10, Gliwice, Poland
    Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2019-09-05Bibliographically approved
    3. A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition
    Open this publication in new window or tab >>A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition
    2012 (English)In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, p. 336-339Conference paper, Published paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

    Place, publisher, year, edition, pages
    IEEE, 2012
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-96534 (URN)10.1109/BioCAS.2012.6418428 (DOI)000316563200099 ()978-1-4673-2291-1 (ISBN)
    Conference
    IEEE Biomedical Circuits and Systems Conference (BioCAS 2012), 28-30 November 2012, Hsinchu, Taiwan
    Available from: 2013-08-21 Created: 2013-08-20 Last updated: 2019-09-05Bibliographically approved
    4. A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
    Open this publication in new window or tab >>A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
    2013 (English)In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, p. 2010-2013Conference paper, Published paper (Refereed)
    Abstract [en]

    A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

    Series
    IEEE International Symposium on Circuits and Systems (ISCAS), 2013, ISSN 0271-4302 ; 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-97263 (URN)10.1109/ISCAS.2013.6572265 (DOI)000332006802059 ()978-1-4673-5760-9 (ISBN)
    Conference
    The IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013
    Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2019-09-05Bibliographically approved
    5. A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier
    Open this publication in new window or tab >>A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier
    2013 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    An ultra-low-voltage low-power switched-capacitor ΔΣ modulator running at a supply voltage as low as 270 mV is presented for medical implant devices. To reduce the supply voltage and power consumption, an inverter-based amplifier is used in the integrator, whose DC-gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. The entire modulator operates at 270 mV supply only, while the switches are driven by charge pump clock doubler. Designed in 65 nm CMOS and clocked at 256 kHz, the simulation results show that the converter achieves 64.4 dB signal-to-noise-ratio (SNR) and 61 dB signal-to-noise-and-distortionratio (SNDR) in 1 kHz bandwidth while consuming 0.85 "W power.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-102896 (URN)
    Available from: 2014-01-07 Created: 2014-01-07 Last updated: 2019-09-05Bibliographically approved
    6. Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
    Open this publication in new window or tab >>Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
    2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, p. 358-370Article in journal (Refereed) Published
    Abstract [en]

    A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

    Place, publisher, year, edition, pages
    IEEE, 2014
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-102756 (URN)10.1109/TCSI.2013.2278346 (DOI)000331191800004 ()
    Available from: 2013-12-20 Created: 2013-12-20 Last updated: 2019-09-05Bibliographically approved
    7. A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
    Open this publication in new window or tab >>A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
    2013 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

    Place, publisher, year, edition, pages
    IEEE, 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-97265 (URN)10.1109/VLSI-SoC.2013.6673235 (DOI)000332046100001 ()
    Conference
    IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 7-9 October, Istanbul, Turkey
    Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2019-09-05Bibliographically approved
    8. A Programmable-Bandwidth Amplifier for Ultra-Low-Power Switched-Capacitor Application
    Open this publication in new window or tab >>A Programmable-Bandwidth Amplifier for Ultra-Low-Power Switched-Capacitor Application
    2011 (English)In: IEEE European Conference on Circuit Theory and Design (ECCTD), IEEE conference proceedings, 2011, p. 761-764Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation modes (400, 700, and 900 kHz), while 52-dB DC gain is preserved in a 5-pF load. The OTA consumes 275-nW static power in a 400 kHz unity-gain frequency and 375-nW static power in a 900 kHz unity-gain frequency from 0.9-V supply.

    Place, publisher, year, edition, pages
    IEEE conference proceedings, 2011
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-73029 (URN)10.1109/ECCTD.2011.6043849 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
    Conference
    20th European Conference on Circuit Theory and Design, Linköping, 29-31 August, Linköping, Sweden
    Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2019-09-05Bibliographically approved
    9. A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System
    Open this publication in new window or tab >>A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System
    2013 (English)In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p. 1918-1921Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

    Series
    IEEE International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-97264 (URN)10.1109/ISCAS.2013.6572242 (DOI)000332006802036 ()978-1-4673-5760-9 (ISBN)
    Conference
    The IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013
    Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2019-09-05Bibliographically approved
    Download full text (pdf)
    Low-Power Delta-Sigma Modulators for Medical Applications
  • 171.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices2013In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, p. 2010-2013Conference paper (Refereed)
    Abstract [en]

    A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

  • 172.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage2013Conference paper (Refereed)
    Abstract [en]

    A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

  • 173.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, p. 336-339Conference paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 174.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, p. 69-78Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 175.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier2013Manuscript (preprint) (Other academic)
    Abstract [en]

    An ultra-low-voltage low-power switched-capacitor ΔΣ modulator running at a supply voltage as low as 270 mV is presented for medical implant devices. To reduce the supply voltage and power consumption, an inverter-based amplifier is used in the integrator, whose DC-gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. The entire modulator operates at 270 mV supply only, while the switches are driven by charge pump clock doubler. Designed in 65 nm CMOS and clocked at 256 kHz, the simulation results show that the converter achieves 64.4 dB signal-to-noise-ratio (SNR) and 61 dB signal-to-noise-and-distortionratio (SNDR) in 1 kHz bandwidth while consuming 0.85 "W power.

  • 176.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System2013In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p. 1918-1921Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

  • 177.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low voltage and process variation tolerant SRAM cell in 90-nm CMOS2010In:  International Symposium on VLSI Design Automation and Test, IEEE , 2010, p. 78-81Conference paper (Refereed)
    Abstract [en]

    In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

  • 178.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, p. 358-370Article in journal (Refereed)
    Abstract [en]

    A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

  • 179.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of OTAs for Ultra-Low-Power Sigma-Delta ADCs in Medical Applications2010In: Swedish System-on-Chip Conference (SSoCC), 2010Conference paper (Other academic)
    Abstract [en]

    High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

  • 180.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications2010In: International Conference on Signals and Electronic Systems, IEEE , 2010, p. 229-232Conference paper (Refereed)
    Abstract [en]

    High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

  • 181.
    Folkesson, Kalle
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ADC modeling from a system perspective and design of RF-sampling radio receivers2004Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The analog-to-digital converter (ADC) is the key component in many modem electronic systems. Examples are wire-line communication systems such as digital subscriber line modems, wireless communication systems such as radio receivers, and sensor systems such as military radar. To perform complete system simulations on these complex systems, high-level models are necessary. However, despite the fact that the ADC performance has a great impact on the system performance, most current design environments only include very simple ADC models. To investigate the relevance of accurate ADC models, a high-level MATLAB model of a successive-approximation ADC including realistic errors is developed. This model is integrated into two application models: an asymmetric digital subscriber line modem and an frequency-modulated continuous wave radar receiver. System simulations are performed and compared to the case when a simple ADC model is used.

    The advances in wireless communication have led to a demand for portable multi-standard radio transceivers, which should be small, low-power, and low-cost. The aim for the future is to use software-defined radio, where one set of hardware is reconfigured by software and can thus handle several standards. One component in a possible software radio, a flexible RF-sampling front-end, is proposed and experimentally demonstrated. It includes an RF-sampling quadrature downconverter, tunable band-pass finite impulse response filters with decimation, and a multi-phase clock-generation circuit capable of very accurate phase shifts. Accurate phase shift between I and Q channels and low jitter are key issues in sampling radio-receiver design and circuitry as well as measurement methods to support this are developed.

  • 182.
    Folkesson, Kalle
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    Microelectronic Research Center, Ericsson Components AB, Kista, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Gustafsson, Andreas
    Defence Research Establishment (FOA), Department of Microwave Technology, Linköping, Sweden.
    A MATLAB-Based ADC Model for RF System Simulation2000In: Proceedings of the Swedish National Symposium on GigaHerz Electronics, 2000, p. 273-276Conference paper (Other academic)
    Abstract [en]

    Analog-to-digital converters (ADCs) are often the limiting components in signal processing systems. When a system is designed, the demands on the ADC are often set unnecessary high to ensure that the system will work. To find reasonable demands on the ADC, an accurate model for system simulations would be useful. Such a model would also make it possible to find out which ADC errors limit the performance in a certain application and to do design trade-offs for various systems. A MATLAB-based time-domain ADC model aimed to work together with frequency domain RF simulators is presented.

  • 183.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Jakonis, Darius
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Design of RF-sampling receiver front-end.2004In: MIXDES 2004,2004, Lodz, Poland: Technical University of Lodz , 2004, p. 538-Conference paper (Refereed)
  • 184.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Jakonis, Darius
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A jitter measurement technique for high-speed sampling systems.2003In: IWADC conference,2003, 2003, p. 25-Conference paper (Refereed)
  • 185.
    Folkesson, Kalle
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An Accurate ADC Model in Radar System SimulationManuscript (preprint) (Other academic)
    Abstract [en]

    To show the usefulness of performing system simulations with an accurate ADC model, some simulations of a radar receiver are presented. The accurate model gives very different results than simple characterization with SNR and SFDR. System performance varies quite much for ADCs with the same specified performance in terms of SNR or SFDR depending on which error mechanism is active in the ADC. With this detailed knowledge of how the ADC affects system performance, the ADC requirement margin can be reduced thus saving cost and power consumption.

  • 186.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An accurate ADC model in radar system simulation.2003In: Swedish system-on-chip conference 2003.,2003, Lund: Lunds universitet , 2003Conference paper (Other academic)
  • 187.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Low-jitter clock paths2001In: Swedish National Symposium on GigaHerz Electronics.,2001, 2001Conference paper (Other academic)
  • 188.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Robust multi-phase clock generation with reduced jitter.2004In: SOC Conference,2004, Piscataway: IEEE, Inc. , 2004, p. 167-Conference paper (Refereed)
  • 189.
    Folkesson, Kalle
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    Microelectronics Research Center, Ericsson Microelectronics AB, Linköping, Sweden.
    Modeling of dynamic errors in algorithmic A/D converters2001In: The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001., Piscataway: IEEE , 2001, p. 455-458Conference paper (Refereed)
    Abstract [en]

    In communication applications, the requirements on A/D converters are high and increasing. To be able to design high-perfomance converters, it is important to understand the speed limitations. In this work, performance decrease caused by dynamic errors related to settling time of the switched circuits at high sampling frequencies is investigated

  • 190.
    Folkesson, Kalle
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Eklund, Jan-Erik
    Microelectronics Research Center, Ericsson Microelectronics AB, Linköpings, Sweden.
    Relevance of using single-tone tests to characterize ADCs for ADSL modems2002In: Proceedings of the 20th Norchip Conference, 2002, Copenhagen: TechnoData A/S , 2002, p. 214-219Conference paper (Refereed)
    Abstract [en]

    The ADC in ADSL modems is chosen to meet a requirement of an effective number of bits. To find the effective number of bits of an ADC, a single-tone test is used. Since an ADSL application is very different from the single-tone, it is not certain that this is suitable method. A detailed ADC model has been included in a MATLAB model of an ADSL link and simulations have been made to investigate the relevance of single-tone characterization of ADCs for ADSL applications.

  • 191.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Knuthammar, Björn
    Wavebreaker AB, Norrköping.
    Dreyfert, Andreas
    Wavebreaker AB, Norrköping.
    A High-Level Dynamic-Error Model of a Pipelined Analog-to-Digital Converter.2005In: ISCAS,2005, Galena, Il, USA: Gerard Enterprises, LLC , 2005, p. 5625-Conference paper (Refereed)
  • 192.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Equalization techniques for multi-Gb/s multi-drop buses2007Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The development of electronics is continuously expanding the possibilities of computational power and system complexity. The progress has in the past and in the foreseeable future primarily been achieved by the development of integrated circuit technologies. Though the trend is to integrate more and more functionality on a single chip (usually referred to as the system-on-chip concept). technology. manufacturing. system integration. and enterprise business model considerations prevent the system-on-chip concept to prevail in all electronic systems. Therefore. the continuous progresses in integrated circuit data handling capabilities impose faster inter chip communication.

    Though the improvements in materials and devices have to some extent fulfilled these increased communication speed requirements, the pace has been slower than the development of the integrated circuits. For many applications, this has made the communication channels between integrated circuits a limiting factor.

    To tackle these problems, electronic systems tend to utilize more point to point high-speed high quality links for chip-to-chip communication. This approach only partially solves the problem and it can for various reasons not be used for a ll systems. One type of system where high-speed narrow links have been used. but where the dominating bus structure s till is a wide multi-drop structure. is the memory interface of a standard computer. Improvements in the electrical properties of this type of bus have so far been enough to keep up with the increased demands for higher data rates, but it will not be able to do so in the future. This thesis presents work exploiting the possibilities of using equalizing techniques to drastically improve the data handling speed of multi-drop memory buses. The approach has been to accept the speed limiting mechanisms of the multi-drop bus and to exploit the fast deve lopment of integrated circuit's on-chip computational power to enable higher data rates.

    The thesis analyses the speed limiting factors on a chip-to-chip multi-drop channel. Different equalization techniques (including blind adaptive techniques) are presented and compared from a multi-drop bus point of view. A new equalizer implementation structure is presented and results from test chip measureme nts are included. Different computational abilities for the memory chip and the memory host chip make us suggest the use of asymmetric equalization relying on the reciprocal properties of the channel. Finally. issues related to evaluation of high -speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.

    List of papers
    1. Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study
    Open this publication in new window or tab >>Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study
    2004 (English)In: IEEE International SOC Conference, 2004. Proceedings., Piscataway: IEEE, Inc. , 2004, p. 147-148Conference paper, Published paper (Refereed)
    Abstract [en]

    A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

    Place, publisher, year, edition, pages
    Piscataway: IEEE, Inc., 2004
    Keywords
    integrated circuit, communication, bus, equalizer
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-22540 (URN)10.1109/SOCC.2004.1362384 (DOI)1801 (Local ID)0-7803-8445-8 (ISBN)1801 (Archive number)1801 (OAI)
    Conference
    IEEE International SOC Conference, 2004 (SOCC). Santa Clara California, September 12-15 2004.
    Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-12-17
    2. Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses
    Open this publication in new window or tab >>Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses
    2006 (English)In: International Symposium on VLSI Design, Automation and Test, 2006, Piscataway, USA: IEEE Conference Publications Management Group , 2006, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a mixed signal decision feedback equalizer (DFE) efficiently implementing sign-sign least-mean-square (SS-LMS) coefficient updating, offset estimation and compensation. The equalizer is designed for multi-drop buses and has 16 six bit fully programmable filter coefficients. The equalizer filter is implemented with a novel carry-save-DAC architecture eliminating the carry propagation limiting factor. Measurement results from a test chip are presented showing no transmission errors and good clock skew robustness when receiving data at 700 Mb/s over a heavily polluted channel. The test chip also includes bit error rate (BER) measurement circuits and equalized eye-chart extraction

    Place, publisher, year, edition, pages
    Piscataway, USA: IEEE Conference Publications Management Group, 2006
    Keywords
    adaptive equalizer, multi-drop bus, decision feedback equalizer, carry-save
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-34129 (URN)10.1109/VDAT.2006.258165 (DOI)20873 (Local ID)1-4244-0180-1 (ISBN)1-4244-0179-8 (ISBN)20873 (Archive number)20873 (OAI)
    Conference
    IEEE International Symposium on VLSI Design, Automation and Test 2006 (VLSI-DAT). Hsinchu, Taiwan. April 26-28 2006.
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-17
    3. High-speed, low latency, digital, one bit input FIR-filter implementation
    Open this publication in new window or tab >>High-speed, low latency, digital, one bit input FIR-filter implementation
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    This paper present a low latency, one bit input, high-speed FIR-filter implementation designed for high-speed mixed signal decision feedback equalizers. The filter structure features a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer implementation. The filter has been implemented in a standard 0.13μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency < 270 ps.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-102637 (URN)
    Available from: 2013-12-17 Created: 2013-12-17 Last updated: 2013-12-17
    4. Single-ended adaptive equalization of bidirectional data communication utilizing reciprocity
    Open this publication in new window or tab >>Single-ended adaptive equalization of bidirectional data communication utilizing reciprocity
    2007 (English)In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper present the idea of single-ended adaptive equalization. The idea enables mitigation of inter-symbol interference in communication systems where it is desirable to utilize signal processing resources on only one side of a communication channel. Utilizing the reciprocity principle we show that this idea is suitable for both point-to-point and point-to-multi-point links. Possible implementation principles for multi-Gb/s communication are described and different implementation considerations are presented.

    Place, publisher, year, edition, pages
    Göteborg: CTH, 2007
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-38039 (URN)41366 (Local ID)41366 (Archive number)41366 (OAI)
    Conference
    Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2016-12-08
  • 193. Order onlineBuy this publication >>
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Improvement Potential and Equalization Circuit Solutions for Multi-drop DRAM Memory Buses2008Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Digital computers have changed human society in a profound way over the last 50 years. Key properties that contribute to the success of the computer are flexible programmability and fast access to large amounts of data and instructions. Effective access to algorithms and data is a fundamental property that limits the capabilities of computer systems. For PC computers, the main memory consists of dynamic random access memory (DRAM). Communication between memory and processor has traditionally been performed over a multi-drop bus.

    Signal frequencies on these buses have gradually increased in order to keep up with the progress in integrated circuit data processing capabilities. Increased signal frequencies have exposed the inherent signal degradation effects of a multidrop bus structure. As of today, the main approach to tackle these effects has been to reduce the number of endpoints of the bus structure. Though improvements in DRAM memory technology have increased the available memory size at each endpoint, the increase has not been able to fully fulfill the demand for larger system memory capacity. Different bus structural changes have been used to overcome this problem. All are different compromises between access latency, data transmission capacity, memory capacity, and implementation costs.

    In this thesis we focus on using the signal processing capabilities of a modern integrated circuit technology as an alternative to bus structural changes. This has the potential to give low latency, high memory capacity, and relatively high data transmission capacity at an additional cost limited to integrated circuit blocks. We first use information theory to estimate the unexplored potential of existing multi-drop bus structures. Hereby showing that reduction of the number of endpoints for multi-drop buses, is by no means based on the fundamental limit of the data transmission capacity of the bus structure. Two test-chips have been designed and fabricated to experimentally demonstrate the feasibility of several Gb/s data-rates over multidrop buses, with limited cost overhead and no latency penalty. The test-chips implement decision feedback equalization, adopted for high speed multi-drop use. The equalizers feature digital filter implementations which, in combination with high speed DACs, enable the use of long digital filters for high speed decision feedback equalization. Blind adaptation has also been implemented to demonstrate extraction of channel characteristics during data transmission. The use of single sided equalization has been proposed in order to limit the need for equalization implementation to the host side of a DRAM memory bus. Furthermore, we propose to utilize the reciprocal properties of the communication channel to ensure that single sided equalization can be performed without any channel characterization hardware on the memory chips. Finally, issues related to evaluation of high-speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.

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  • 194.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Project Guide, TSEK 01 VLSI Chip Design Project and TSEK 10 Evaluation of an IC.2005Other (Other (popular science, discussion, etc.))
  • 195.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    2.6 Gb/s Over a Four-Drop Bus Using an Adaptive 12-Tap DFE2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, p. 470-473Conference paper (Refereed)
    Abstract [en]

    For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.  

  • 196.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.2007In: 2007 International Symposium on System-on-Chip.,2007, Tampere: Tampere University of Technology , 2007, p. 125-Conference paper (Refereed)
  • 197.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Blind adaptive mixed-signal DFE for a four drop memory bus.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 198.
    Fredriksson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses2006In: International Symposium on VLSI Design, Automation and Test, 2006, Piscataway, USA: IEEE Conference Publications Management Group , 2006, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents a mixed signal decision feedback equalizer (DFE) efficiently implementing sign-sign least-mean-square (SS-LMS) coefficient updating, offset estimation and compensation. The equalizer is designed for multi-drop buses and has 16 six bit fully programmable filter coefficients. The equalizer filter is implemented with a novel carry-save-DAC architecture eliminating the carry propagation limiting factor. Measurement results from a test chip are presented showing no transmission errors and good clock skew robustness when receiving data at 700 Mb/s over a heavily polluted channel. The test chip also includes bit error rate (BER) measurement circuits and equalized eye-chart extraction

  • 199.
    Fredriksson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-speed, low latency, digital, one bit input FIR-filter implementationManuscript (preprint) (Other academic)
    Abstract [en]

    This paper present a low latency, one bit input, high-speed FIR-filter implementation designed for high-speed mixed signal decision feedback equalizers. The filter structure features a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer implementation. The filter has been implemented in a standard 0.13μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency < 270 ps.

  • 200.
    Fredriksson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Improvement Potential and Equalization Example for Multidrop DRAM Memory Buses2009In: IEEE TRANSACTIONS ON ADVANCED PACKAGING, ISSN 1521-3323, Vol. 32, no 3, p. 675-682Article in journal (Refereed)
    Abstract [en]

    For PC DRAM memory buses, the number of slots per channel have been decreased as signal frequencies increase. This limits the data capacity per channel. In this paper, we show that the slot reduction is not due to fundamental limits of the channel structure but due to signaling schemes. An equalization scheme is presented which enables higher bit-rates with minimum modification of bus structure and memory circuits. The circuitry added to the host side of the bus has reasonable complexity and features very low latency. Measurements of memory-to-host transmissions over a four-drop-bus at 2.6 Gb/s using a 0.13 mu m CMOS test-circuit is presented.

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