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  • 151.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    General Purpose Computing on Low-Power Embedded GPUs: Has It Come of Age?2013In: 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2013), Samos, Greece, July 15-18, 2013., IEEE Press, 2013Conference paper (Refereed)
    Abstract [en]

    In this paper we evaluate the promise held by low power GPUs for non-graphic workloads that arise in embedded systems. Towards this, we map and implement 5 benchmarks, that find utility in very different application domains, to an embedded GPU. Our results show that apart from accelerated performance, embedded GPUs are promising also because of their energy efficiency which is an important design goal for battery-driven mobile devices. We show that adopting the same optimization strategies as those used for programming high-end GPUs might lead to worse performance on embedded GPUs. This is due to restricted features of embedded GPUs, such as, limited or no user-defined memory, small instruction-set, limited number of registers, among others. We propose techniques to overcome such challenges, e.g., by distributing the workload between GPUs and multi-core CPUs, similar to the spirit of heterogeneous computation.

  • 152.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Horga, Adrian
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Saving Energy without Defying Deadlines on Mobile GPU-based Heterogeneous Systems2014In: 2014 International Conference on Hardware/Software Codesign and System Synthesis, Association for Computing Machinery (ACM), 2014Conference paper (Refereed)
    Abstract [en]

    With the advent of low-power programmable compute cores based on GPUs, GPU-equipped heterogeneous platforms are becoming common in a wide spectrum of industries including safety-critical domains like the automotive industry. While the suitability of GPUs for throughput oriented applications is well-accepted, their applicability for real-time applications remains an open issue. Moreover, in mobile/embedded systems, energy-efficient computing is a major concern and yet, there has been no systematic study on the energy savings that GPUs may potentially provide. In this paper, we propose an approach to utilize both the GPU and the CPU in a heterogeneous fashion to meet the deadlines of a real-time application while ensuring that we maximize the energy savings. We note that GPUs are inherently built to maximize the throughput and this poses a major challenge when deadlines must be satisfied. The problem becomes more acute when we consider the fact that GPUs are more energy efficient than CPUs and thus, a naive approach that is based on maximizing GPU utilization might easily lead to infeasible solutions from a deadline perspective.

  • 153.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Perception-aware power management for mobile games via dynamic resolution scaling2015In: 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), IEEE , 2015, p. 613-620Conference paper (Refereed)
    Abstract [en]

    Modern mobile devices provide ultra-high resolutions in their display panels. This imposes ever increasing workload on the GPU leading to high power consumption and shortened battery life. In this paper, we first show that resolution scaling leads to significant power savings. Second, we propose a perception-aware adaptive scheme that sets the resolution during game play. We exploit the fact that game players are often willing to trade quality for longer battery life. Our scheme uses decision theory, where the predicted user perception is combined with a novel asymmetric loss function that encodes users' alterations in their willingness to save power.

  • 154.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Chattopadhyay, Sudipta
    Singapore Univ Technol and Design, Singapore.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications2019In: 2019 DESIGN, AUTOMATION and TEST IN EUROPE CONFERENCE and EXHIBITION (DATE), IEEE , 2019, p. 570-575Conference paper (Refereed)
    Abstract [en]

    We present a software approach to address the data latency issue for certain GPU applications. Each application is modeled as a kernel graph, where the nodes represent individual GPU kernels and the edges capture data dependencies. Our technique exploits the GPU L2 cache to accelerate parameter passing between the kernels. The key idea is that, instead of having each kernel process the entire input in one invocation, we subdivide the input into fragments (which fit in the cache) and, ideally, process each fragment in one continuous sequence of kernel invocations. Our proposed technique is oblivious to kernel functionalities and requires minimal source code modification. We demonstrate our technique on a full-fledged image processing application and improve the performance on average by 30% over various settings.

  • 155.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Chattopadhyay, Sudipta
    Singapore University of Technology and Design (SUTD), Information Systems Technology and Design (ISTD).
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications2019Conference paper (Refereed)
    Abstract [en]

    We present a software approach to address the data latency issue for certain GPU applications. Each application is modeled as a kernel graph, where the nodes represent individual GPU kernels and the edges capture data dependencies. Our technique exploits the GPU L2 cache to accelerate parameter passing between the kernels. The key idea is that, instead of having each kernel process the entire input in one invocation, we subdivide the input into fragments (which fit in the cache) and, ideally, process each fragment in one continuous sequence of kernel invocations. Our proposed technique is oblivious to kernel functionalities and requires minimal source code modification. We demonstrate our technique on a full-fledged image processing application and improve the performance on average by 30% over various settings.

  • 156.
    Mahfouzi, Rouhollah
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Aminifar, Amir
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. École Polytechnique Fédérale de Lausanne (EPFL), Switzerland.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Arts and Sciences.
    Intrusion-Damage Assessment and Mitigation in Cyber-Physical Systems for Control Applications2016In: RTNS '16 Proceedings of the 24th International Conference on Real-Time Networks and Systems, New York: ACM Press, 2016, p. 141-150Conference paper (Refereed)
    Abstract [en]

    With cyber-physical systems opening to the outside world, security can no longer be considered a secondary issue. One of the key aspects in security of cyber-phyiscal systems is to deal with intrusions. In this paper, we highlight the several unique properties of control applications in cyber-physical systems. Using these unique properties, we propose a systematic intrusion-damage assessment and mitigation mechanism for the class of observable and controllable attacks.

    On the one hand, in cyber-physical systems, the plants follow certain laws of physics and this can be utilized to address the intrusion-damage assessment problem. That is, the states of the controlled plant should follow those expected according to the physics of the system and any major discrepancy is potentially an indication of intrusion. Here, we use a machine learning algorithm to capture the normal behavior of the system according to its dynamics. On the other hand, the control performance strongly depends on the amount of allocated resources and this can be used to address the intrusion-damage mitigation problem. That is, the intrusion-damage mitigation is based on the idea of allocating more resources to the control application under attack. This is done using a feedback-based approach including a convex optimization.

  • 157.
    Mahfouzi, Rouhollah
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Aminifar, Amir
    Embedded Systems Laboratory, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland..
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. General Motors, USA.
    Payer, Mathias
    HexHive Systems Security Group Swiss Federal Institute of Technology (EPFL) Lausanne, Switzerland.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Security-aware Routing and Scheduling for Control Applications on Ethernet TSN Networks2019In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 25, no 1Article in journal (Refereed)
    Abstract [en]

    Today, it is common knowledge in the cyber-physical systems domain that the tight interaction between the cyber and physical elements provides the possibility of substantially improving the performance of these systems that is otherwise impossible. On the downside, however, this tight interaction with cyber elements makes it easier for an adversary to compromise the safety of the system. This becomes particularly important, since such systems typically are composed of several critical physical components, e.g., adaptive cruise control or engine control that allow deep intervention in the driving of a vehicle. As a result, it is important to ensure not only the reliability of such systems, e.g., in terms of schedulability and stability of control plants, but also resilience to adversarial attacks.

    In this article, we propose a security-aware methodology for routing and scheduling for control applications in Ethernet networks. The goal is to maximize the resilience of control applications within these networked control systems to malicious interference while guaranteeing the stability of all control plants, despite the stringent resource constraints in such cyber-physical systems. Our experimental evaluations demonstrate that careful optimization of available resources can significantly improve the resilience of these networked control systems to attacks.

  • 158.
    Mahfouzi, Rouhollah
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Aminifar, Amir
    Ecole Polytech Fed Lausanne, Switzerland.
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. Gen Motors RandD, MI USA.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Stability-Aware Integrated Routing and Scheduling for Control Applications in Ethernet Networks2018In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION and TEST IN EUROPE CONFERENCE and EXHIBITION (DATE), IEEE , 2018, p. 682-687Conference paper (Refereed)
    Abstract [en]

    Real-time communication over Ethernet is becoming important in various application areas of cyber-physical systems such as industrial automation and control, avionics, and automotive networking. Since such applications are typically time critical, Ethernet technology has been enhanced to support time driven communication through the IEEE 802.1 TSN standards. The performance and stability of control applications is strongly impacted by the timing of the network communication. Thus, in order to guarantee stability requirements, when synthesizing the communication schedule and routing, it is needed to consider the degree to which control applications can tolerate message delays and jitters. In this paper we jointly solve the message scheduling and routing problem for networked cyber-physical systems based on the time-triggered Ethernet TSN standards. Moreover, we consider this communication synthesis problem in the context. of control applications and guarantee their worst-case stability, taking explicitly into consideration the impact of communication delay and jitter on control quality. Considering the inherent complexity of the network communication synthesis problem, we also propose new heuristics to improve synthesis efficiency without any major loss of quality. Experiments demonstrate the effectiveness of the proposed solutions.

  • 159.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs2006In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, p. 718-Conference paper (Refereed)
    Abstract [en]

    This paper addresses communication optimisation for applications implemented on networks-on-chip. The mapping of data packets to network links and the timing of the release of the packets are critical for avoiding destination contention. This reduces the demand for communication buffers with obvious advantages in chip area and energy savings. We propose a buffer need analysis approach and a strategy for communication synthesis and packet release timing with minimum communication buffer demand that guarantees worst-case response times.

  • 160.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fault and EnergyAware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC2005In: 42nd Design Automation Conference,2005, Anaheim, CA, USA: IEEE Computer Society Press , 2005, p. 266-Conference paper (Refereed)
    Abstract [en]

    As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on bo th message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmiss ion of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statica lly assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. Firstly, we reduce the total amount of transmitted messages, and, secondly, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arriva l probability and guaranteed worst case application response time.

  • 161.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fault-aware communication mapping for NoCs with guaranteed latency2007In: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 35, no 2, p. 125-156Article in journal (Refereed)
    Abstract [en]

    As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time. © Springer Science+Business Media, LLC 2007.

  • 162.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time2001In: 13th Euromicro Conference on Real-Time Systems,2001, Delft, The Netherlands: IEEE Computer Society Press , 2001, p. 19-Conference paper (Refereed)
    Abstract [en]

    This paper presents an efficient way to analyse the performance of task sets, where the task execution time is specified as a generalized continuous probability distribution. We consider fixed task sets of periodic, possibly dependent, non-pre-emptable tasks with deadlines less than or equal to the period. Our method is not restricted to any specific scheduling policy and supports policies with both dynamic and static priorities. An algorithm to construct the underlying stochastic process in a memory and time efficient way is presented. We discuss the impact of various parameters on complexity, in terms of analysis time and required memory. Experimental results show the efficiency of the proposed approach.

  • 163.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints2004In: 10th IEEE Real-Time and Embedded Technology and Applications Symposium,2004, Toronto, Canada: IEEE Computer Society Press , 2004, p. 562-Conference paper (Refereed)
    Abstract [en]

    Both analysis and design optimization of real-time systems has predominantly concentrated on considering hard real-time constraints. For a large class of applications, however, this is both unrealistic and leads to unnecessarily expensive implementations. This paper addresses the problem of task priority assignment and task mapping in the context of multiprocessor applications with stochastic execution times and in the presence of constraints on the percentage of missed deadlines. We propose a design space exploration strategy based on Tabu Search together with a fast method for system performance analysis. Experiments emphasize the efficiency of the proposed analysis method and optimization heuristic in generating high quality implementations of soft real-time systems with stochastic task execution times and constraints on deadline miss ratios

  • 164.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Real-Time Applications with Stochastic Task Execution Times2007 (ed. 1)Book (Other academic)
    Abstract [sv]

    This book presents three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each best fits a different context: an exact one efficiently applicable to monoprocessor systems; an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed; and one less accurate but sufficiently fast in order to be placed inside optimization loops

  • 165.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis of Applications with Stochastic Task Execution Times2004In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 3, no 4, p. 706-735Article in journal (Refereed)
    Abstract [en]

    In the past decade, the limitations of models considering fixed (worst-case) task execution times have been acknowledged for large application classes within soft real-time systems. A more realistic model considers the tasks having varying execution times with given probability distributions. Considering such a model with specified task execution time probability distribution functions, an important performance indicator of the system is the expected deadline miss ratio of the tasks and of the task graphs. This article presents an approach for obtaining this indicator in an analytic way. Our goal is to keep the analysis cost low, in terms of required analysis time and memory, while considering as general classes of target application models as possible. The following main assumptions have been made on the applications that are modeled as sets of task graphs: the tasks are periodic, the task execution times have given generalized probability distribution functions, the task execution deadlines are given and arbitrary, the scheduling policy can belong to practically any class of non-preemptive scheduling policies, and a designer supplied maximum number of concurrent instantiations of the same task graph is tolerated in the system. Experiments show the efficiency of the proposed technique for monoprocessor systems.

  • 166.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis of Multiprocessor Real-Time Applications with Stochastic Task Execution Times2002In: Intl Conference on Computer Aided Design, ICCAD 02,2002, San Jose, California, USA: IEEE Computer Society Press , 2002, p. 699-Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to the analysis of task sets implemented on multiprocessor systems, when the task execution times are specified as generalized probability distributions. Because of the extreme complexity of the problem, an exact solution is practically impossible to be obtained even for toy examples. Therefore, our methodology is based on approximating the generalized probability distributions of execution times by Coxian distributions of exponentials. Thus, we transform the generalized semi-Markov process, corresponding to the initial problem, into a continuous Markov chain (CTMC) which, however, is extremely large and, hence, most often is impossible to be stored in memory. We have elaborated a solution which allows to generate and analyze the CTMC in an efficient way, such that only a small part has to be stored at a given time. Several experiments investigate the impact of various parameters on complexity, in terms of time and memory, as well as the trade-offs regarding the accuracy of generated results.

  • 167.
    Manolache, Sorin
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability Analysis of Real-Time Systems with Stochastic Task Execution Times2006In: ARTES: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, p. 123-159Chapter in book (Other academic)
    Abstract [en]

    For soft real-time applications, a system is considered to function correctly even if some timeliness requirements are occasionally broken, since this leads only to a tolerable reduction of the service quality. Analysis of such a system should be focused on the degree to which the system meets its timeliness requirements rather than on a binary answer indicating whether the whole system is schedulable or not. In many soft real-time applications, the task execution times vary also widely since they are dependent on many parameters. In such a context, analysis techniques based on worst case execution time assumption will lead to very pessimistic results, and many techniques have been developed to consider a more realistic model that assumes tasks to have varying execution times with given probability distributions. The chapter presents one of such techniques. It describes an analytic method to produce the expected deadline miss ratio of the tasks and the task graphs that represent a software real-time application. The reported method improves the currently existing ones by providing exact solutions for larger and less restricted task sets. In particular, it allows continuous task execution time probability distributions, and supports different scheduling policy. Furthermore, task dependencies and arbitrary deadlines are supported by the proposed technique.

  • 168.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints2008In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 7, no 2Article in journal (Refereed)
    Abstract [en]

    Both analysis and design optimisation of real-time systems has predominantly concentrated on considering hard real-time constraints. For a large class of applications, however, this is both unrealistic and leads to unnecessarily expensive implementations. This paper addresses the problem of task priority assignment and task mapping in the context of multiprocessor applications with stochastic execution times and in the presence of constraints on the percentage of missed deadlines. We propose a design space exploration strategy together with a fast method for system performance analysis. Experiments emphasize the efficiency of the proposed analysis method and optimisation heuristic in generating high-quality implementations of soft real-time systems with stochastic task execution times and constraints on deadline miss ratios.

  • 169.
    Marculescu, R.
    et al.
    Dept. of Elec./Computer Eng., Carnegie Mellon Univ., 5000 Forbes Ave., Pittburgh, PA 15213-3890, United States.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Designing real-time embedded multimedia systems2004In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 21, no 5, p. 354-356Other (Other academic)
    Abstract [en]

    [No abstract available]

  • 170. Marculescu, R
    et al.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Guest editors' introduction: Designing real-time embedded multimedia systems2004In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 21, no 5, p. 354-356Other (Other academic)
  • 171.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Heuristic for Wiring-Aware Built-In Self-Test Synthesis2004In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004, Rennes, France: IEEE Computer Society Press , 2004, p. 408-Conference paper (Refereed)
    Abstract [en]

    This paper addresses the problem of BIST synthesis that takes into account wiring area. A technique for minimizing BIST hardware overhead is presented. The technique uses results of symbolic testability analysis to guarantee testability of all modules in the design. New behavioral-level BIST enhancement metrics are used to guide synthesis in such a way that the number of testability enhancements is minimized. The technique is not only fast but also adds low BIST overhead.

  • 172.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2003Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system tomake it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. Keywords: BIST insertion, test synthesis, wiring area, and Simulated Annealing.

  • 173.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2004In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004, p. 413-415Conference paper (Refereed)
    Abstract [en]

    This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It considers both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

  • 174.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2005In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 20, no 2, p. 216-223Article in journal (Refereed)
    Abstract [en]

    This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

  • 175.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints2001Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints. A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.

  • 176.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    BIST Synthesis: An Approach to Resources Optimization under Test Time Constraints2002In: 5th Design and Diagnostic of Electronic Computer Systems DDECS2002,2002, 2002, p. 346-351Conference paper (Refereed)
    Abstract [en]

    An Approach at optimizing the BIST resource usage under test-time constraints is introduced. The test problem identification and BIST enhancement strategy during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while MISRs sharing conflicts as well as controllability and observability constraints are considered.

  • 177.
    Niknafs, Mina
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ukhov, Ivan
    Gears Leo AB, Sweden.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Runtime Resource Management with Workload Prediction2019In: PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), ASSOC COMPUTING MACHINERY , 2019Conference paper (Refereed)
    Abstract [en]

    Modern embedded platforms need sophisticated resource managers in order to utilize the heterogeneous computational resources efficiently. Moreover, such platforms are exposed to fluctuating workloads unpredictable at design time. In such a context, predicting the incoming workload might improve the efficiency of resource management. But is this true? And, if yes, how significant is this improvement? How accurate does the prediction need to be in order to improve decisions instead of doing harm? By proposing a prediction-based resource manager aimed at minimizing energy consumption while meeting task deadlines and by running extensive experiments, we try to answer the above questions.

  • 178.
    Niknafs, Mina
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ukhov, Ivan
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Two-Phase Interarrival Time Prediction for Runtime Resource Management2017In: 2017 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), IEEE , 2017, p. 524-528Conference paper (Refereed)
    Abstract [en]

    Platforms that are based on heterogeneous architectures require an intelligent resource manager. An intelligent resource manager should be able to accurately predict the future workload of the system at hand and take it into consideration. In this paper, we show that there exist patterns in the interarrival times of resource requests, and that these patterns can be used for modeling and prediction of the future arrivals. To this end, we develop a two-phase machine-learning-based framework and apply it to real data. First, in the offline phase of our framework, the interarrival times are clustered based on a number of extracted features, and then an adequate modeling and prediction method is selected for each detected cluster. It is shown that, due to the intricate and varied nature of interarrival times, a universal modeling and prediction method does not provide optimal results, and a customized method should be applied to each of the detected clusters. Second, in the runtime phase of our framework, the results provided from the offline phase are used to perform computationally cheap prediction. The experimental results show that our approach has a prediction error below 12% and provides an error reduction of more than 17% in comparison with a straightforward method.

  • 179.
    Niknafs, Mina
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ukhov, Ivan
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Workload Prediction for Runtime Resource Management2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    An intelligent resource manager is an essential part of platforms based on heterogeneous architectures. The resource manager should be able to accurately predict the future workload of the system at hand and take it into consideration for making decisions. In this paper, we study a large computer cluster and show that there exist patterns in the sequence of applications that each user runs over time, and that these patterns can be used for modeling and prediction of the applications that will be requested in the future. To this end, we develop a predictive technique based on the n-gram model. It is shown that, due to the varied nature of application sequences of different users, a universal model does not provide optimal results, and a customized model should be constructed for each user. The experimental results show that the straightforward methods have a prediction accuracy below 16% when assessed on a real-life data set. Our technique provides an accuracy improvement of more than 51% in comparison with the straightforward method.

  • 180.
    Niknafs, Mina
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Ukhov, Ivan
    Gears of Leo AB, Sweden.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Runtime Resource Management with Workload Prediction2019Conference paper (Refereed)
    Abstract [en]

    Modern embedded platforms need sophisticated resource managers in order to utilize the heterogeneous computational resources efficiently. Moreover, such platforms are exposed to fluctuating workloads unpredictable at design time. In such a context, predicting the incoming workload might improve the efficiency of resource management. But is this true? And, if yes, how significant is this improvement? How accurate does the prediction need to be in order to improve decisions instead of doing harm? By proposing a prediction-based resource manager aimed at minimizing energy consumption while meeting task deadlines and by running extensive experiments, we try to answer the above questions.

  • 181.
    Nilsson, Peter
    et al.
    Department of Electro Science Lund University.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Tenhunnen, Hannu
    Department of Electronics Royal Institute of Technology.
    SOCWARE: A New Swedish Design Cluster For System-On-Chip2001In: International Conference on Microelectronic Systems Education,2001, Las Vegas, USA: IEEE Computer Society Press , 2001, p. 44-Conference paper (Refereed)
    Abstract [en]

    Socware is the name for a new design cluster in Sweden, which intends to unify university, research institutes, and industry towards a common goal, namely System-on-Chip. In this paper, one of the programs within the cluster, the Socware Research & Education Program, is presented. The program aims to organize a new education curriculum for System-on-Chip design. The education is directed to undergraduate and graduate students as well as Master's in industry. Totally, the Socware Design Cluster has 50 Meuro of public funds, where 15 Meuro are reserved for the Socware Research & Education program.

  • 182.
    Nunna, Swaroop
    et al.
    TU Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakraborty, Samarjit
    TU Munich, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Exploiting GPU On-Chip Shared Memory for Accelerating Schedulability Analysis2010In: International Symposium on Electronic System Design (ISED10), Bhubaneswar, India, December 2010., 2010Conference paper (Refereed)
    Abstract [en]

    Embedded electronic devices like mobile phones and automotive control units must perform under strict timing constraints. As such, schedulability analysis constitutes an important phase of the design cycle of these devices. Unfortunately, schedulability analysis for most realistic task models turn out to be computationally intractable (NP-hard). Naturally, in the recent past, different techniques have been proposed to accelerate schedulability analysis algorithms, including parallel computing on Graphics Processing Units (GPUs). However, applying traditional GPU programming methods in this context restricts the effective usage of on-chip memory and in turn imposes limitations on fully exploiting the inherent parallel processing capabilities of GPUs. In this paper, we explore the possibility of accelerating schedulability analysis algorithms on GPUs while exploiting the usage of on-chip memory. Experimental results demonstrate upto 9× speedup of our GPU-based algorithms over the implementations on sequential CPUs.

  • 183.
    Peng, Zebo
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    He, Zhiyuan
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Challenges and solutions for thermal-aware SOC testing2007In: Informacije midem, ISSN 0352-9045, Vol. 37, no 4, p. 220-227Article in journal (Refereed)
    Abstract [en]

    High temperature has negative impact on the performance, reliability and lifespan of a system on chip. During testing, the chip can be overheated due to a substantial increase of switching activities and concurrent tests in order to reduce test application time. This paper discusses several issues related to the thermal problem during SoC testing. It will then present a thermal-aware SoC test scheduling technique to generate the shortest test schedule such that the temperature constraints of individual cores and the constraint on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, we partition test sets into shorter test sub-sequences and add cooling periods in between. Further more, we interleave the test sub-sequences from different test sets in such a manner that the test-bus bandwidth reserved for one core is utilized during its cooling period for the test transportation and application of the other cores. We have developed a heuristic to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods. Experimental results have shown the efficiency of the proposed heuristic.

  • 184.
    Peng, Zebo
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Emerging strategies for resource-constrained testing of system chips2005Other (Other academic)
  • 185.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and optimisation of heterogeneous real-time embedded systems2005In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, no 2, p. 130-147Article in journal (Refereed)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimisation techniques. Analysis and optimisation techniques for heterogeneous real-time embedded systems are presented in the paper. The authors address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. They present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimisation problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimisation heuristics for frame packing aimed at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 186.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and optimisation of heterogeneous real-time embedded systems2006In: System On Chip: Next Generation Electronics / [ed] Al-Hashimi, Bashir, Stevenage, Herts, United Kingdom: The Institution of Engineering and Technology , 2006, p. 75-120Chapter in book (Other academic)
    Abstract [en]

    We have presented an analysis for multi-cluster systems and outlined several characteristic design problems, related to the partitioning and mapping of functionality and the optimisation of the access to the communication infrastructure. An approach to schedulability-driven frame packing for the synthesis of multi-cluster systems was presented as an example of solving such a design optimisation problem. We have developed two optimisation heuristics for frame configuration synthesis which are able to determine frame configurations that lead to a schedulable system. We have shown that by considering the frame packing problem, we are able to synthesise schedulable hard real-time systems and to potentially reduce the overall cost of the architecture.

  • 187.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and Optimization of Heterogeneous Real-Time Embedded Systems2005In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, no 2, p. 130-147Article in journal (Refereed)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimization techniques. In this paper, we present analysis and optimization techniques for heterogeneous real-time embedded systems. We address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. We present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimization problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimization heuristics for frame packing aiming at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 188.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and Synthesis of Distributed Real-Time Embedded Systems2004Book (Other academic)
    Abstract [en]

    Embedded computer systems are now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computers. An important class of embedded computer systems is that of hard real-time systems, which have to fulfill strict timing requirements. As real-time systems become more complex, they are often implemented using distributed heterogeneous architectures. Analysis and Synthesis of Distributed Real-Time Embedded Systems addresses the design of real-time applications implemented using distributed heterogeneous architectures. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Regarding this last aspect, time-driven and event-driven systems, as well as a combination of the two, are considered. Such systems are used in many application areas like automotive electronics, real-time multimedia, avionics, medical equipment, and factory systems. The proposed analysis and synthesis techniques derive optimized implementations that fulfill the imposed design constraints. An important part of the implementation processis the synthesis of the communication infrastructure, which has a significant impact on the overall system performance and cost. Analysis and Synthesis of Distributed Real-Time Embedded Systems considers the mapping and scheduling tasks within an incremental design process. To reduce the time-to-market of products, the design of real-time systems seldom starts from scratch. Typically, designers start from an already existing system, running certain applications, and the design problem is to implement new functionality on top of this system. Supporting such an incremental design process provides a high degree of flexibility, and can result in important reductions of design costs. Analysis and Synthesis of Distributed Real-Time Embedded Systems will be of interest to advanced undergraduates, graduate students, researchers and designers involved in the field of embedded systems.

  • 189.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications2006In: ARTES -: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, p. 49-101Chapter in book (Other academic)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimization techniques. In this paper, we present analysis and optimization techniques for heterogeneous real-time embedded systems. We address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. We present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briey highlight characteristic design optimization problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimization heuristics for frame packing aiming at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 190.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Distributed Embedded Real-Time Systems - Analysis and Exploration2005In: Embedded Systems Design: The ARTIST Roadmap for Research and Development / [ed] Bruno Bouyssounouse ; Joseph Sifakis, New York: Springer Verlag , 2005, p. 406-422Chapter in book (Other academic)
    Abstract [en]

    This extensive and increasing use of embedded systems and their integration in everyday products mark a significant evolution in information science and technology. Nowadays embedded systems design is subject to seamless integration with the physical and electronic environment while meeting requirements like reliability, availability, robustness, power consumption, cost, and deadlines. Thus, embedded systems design raises challenging problems for research, such as security, reliable and mobile services, large-scale heterogeneous distributed systems, adaptation, component-based development, and validation and tool-based certification.

    This book results from the ARTIST FP5 project funded by the European Commision. By integration 28 leading European research institutions with many top researchers in the area, this book assesses and strategically advances the state of the art in embedded systems. The coherently written monograph-like book is a valuable source of reference for researchers active in the field and serves well as an introduction to scientists and professionals interested in learning about embedded systems design.

  • 191.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems2002In: 8th International Conference on Real-Time Computing Systems and Applications RTCSA 2002,2002, 2002, p. 337-346Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to mapping and scheduling of distributed hard real-time systems, aiming at improving the flexibility of the design process. We consider an incremental design process that starts from an already existing system running a set of applications, with preemptive priority based scheduling at the process level, and time triggered static scheduling at the communication level. We are interested to implement new functionality so that the already running applications are disturbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problems are considered in the context of a realistic communication model based on a TDMA protocol. Extensive experiments as well as a real life example demonstrate the relevance of this problem and the efficiency of our solutions.

  • 192.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Performance Estimation for Embedded Systems with Data and Control Dependencies2000In: 8th International Workshop on HardwareSoftware Codesign CODES 2000,2000, San Diego, USA: IEEE Computer Society Press , 2000, p. 62-66Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to performance estimation for hard real-time systems. We consider architectures consisting of multiple processors. The scheduling policy is based on a preemptive strategy with static priorities. Our model of the system captures both data and control dependencies, and the analysis is able to reduce the pessimism of the estimation by using the knowledge about these dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

  • 193.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems2003In: IEE journal on computers and digital techniques / Institution of electrical engineers, ISSN 0140-1335, Vol. 150, no 5, p. 303-312Article in journal (Refereed)
    Abstract [en]

    We present an approach to schedulability analysis for the synthesis of multicluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

  • 194.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, p. 184-Conference paper (Refereed)
    Abstract [en]

    We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

  • 195.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis for Systems with Data and Control Dependencies2000In: 12th Euromicro Conference on Real-Time Systems,2000, Stockholm, Sweden: IEEE Computer Society Press , 2000, p. 201-208Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to schedulability analysis for hard real-time systems with control and data dependencies. We consider distributed architectures consisting of multiple programmable processors, and the scheduling policy is based on a static priority preemptive strategy. Our model of the system captures both data and control dependencies, and the schedulability approach is able to reduce the pessimism of the analysis by using the knowledge about control and data dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

  • 196.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems2006In: ARTES: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, p. 537-569Chapter in book (Other academic)
    Abstract [en]

    We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.

  • 197.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Communication Synthesis for Time-Triggered Embedded Systems2004In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 26, no 3, p. 297-325Article in journal (Refereed)
    Abstract [en]

    We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.

  • 198.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability-Driven Frame Packing for Multi-Cluster Distributed Embedded Systems2003In: LCTES '03 Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems, New York, NY, United States: Association for Computing Machinery (ACM), 2003, Vol. 38 issue 7, p. 113-122Conference paper (Other academic)
    Abstract [en]

    We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.

  • 199.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability-driven frame packing for multicluster distributed embedded systems2005In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 4, no 1, p. 112-140Article in journal (Refereed)
    Abstract [en]

    We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable, thus the end-to-end message communication constraints are satisfied. We have proposed a schedulability analysis for applications consisting of mixed event-triggered and timetriggered processes and messages, and a worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.

  • 200.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems2004In: 16th Euromicro Conference on Real-Time Systems,2004, Catania, Sicily: IEEE Computer Society Press , 2004, p. 91-Conference paper (Refereed)
    Abstract [en]

    We present an approach to partitioning and mapping for multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have proposed a schedulability analysis for such systems, including a worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Based on this analysis, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, and process mapping. We present a branch and bound algorithm for solving these problems. Our heuristic is able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

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