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• 201.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Arithmetic2010In: Handbook of signal processing systems / [ed] Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, Springer , 2010, 1, p. 283-327Chapter in book (Refereed)

Handbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels.

• 202.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Bit-level pipelinable general and fixed coefficient digit-serial/parallel multipliers based on shift-accumulation2002In: International Conference on Electronics, Circuits, and Systems,2002, Piscataway, NJ: IEEE , 2002, p. 493-Conference paper (Refereed)

In this work, we introduce a novel approach to digit-serial/parallel multiplication. This general class of multipliers is based on shift-accumulation which also makes the approach suitable for implementation of shift-accumulators in distributed arithmetic. As a variable in the design process, the maximal number of cascaded full-adders can be selected. Thus, it is possible to, as a special case, obtain a bit-level pipelined multiplier. Both general and fixed coefficient multiplication is considered. The hardware complexity is low compared with other approaches.

• 203.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Design of linear-phase FIR filters combining subexpression sharing with MILP2002In: Midwest Symposium on Circuits and Systems,2002, Piscataway, NJ: IEEE , 2002, p. III/9-Conference paper (Refereed)

In this work we formulate a mixed integer linear programming (MILP) problem for designing linear-phase FIR filters with low arithmetic complexity. By incorporating subexpression sharing in the problem formulation, the number of adders will be lower compared with previous approaches, where minimizing the number of non-zero bits of the coefficients has been the objective.

• 204.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Design of reduced complexity linear-phase polyphase FIR filters using mixed integer linear programming2004In: Swedish System-on-Chip Conference 2004, 2004Conference paper (Other academic)

In this work a mixed integer linear programming (MILP) formulation for the design of a class of linear-phase FIR filters are presented. The formulation can be solved using general purpose MILP solvers to obtain filter implementationwith a minimum number of signed-power-of-two (SPT) terms given a filter specification. The filter structures considered are based on reduced complexity polyphase decomposition. It is shown that the total number of SPT terms per sample can be reduced using this filter architecture. However, the savings are not as large as other work propose, when optimal design techniques are used.

• 205.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
ILP modelling of the common subexpression sharing problem2002In: International Conference on Electronics, Circuits, and Systems,2002, Piscataway, NJ: IEEE , 2002, p. 1171-Conference paper (Refereed)

Subexpression sharing is an important implementation issue when one data is multiplied with many constants or a sum of products is computed. By modelling the subexpression sharing problem using integer linear programming (ILP) an optimal solution can be found. Further, the model can be directly incorporated with the design of algorithms that have linear design constraints, e.g., linear-phase FIR filters. The proposed method is compared with previously reported algorithms. It produces better results than other subexpression sharing methods, even though it is still not comparable with the optimal method based on graph representation. However, the possibility to expand the ILP model beyond subexpression sharing is discussed. This would then produce identical results to the optimal adder graph method.

• 206.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Low-complexity and high-speed constant multiplications for digital filters using carry-save arithmetic2011In: Digital Filters / [ed] Fausto Pedro Garcia Marquez, Rijeka, Croatia: InTech, 2011, p. 241-256Chapter in book (Other academic)

In this work we discuss the realization of constant multiplication using a minimum number of carry-save adders. We consider both non-redundant and carry-save representation for the input data. For both cases we present all possible interconnection topologies, using up to six and five adders, respectively. These are sufficient to realize constant multiplications for all coefficients with a wordlength up to 19 bits.

• 207.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Low-complexity constant multiplication using carry-save arithmetic for high-speed digital filters2007In: International Symposium on Image and Signal Processing and Analysis,2007, Piscataway: IEEE , 2007, p. 212-217Conference paper (Refereed)
• 208.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
CMOS Data Converters for Communications2000Book (Other academic)

CMOS Data Converters for Communications distinguishes  itself from other data converter books by emphasizing system-related  aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given  communication system (baseband, passband, and multi-carrier systems).  The authors also review CMOS data converter architectures and discuss  their suitability for communications.

The rest of the book is  dedicated to high-performance CMOS data converter architecture and  circuit design. Pipelined ADCs, parallel ADCs with an improved passive  sampling technique, and oversampling ADCs are the focus for ADC  architectures, while current-steering DAC modeling and implementation  are the focus for DAC architectures. The principles of the  switched-current and the switched-capacitor techniques are reviewed  and their applications to crucial functional blocks such as  multiplying DACs and integrators are detailed.

The book outlines the  design of the basic building blocks such as operational amplifiers,  comparators, and reference generators with emphasis on the practical  aspects. To operate analog circuits at a reduced supply voltage,  special circuit techniques are needed. Low-voltage techniques are also  discussed in this book.

CMOS Data Converters for Communications can be used as a  reference book by analog circuit designers to understand the data  converter requirements for communication applications. It can also be  used by telecommunication system designers to understand the  difficulties of certain performance requirements on data converters.  It is also an excellent resource to prepare analog students for the  new challenges ahead.

• 209.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model: Optimization of an Eight-Bit C-xC SAR ADC2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis

In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor network to performthe conversion. Focus in the master’s thesis was set to understand how the charge is redistributedin the network during the conversion and calibration phase. Redundancy andparasitic capacitors is present in the system and rises the need for extra conversion steps aswell as a calibration algorithm. The calibration algorithm, Bit Weight Estimation, calculatesa weight corresponding to each bit which is used in the last conversion step to perform adigital weighting. The result of extensive calculations in different C-xC capacitor networkswas a model in Python of an N-bit C-xC sar adc. That model was used to create a model ofan eight-bit C-xC sar adc and finding suitable parameters for it through calculations andsimulations. The parameters giving the best inl was chosen. With the best parameters theC-xC sar adc static and dynamic performance was tested and showed an inl of less than1lsb, snr of 47:8 dB and enob of 7:6 bits.

fulltext
• 210.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores2013Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis

FPGA-kort är ett bra verktyg för företag som snabbt vill kunna ta fram en prototyp för nya projekt, då de är omprogrammeringsbara så att samma hårdvara kan användas för att göra prototyper till mänger av olika system. Ett vanligt programmeringsspråk för att programmera FPGA-kort är VHDL som är ett hårdvarunära språk. Som ett komplement till VHDL är det väldigt användbart att kunna köra något mer generellt programspråk som till exempel C. Detta går att lösa genom att man använder en NIOS2-kärna i FPGA-kretsen och överför kompilerad C-kod till den från en persondator.

Denna rapport kommer att beskriva hur man på ett Altera DE2 FPGA-kort kan implementera olika lösningar för att använda externa gränssnitt till en NIOS2–kärna. Det vill säga hur man kan använda den hårdvara man programmerat med VHDLkod i mjukvaruprogrammen man skriver i C-kod. Fokus kommer att ligga på att jämföra olika lösningar för att visa text på extern skärm via VGA-gränssnittet. En lösning är skapad i SOPC Builder där alla komponenter är skrivna i VHDL och en lösning är skapad i QSYS där Altera University Programs färdiga IP-block används. Även en PS/2-lösning för NIOS2-kärnan kommer att förklaras.

fulltext
• 211.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Building Blocks for Low-Voltage Analog-to-Digital Interfaces2014Licentiate thesis, comprehensive summary (Other academic)

In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.

To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/$\small\sqrt{Hz}$ while consuming 6.8 mW.

Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.

Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist.

Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

1. An Analog Receiver Front-End for Capacitive Body-Coupled Communication
Open this publication in new window or tab >>An Analog Receiver Front-End for Capacitive Body-Coupled Communication
2012 (English)In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper, Poster (with or without abstract) (Other academic)
##### Abstract [en]

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

IEEE, 2012
##### National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
##### Identifiers
urn:nbn:se:liu:diva-84302 (URN)10.1109/NORCHP.2012.6403137 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
##### Conference
30th Norchip Conference 2012, The Nordic Microelectronics event, 12-13 November 2012, Copenhagen, Denmark
Available from: 2012-10-04 Created: 2012-10-04 Last updated: 2018-11-08Bibliographically approved
2. Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
Open this publication in new window or tab >>Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, p. 381-384Conference paper, Oral presentation only (Refereed)
##### Abstract [en]

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

##### Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
##### Series
International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
##### National Category
Signal Processing
##### Identifiers
urn:nbn:se:liu:diva-87996 (URN)10.1109/ISCAS.2013.6571860 (DOI)000332006800094 ()978-1-4673-5760-9 (ISBN)
##### Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-01-28 Created: 2013-01-28 Last updated: 2018-11-08
3. Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
Open this publication in new window or tab >>Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
2014 (English)In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, p. 185-188Conference paper, Published paper (Refereed)
##### Abstract [en]

The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation  achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).

##### Place, publisher, year, edition, pages
Poland: , 2014
##### Keywords
SAR ADC, Reference voltage buffer, DAC
##### National Category
Electrical Engineering, Electronic Engineering, Information Engineering
##### Identifiers
urn:nbn:se:liu:diva-106913 (URN)10.1109/MIXDES.2014.6872182 (DOI)000345852100036 ()2-s2.0-84906699621 (Scopus ID)978-83-63578-04-6 (ISBN)
##### Conference
21st International Conference, Mixed Design of Integrated Circuits and Systems (MIXDES 2014), June 19-21, 2014, Lublin, Poland
Available from: 2014-05-26 Created: 2014-05-26 Last updated: 2015-11-18
4. A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
Open this publication in new window or tab >>A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 28-38Article in journal (Refereed) Published
##### Abstract [en]

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

##### Place, publisher, year, edition, pages
Elsevier, 2015
##### National Category
Signal Processing
##### Identifiers
urn:nbn:se:liu:diva-111957 (URN)10.1016/j.vlsi.2015.01.002 (DOI)000357054300003 ()
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2018-11-08Bibliographically approved
Building Blocks for Low-Voltage Analog-to-Digital Interfaces
omslag
presentationsbild
• 212.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
An Analog Receiver Front-End for Capacitive Body-Coupled Communication2012In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper (Other academic)

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

• 213.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
A Study on the Design of Reconfigurable ADCs2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis

In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results.

Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications.

The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

FULLTEXT03
• 214.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
A Study on Switched-Capacitor Blocks for Reconfigurable ADCs2011In: Electronics, Circuits and Systems (ICECS), 2011, 2011, p. 649-652Conference paper (Refereed)

Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.sigma-delta ADCs

• 215.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 28-38Article in journal (Refereed)

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

• 216.
Norwegian University of Science and Technology.
Norwegian University of Science and Technology. Norwegian University of Science and Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Norwegian University of Science and Technology.
Analysis of switching activity in DSP signals in the presence of noise2009In: IEEE EUROCON, Piscataway: IEEE , 2009, p. 234-239Conference paper (Refereed)

Input switching activity is one of the deciding factors for power consumption in digital signal processing components. For accurate power estimation, it is essential to have knowledge about the switching activity in the input signal, including how this activity changes in different environments, e.g., in the presence of noise. The dual bit type (DBT) method aims at characterizing the bit-level switching activity in a signal, using signal statistics. However, the DBT method requires that the correlation coefficient and switching activity for the most significant bit of the signal are available. In this paper we give an expression for direct calculation of the correlation coefficient for the most significant bit in a signal, using the word-level correlation coefficient. Using simulation results we examine the accuracy of the given method to calculate the switching activity and correlation coefficient for the most significant bit. Furthermore, we derive expressions for accurately calculating the variance and word-level correlation coefficient for a correlated signal, when an additional noise of a given variance is added to the signal. This can be used to estimate the bit-level switching activity in a signal in the presence of noise. Finally, based on this we study the impact the additional noise has on the switching activity of the resulting signal.

• 217.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Implementation of a Low-Cost Analog-to-Digital Converter for Audio Applications Using an FPGA2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis

The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a ﬁrst order passive loop-ﬁlter and (2) a - converter with a second order active loop-ﬁlter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Diﬀerential-Signaling) input buﬀers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Eﬀectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs$0.53for mono audio and \$0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).

fulltext
• 218.
Multimedia Systems Department, Faculty of Electronics, Gdansk University of Technology, Gdansk 80-952, Poland.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Teleinformation Networks Department, Faculty of Electronics, Gdansk University of Technology, Gdansk 80-952, Poland.
A fractionally delaying complex Hilbert transform filter2008In: IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, Vol. 55, no 5, p. 452-456Article in journal (Refereed)

In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter-the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay. © 2008 IEEE.

• 219.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
A computer-aided approach to design of robust analog circuits2006Doctoral thesis, monograph (Other academic)

Traditional design methods for analog circuits are based on rules-of-thumbs, experience, and trial-and-error approaches involving the use of circuit simulators. It is an unstructured process, which is time-consuming, error prone, and requires the attention of a skilled analog designer. This situation calls for design methodologies that are more efficient.

We have developed an efficient approach and corresponding tools that address these issues. A computer-aided design tool for design of large analog circuits with low level of human intervention has been developed. The tool combines efficient performance measure evaluation and optimization methods to determine the device sizes and generate layouts for analog circuits. Large analog circuits with about 200 devices have been designed. The circuits are optimized with respect to, e.g., power consumption, and subject to a large number of performance requirements. All performance measures are automatically derived, which reduces the probability of introducing errors.

Experimental results indicate that our approach can be used to design robust high-performance analog circuits with improved performance compared to manual approaches. Furthermore, the computer-aided tool decreases both the overall design time and the time required of a skilled designer.

To accomplish this, an optimization strategy that enables device sizing without an initial design has been developed. Robust circuits are obtained by taking the variations in the manufacturing process into account. Degrading layout effects are also considered using a parasitic feedback technique. To gain insight and allow exploration of the complex relation between performance measures in analog circuits, we have developed techniques for design space exploration.

• 220.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Studies on Design Automation of Analog Circuits - the Design Flow2003Licentiate thesis, monograph (Other academic)

During the past few years the concept of system-on-chip (SoC) have become an important segment in the market of integrated circuits. This recent development have increased not only the number of devices and the functionality that can be put on a chip, but the chips now includes both digital and analog circuits.

ln digital design the level of abstraction and automation in the design flow have manage to keep in phase with this development. However, this is not the case for analog circuits. The analog design flow suffers from a low-level of abstraction and automation, making it one of the major bottlenecks in mixed signal design.

Here we address the problem of automating the analog design now. Specifically, the problem of determining the design parameters for an analog integrated circuit at the cell level is considered. An optimization method in conjunction with automatically derived equations for the circuit performance is used to solve this task. The methods and algorithms used have been implemented into a tool that can be used to design continuous-time analog amplifiers. Using this approach the design time can be reduced from weeks to hours, at the same time the circuit performance can potentially be increased.

The coupling between the device sizing and layout generation is also addressed. A parasitic feedback approach is used in order to make sure that the performance requirements are met for the circuit layout.

The tool is also used to explore the design space in analog amplifier design and find trade-offs. An example where three different amplifier topologies are compared is given. It shows that large savings can be made, with respect to both area and power consumption, by selecting the best topology to meet a specific performance specification.

• 221.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Layout generation of matched capacitors2002In: Radiovetenskap och Kommunikation,2002, 2002Conference paper (Refereed)
• 222.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
A Design Platform for Computer-Aided Design of Analog Amplifiers2003In: Swedish System-on-Chip Conferance,2003, 2003Conference paper (Refereed)
• 223.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
An Equation-Based Optimization Approach for Analog Circuit Design2003In: International Symposium on Signals, Circuits Systems,2003, 2003, p. 77-80Conference paper (Refereed)
• 224.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
An Optimization-Based Approach for Analog Circuit Design2003In: European Conference on Circuit Theory and Design,2003, 2003, p. 369-372Conference paper (Refereed)
• 225.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Automatic Device Sizing in Analog Circuit Design2002In: Radiovetenskap och Kommunikation,2002, 2002, p. 187-191Conference paper (Refereed)
• 226.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Design space exploration and trade-offs in analog amplifier design2003In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings / [ed] Jorge Juan Chico, Enrico Macii, Springer Berlin/Heidelberg, 2003, Vol. 2799, p. 338-347Conference paper (Refereed)

In this paper, we discuss an optimization-based approach for design space exploration to find limitations and possible trade-offs between performance metrics in analog circuits. The exploration guides the designer when making design decisions. For the design space exploration, which is expensive in terms of computation time, we use an optimization-based device sizing tool that runs concurrent optimization tasks on a network of workstations. The tool enables efficient and accurate exploration of the available design space. As a design example, we investigate three operational transconductance amplifiers, OTAs, implemented in a standard 0.35-mum CMOS process. This example shows that large savings in terms of chip area and power consumption can be made by selecting the most suitable circuit.

• 227.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Optimization-Based Design Space Exploration of Analog Circuits2003In: European Conference on Circuit Theory and Design,2003, 2003, p. 393-396Conference paper (Refereed)
• 228.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Time and Performance Efficient Design of Analog Circuits2005In: Radiovetenskap och Kommunikation,2005, 2005, p. 181-186Conference paper (Refereed)
• 229.
Linköping University, Department of Electrical Engineering, Electronics System.
Utveckling av Breakoutbox för Fuel Flow Transmitter2010Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis

Development and construction of an electronic Breakout box is the main work for this thesis. The box is a part of a test system for the component Fuel Flow Transmitter and should convert signals to be suitable for a frequency counter. A previously constructed Breakoutbox for this purpose is being old and needed to be recreated. So SAAB Aerotech, Aircraft services, the company for the thesis work wanted to construct a new, more sustainable Breakoutbox adapted to a more modern technology. The signals to the box comes from the transmitter and should be converted to suitable signals for a frequency counter so it can show pulse and time difference between the signals. Both a digital and an analog approach for this purpose have been examined in the work. The result was that the analog solution worked better because the conversion could be performed with OP-amplifier instead of algorithms in a microprocessor. Many problems occured in this thesis work that wasn’t included in the beginning so the most important property proved to be the ability to solve this problems. The Breakout box finally met the requirements from the specification and will in the future be used instead of the old Breakout box as a component in the test system for the Fuel Flow Transmitter.

Utveckling av Breakoutbox för Fuel Flow Transmitter
• 230. Holm, Kjell
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Low-complexity and low-power color space conversion for digital video2006In: IEEE Norchip Conference,2006, Piscataway: IEEE , 2006Conference paper (Refereed)
• 231.
n/a.
n/a. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Implementation aspects of second-order LDI/LDD allpass filters2001In: Proc. IEEE European Conf. on Circuit Theory and Design, ECCTD'01, 2001, p. 237-240Conference paper (Refereed)
• 232.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, Department of Electrical Engineering.
Pulse And Noise shaping D/A converter (PANDA) – Block implementation in 65nm SOI CMOS2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis

In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology.

The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used.

This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.

FULLTEXT01
• 233.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
An optimization-based approach to efficient design of analog circuits2006Doctoral thesis, monograph (Other academic)

Traditional design methods for analog circuits are based on rules-of-thumbs, experience, and trial-and-error approaches involving the use of circuit simulators. It is an unstructured process, which is time-consuming, error prone, and requires the attention of a skilled analog designer. This situation calls for design methodologies that are more efficient.

We have developed an efficient approach and corresponding tools that address these issues. A computer-aided design tool for design of large analog circuits with low level of human intervention has been developed. The tool combines efficient performance measure evaluation and optimization methods to determine the device sizes and generate layouts for analog circuits. Large analog circuits with about 200 devices have been designed. The circuits are optimized with respect to, e.g., power consumption, and subject to a large number of performance requirements. All performance measures are automatically derived, which reduces the probability of introducing errors.

Experimental results indicate that our approach can be used to design robust highperformance analog circuits with improved performance compared to manual approaches. Furthermore, the computer-aided tool decreases both the overall design time and the time required of a skilled designer.

We have developed a technique that derives the performance equations directly from the circuit schematics as well as techniques for efficient evaluation of the equations. This approach reduces the risk of introducing errors and enables the use of accurate device models, i.e., high-accuracy equations without approximations are obtained.

In fully differential circuits, common-mode stabilization is required. Even though a multitude of common-mode feedback circuits have been presented in the literature, the performance requirements for these circuits are rarely fully explained. Here, the common-mode feedback design problem is addressed to gain design insights. A Volterra series model is used to analyze the distortion terms caused by the use of a common-mode feedback. From this analysis, the DC gain, bandwidth, and stability requirements of the common-mode loop are discussed.

• 234.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
A design path for optimization-based analog circuit design2002In: IEEE Midwest Symposium on Circuits and System,2002, 2002, p. 287-290Conference paper (Refereed)
• 235.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Automated Design of Analog Filters at Transistor Level2005In: Swedish System-on-Chip Conferance,2005, 2005Conference paper (Refereed)
• 236.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Automated Device Sizing of Analog Circuits With Yield Enhancement2004In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
• 237.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Optimization-Based Device Sizeing in Analog Circuit Design2002In: Swedish System-on-Chip Conferance,2002, 2002Conference paper (Refereed)
• 238.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Using Optimization to Find Design Trade-Offs in Analog Amplifier Design2003In: Swedish System-on-Chip Conferance,2003, 2003Conference paper (Refereed)
• 239.
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Yield Enhancement Techniques in Analog Design Automation2004In: IEEE NorChip Conf,2004, 2004Conference paper (Other academic)
• 240.
Linköping University, Department of Electrical Engineering.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, Department of Electrical Engineering.
A polynomial-based division algorithm2002In: IEEE Int. Symp. Circuits and Systems, 2002, 2002, p. III-571-III-574Conference paper (Refereed)

A polynomial-based division algorithm and a corresponding hardware structure are proposed. The proposed algorithm is shown to be competitive to other conventional algorithms like the Newton-Raphson algorithm for up to about 32 bits accuracy. For example, using Newton-Raphson with less than 12 bits accuracy of the initial approximation, requires 33% more general multiplications than the proposed algorithm, in order to achieve 24 bits accuracy.

• 241.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Utvecklingsmetodik för styrning av stegmotorer med en FPGA2013Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis

This Bachelor thesis have been done for Calmon Stegmotorteknik AB (CST) to develop the FPGA part of their developmentplatform. This thesis is created to give thoughts and theory about the development methodology used in this project. CST:s development platform will be used for video processing, motor controls and also measurement and instrument applications.This thesis however concerns only the functions that is needed for using motor controls on the development board. Which includes implementation of PWM, microstepping control and also motor control with help of fullstep and halfstep.

Examensarbetet
• 242.
Mittuniversitetet.
Mittuniversitetet. Mittuniversitetet. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
On the number representation in sub-expression sharing2010In: International Conference on Signals and Electronic Systems, ICSES'10 - Conference Proceeding 2010,, 2010, p. 17-20Conference paper (Refereed)

The core of many DSP tasks is Multiplication ofone data with several constants, i.e. in Digital filtering, image processing DCT and DFT. The Modern Portable equipments like Cellular phones and MP3 players which has DSP circuits,involve large number of multiplications of one variable with several constants (MCM) which leads to large area, delay and energy consumption in hardware. Multiplication operation can be realized using addition/subtraction and shifts without general multipliers. Different number representations are used in MCM algorithms and there are differnet views about different representations. Some of the authors termed the Canonic Signed Digit (CSD) representation as better for subexpression sharing. We have compared the results of CSD and Binary representations using our Generalized MCM Algorithm on Random Matrices and come to conclusion that binary representation is better compared to CSD when a system has multiple inputs and multiple outputs.

• 243.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time.

The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers.

The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

Sohail_02092012
• 244.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Finite wordlength properties of matrix inversion algorithms in fixed-point and logarithmic number system2011In: 2011 20th European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ, USA: IEEE , 2011, p. 673-676Conference paper (Refereed)

Matrix inversion is sensitive towards the number representation used. In this paper simulations of matrix inversion with numbers represented in the fixed-point and logarithmic number systems (LNS) are presented. A software framework has been implemented to allow extensive simulation of finite wordlength matrix inversion. Six different algorithms have been used and results on matrix condition number, wordlength, and to some extent matrix size are presented. The simulations among other things show that the wordlength requirements differ significantly between different algorithms in both fixed-point and LNS representations. The results can be used as a starting point for a matrix inversion hardware implementation.

• 245.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
On Using the Logarithmic Number System for Finite Wordlength Matrix Inversion2011In: The 54th IEEE International Midwest Symposium on Circuits and Systems: IEEE MWSCAS 2011, Piscataway, NJ, USA: IEEE , 2011, p. 1-4Conference paper (Refereed)

Matrix inversion is a key operation in for instance adaptivefilters and MIMO communication system receivers. For ill-conditionedchannel matrices long wordlengths are required for fixed-point implementationof matrix inversion. In this work, the wordlength/error tradeoffsfor matrix inversion using different algorithms with fixed-point andlogarithmic number systems (LNS) are considered. LNS provides higherresolution for small numbers and a larger dynamic range. Also, it willalter the cost of the basic operations in the algorithms. The results showthat also the wordlength required to achieve a comparable error differsignificantly between different algorithms and for most algorithms isreduced for LNS compared to fixed-point.

• 246.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs2012In: 22nd International Conference on Field Programmable Logic and Applications (FPL) / [ed] Dirk Koch, Satnam Singh, Jim Torresen, Piscataway, NJ, USA: IEEE Communications Society, 2012, p. 71-74Conference paper (Refereed)

Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.

• 247.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Low Power Gain Cell Arrays: Voltage Scaling and Leakage Reduction2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis

In this thesis, a fully logic - compatible Gain - Cell (GC) based Dynamic - Random - Access (DRAM) with a storage capacity of 2048 bit is designed in UMC – 180 nm technology. The GC used is a two transistor PMOS (2PMOS) cell. This thesis aims at building the foundation for further research on the effects of supply voltage ff scaling on retention time, leakage and power consumption. Different techniques are used to reduce leakage current for longer retention time and ultimately low power. Different types of decoders are analyzed for low power. First, general concepts of memories are presented. Furthermore, the topic of leakage and its effect on retention time and power consumption is introduced. Two memories are designed, first one is single port memory with improved retention time. Finally, a Two port memory with all peripherals, which consists of he GC array, Decoder, Drivers, Registers, Pulse generators is designed. All the simulations for voltage scaling and retention time are shown.

fulltext
• 248.
ECE Department, Isfahan University of Technology, Isfahan, Iran.
ECE Department, Isfahan University of Technology, Isfahan, Iran. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Calibration of sigma-delta analog-to-digital converters based on histogram test methods2010In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper (Refereed)

In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.

• 249.
ECE Dept. Isfahan University of Technology, Isfahan, Iran.
ECE Dept. Isfahan University of Technology, Isfahan, Iran. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Calibration of high-resolution flash ADCS based on histogram test methods2010In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, p. 114-117Conference paper (Other academic)

In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

• 250.
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran. Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
A nonlinearity error calibration technique for pipelined ADCs2011In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 44, no 3, p. 229-241Article in journal (Refereed)

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

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