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  • 201.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-performance and Low-voltage Datapath and Interconnect Design Challenges2004In: In proceedings of: 12th IEEE Mediterranean Electrotechnical Conference, MELECON, 12-15 May, Dubrovnik, Croatia, 2004Conference paper (Refereed)
  • 202.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arakawa, Fumio
    Hitachi, Tokyo, Japan.
    Session 20 overview - processor building blocks2005Conference paper (Other (popular science, discussion, etc.))
  • 203.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arimoto, Kazutami
    Renesas Corp, Itami, Hyogo 6640005 Japan .
    Cantatore, Eugenio
    Eindhoven University Technology, NL-5600 MB Eindhoven, Netherlands .
    Zhang, Kevin
    Intel Corp, Hillsboro, OR 97124 USA .
    Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 1, p. 3-6Article in journal (Other academic)
    Abstract [en]

    n/a

  • 204.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Balamurugan, G.
    Intel Corp., USA.
    Soumyanath, K.
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Leakage-tolerant circuit and method for large register files2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

  • 205.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Multi-phase clock generation and synchronization2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for controlling a local clock includes receiving a reference clock and generating a phase-shifted version of the reference clock. The two clocks are synchronized using a closed-loop method that produces a control signal. The control signal is smoothed during the closed-loop method and the smoothed signal is then used, instead of the control signal, in generating the phase-shifted clock

  • 206.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Intel Corporation, Hillsboro, USA.
    Borkar, S.
    Intel Corporation, Hillsboro, USA.
    Rahman, A.
    Intel Corporation, Hillsboro, USA.
    Webb, C.
    Intel Corporation, Hillsboro, USA.
    A burn-in tolerant dynamic circuit technique2002In: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, p. 81-84Conference paper (Refereed)
  • 207.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Conditional Keeper Technique for Sub-0.13mm Wide Dynamic Gates2001In: In proceedings of: International Symposium on VLSI Circuits, 2001, p. 29-30Conference paper (Refereed)
  • 208.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Sournyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS2001In: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design, New York, USA: ACM , 2001, p. 68-71Conference paper (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.

     

  • 209.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Conditional burn-in keeper for dynamic circuits2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

  • 210.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Fast static receiver with input dependent inversion threshold.2006Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

  • 211.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Voltage-level converter2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

  • 212.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram K.
    Intel Corp., Hillsboro, USA.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Apperson, Stuart
    Intel Corp., Hillsboro, USA.
    Bloechel, Bradley
    Intel Corp., Hillsboro, USA.
    Borkar, Shekar
    Intel Corp., Hillsboro, USA.
    A 3.5GHz 32mW 150nm multiphase clock generator for high-performande microprocessors.2003In: IEEE International Solid-State Circuits Conference.,2003, Augusta, Maine: J.S.McCarthy Printers , 2003, p. 112-Conference paper (Refereed)
  • 213.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 214.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 215.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Inten Corp., USA.
    Narendra, Siva
    Inten Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 216.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corsp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 217.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 218.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A sub-130-nm conditional keeper technique2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, p. 633-638Article in journal (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

  • 219.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp, USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Fast dual-rail dynamic logic style2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 220.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Flash (II)-Domino: a fast dual-rail dynamic logic style2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 221.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits1999In: In proceedings of: IEEE International Conference on Electronics, Circuits, And System, 1999, p. 209-212Conference paper (Refereed)
    Abstract [en]

     

  • 222.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering2000In: In proceedings of: IEEE International Symposium on Circuits and Systems. Vol.5, IEEE , 2000, p. 465-468Conference paper (Refereed)
    Abstract [en]

    In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction

  • 223.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits1998In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, p. 245-249Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

  • 224.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Manoj, Sinha
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Differential charge transfer sense ampliifier2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

  • 225.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mathew, S.
    Intel Corp., USA.
    Advanced high-performance microprocessor design challenges and solutions2002In: Proceedings of 15th Annual IEEE International ASIC/SOC Conference, 2002, p. 476-476Conference paper (Refereed)
  • 226.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reynaert, Patrick
    Katholieke University of Leuven, Belgium .
    Ytterdal, Trond
    Norwegian University of Science and Technology, Norway .
    Editorial Material: Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1511-1514Article in journal (Other academic)
    Abstract [en]

    n/a

  • 227.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, D.
    Intel Corp., Hillsboro, USA.
    Krishnamurthy, Ram
    Intel Corp., Hillsboro, USA.
    De, V.
    Intel Corp., Hillsboro, USA.
    Borkar, S.
    Intel Corp., Hillsboro, USA.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Bitline leakage equalization for sub-100nm caches.2003In: ESSCIRC 2003,2003, Lissabon: Grafica Maiadouro SA , 2003, p. 401-Conference paper (Refereed)
  • 228.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, Dinesh
    Intel Corp., USA.
    Hsu, Steven K.
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    De, Vivek K.
    Intel Corp., USA.
    Statis random access memory with symmetric leakage-compensated bit line.2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

  • 229.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices. Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    Integrated circuits bus architecture including a full-swing, clocked, commongate receiver for fast on-chip signal transmission2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.

  • 230.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Soumynath, Krishnamurthy
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates.2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

  • 231.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction1997In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1997, p. 305-314Conference paper (Refereed)
    Abstract [en]

    A new wire estimation technique is presented. It utilizes the topology of the netlist and is sensitive to the actual design. It has the unique quality to estimate the length of every power consuming interconnection individually. Compared to other wire length estimation techniques which use average or total wire length, the result of the new technique shows a strong correlation with the result of "real" automatic placement and route tools. Hence it can estimate a reasonable wire capacitance for each interconnection. The individual wire lengths, combined with individual node activities, are essential for an accurate power estimation.

  • 232.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Improving Cell Libraries for Low Power Design1996In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1996, p. 317-325Conference paper (Refereed)
  • 233. Order onlineBuy this publication >>
    Alvbrant, Joakim
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A study on emerging electronics for systems accepting soft errors2016Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Moore’s law has until today mostly relied on shrinkage of the size of the devices inintegrated circuits. However, soon the granularity of the atoms will set a limit together with increased error probability of the devices. How can Moore’s law continue in thefuture? To overcome the increased error rate, we need to introduce redundancy. Applyingmethods from biology may be a way forward, using some of the strategies that transformsan egg into a fetus, but with electronic cells.

    A redundant system is less sensitive to failing components. We define electronic clayas a massive redundancy system of interchangeable and unified subsystems. We show how a mean voter, which is simpler than a majority voter, impact a redundant systemand how optimization can be formalized to minimize the impact of failing subsystems.The performance at given yield can be estimated with a first order model, without the need for Monte-Carlo simulations. The methods are applied and verified on a redundant finite-impulse response filter.

    The elementary circuit behavior of the memristor, ”the missing circuit element”, is investigated for fundamental understanding and how it can be used in applications. Different available simulation models are presented and the linear drift model is simulated with Joglekar-Wolf and Biolek window functions. Driven by a sinusoidal current, the memristor is a frequency dependent component with a cut-off frequency. The memristor can be densely packed and used in structures that both stores and compute in the same circuit, as neurons do. Surrounding circuit has to affect (write) and react (read) to the memristor with the same two terminals.

    We looked at artificial neural network for pattern recognition, but also for self organization in electronic cell array. Finally we look at wireless sensor network and how such system can adopt to the environment. This is also a massive redundant clay-like system.

    Future electronic systems will be massively redundant and adaptive. Moore’s law will continue, not based on shrinking device sizes, but on cheaper, numerous, unified and interchangeable subsystems.

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  • 234.
    Alvbrant, Joakim
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Keshmiri, Vahid
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Transfer Characteristics and Bandwidth Limitation in a Linear-Drift Memristor Model2015In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), IEEE , 2015, p. 332-335Conference paper (Refereed)
    Abstract [en]

    The linear-drift memristor model, suggested by HP Labs a few years ago, is used in this work together with two window functions. From the equations describing the memristor model, the transfer characteristics of a memristor is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with some of its physical parameters. The design space is elaborated upon and it is shown that the state speed, the variation of the doped and undoped regions of the memristor, is inversely proportional to the physical length, and depth of the device. The transfer characteristics is simulated for Joglekar-Wolf, and Biolek window functions and the results are analyzed. The Joglekar-Wolf window function causes a distinct behavior in the tranfer characteristics at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also elaborate on the design constraints derived from the transfer characteristics.

  • 235.
    Alvbrant, Joakim
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Study and Simulation Example of a Redundant FIR Filter2012In: Proceedings 30th Norchip Conference, IEEE, 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.

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  • 236.
    Alvila, Markus
    Linköping University, Department of Electrical Engineering, Information Coding.
    A Performance Evaluation of Post-Quantum Cryptography in the Signal Protocol2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The Signal protocol can be considered state-of-the-art when it comes to secure messaging, but advances in quantum computing stress the importance of finding post-quantum resistant alternatives to its asymmetric cryptographic primitives.

    The aim is to determine whether existing post-quantum cryptography can be used as a drop-in replacement for the public-key cryptography currently used in the Signal protocol and what the performance trade-offs may be.

    An implementation of the Signal protocol using commutative supersingular isogeny Diffie-Hellman (CSIDH) key exchange operations in place of elliptic-curve Diffie-Hellman (ECDH) is proposed. The benchmark results on a Samsung Galaxy Note 8 mobile device equipped with a 64-bit Samsung Exynos 9 (8895) octa-core CPU shows that it takes roughly 8 seconds to initialize a session using CSIDH-512 and over 40 seconds using CSIDH-1024, without platform specific optimization.

    To the best of our knowledge, the proposed implementation is the first post-quantum resistant Signal protocol implementation and the first evaluation of using CSIDH as a drop-in replacement for ECDH in a communication protocol.

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    A Performance Evaluation of Post-Quantum Cryptography in the Signal Protocol
  • 237.
    Alwan, Abdulrahman
    Linköping University, Department of Electrical Engineering, Information Coding.
    Implementation of Wavelet-Kalman Filtering Technique for Auditory Brainstem Response2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Auditory brainstem response (ABR) evaluation has been one of the most reliable methods for evaluating hearing loss. Clinically available methods for ABR tests require averaging for a large number of sweeps (~1000-2000) in order to obtain a meaningful ABR signal, which is time consuming.  This study proposes a faster new method for ABR filtering based on wavelet-Kalman filter that is able to produce a meaningful ABR signal with less than 500 sweeps. The method is validated against ABR data acquired from 7 normal hearing subjects with different stimulus intensity levels, the lowest being 30 dB NHL. The proposed method was able to filter and produce a readable ABR signal using 400 sweeps; other ABR signal criteria were also presented to validate the performance of the proposed method.

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  • 238.
    Amarasuriya, Gayan
    et al.
    Princeton University, NJ 08544 USA.
    Larsson, Erik G
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Vincent Poor, H.
    Princeton University, NJ 08544 USA.
    Wireless Information and Power Transfer in Multiway Massive MIMO Relay Networks2016In: IEEE Transactions on Wireless Communications, ISSN 1536-1276, E-ISSN 1558-2248, Vol. 15, no 6, p. 3837-3855Article in journal (Refereed)
    Abstract [en]

    Simultaneous wireless information and power transfer techniques for multiway massive multiple-input multiple-output (MIMO) relay networks are investigated. By using two practically viable relay receiver designs, namely 1) the power splitting receiver and 2) the time switching receiver, asymptotic signal-to-interference-plus-noise ratio (SINR) expressions are derived for an unlimited number of antennas at the relay. These asymptotic SINRs are then used to derive asymptotic symmetric sum rate expressions in closed form. Notably, these asymptotic SINRs and sum rates become independent of radio frequency-to-direct current (RF-to-DC) conversion efficiency in the limit of infinitely many relay antennas. Moreover, tight average sum rate approximations are derived in closed form for finitely many relay antennas. The fundamental tradeoff between the harvested energy and the sum rate is quantified for both relay receiver structures. Notably, the detrimental impact of imperfect channel state information (CSI) on the MIMO detector/precoder is investigated, and thereby, the performance degradation caused by pilot contamination, which is the residual interference due to nonorthogonal pilot sequence usage in adjacent/cochannel systems, is quantified. The presence of cochannel interference (CCI) can be exploited to be beneficial for energy harvesting at the relay, and consequently, the asymptotic harvested energy is an increasing function of the number of cochannel interferers. Notably, in the genie-aided perfect CSI case, the detrimental impact of CCI for signal decoding can be cancelled completely whenever the number of relay antennas grows without bound. Nevertheless, the pilot contamination severely degrades the sum rate performance even for infinitely many relay antennas.

  • 239.
    Ambuluri, Sreehari
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Garrido, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Caffarena, Gabriel
    Boadilla del Monte, Madrid, Spain.
    Ogniewski, Jens
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Ragnemalm, Ingemar
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    New Radix-2 and Radix-22 Constant Geometry Fast Fourier Transform Algorithms For GPUs2013Conference paper (Refereed)
    Abstract [en]

    This paper presents new radix-2 and radix-22 constant geometry fast Fourier transform (FFT) algorithms for graphics processing units (GPUs). The algorithms combine the use of constant geometry with special scheduling of operations and distribution among the cores. Performance tests on current GPUs show a significant improvements compared to the most recent version of NVIDIA’s well-known CUFFT, achieving speedups of up to 5.6x.

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  • 240.
    Amgård, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Bergman, Kevin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Efficient Energy Use of FPGA for Underwater Sensor Network2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Operational time is becoming an increasingly important aspect in electronic devices and is also highly relevant in Underwater Acoustic Sensor Networks (UWSN). This thesis contains a study which explores what can be done to de-crease power consumption while maintaining the same functionality of an FPGA inside an underwater sensor-node network. A longer operational time means a more effective system since reconnaissance is one of UWSN’s area of application. The thesis will also cover the implementation of a new sensor-node ‘mode’ which will add new features and increase operational time.

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  • 241.
    Amin, Farooq ul
    Linköping University, Department of Electrical Engineering.
    On the Design of an Analog Front-End for an X-Ray Detector2009Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.

    A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.

    The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

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    On the Design of an Analog Front-End for an X-Ray Detector
  • 242.
    Amirijoo, Mehdi
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory.
    Brännström, Per
    Institutionen för datavetenskap Linköpings universitet.
    Hansson, Jörgen
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory.
    Gunnarsson, Svante
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Automatic Control.
    Son, Sang
    Department of Computer Science University of Virginia.
    Toward Adaptive Control of QoS-Importance Decoupled Real-Time Systems2007In: IEEE International Workshop on Feedback Control Implementation and Design in Computing Systems and Networks,2007, 2007Conference paper (Refereed)
    Abstract [en]

    This paper deals with differentiated services in real-time systems. Tasks submitted to a real-time system are differentiated with respect to importance and QoS requirements. We use feedback control to enforce the requirements in QoS and ensure a hierarchical admission policy based on the importance of the tasks. The results show that the requirements are met during steady state when the workload is constant. The feedback control approach does not satisfactorily manage QoS when there is a sudden and significant workload change (transient state) due to the time-variant nature of the system. To address this, we present preliminary and promising results using adaptive control, and report on some challenges we are facing when applying the theory.

  • 243.
    Amirijoo, Mehdi
    et al.
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Chaufette, Nicolas
    Hansson, Jörgen
    Software Engineering Institute, Carnegie Mellon University, USA.
    Son, Sang H.
    Dept. of Computer Science, University of Virginia, Charlottesville, USA.
    Gunnarsson, Svante
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Generalized performance management of multi-class real-time imprecise data services2005In: Real-Time Systems Symposium, 2005. RTSS 2005. 26th IEEE International, 2005, p. 12-49Conference paper (Other academic)
    Abstract [en]

    The intricacy of real-time data service management increases mainly due to the emergence of applications operating in open and unpredictable environments, increases in software complexity, and need for performance guarantees. In this paper we propose an approach for managing the quality of service of real-time databases that provide imprecise and differentiated services, and that operate in unpredictable environments. Transactions are classified into service classes according to their level of importance. Transactions within each service class are further classified into subclasses based on their quality of service requirements. In this way transactions are explicitly differentiated according to their importance and quality of service requests. The performance evaluation shows that during overloads the most important transactions are guaranteed to meet their deadlines and that reliable quality of service is provided even in the face of varying load and execution time estimation errors.

  • 244.
    Amirijoo, Mehdi
    et al.
    Ericsson AB, Sweden.
    Frenger, Pål
    Ericsson AB, Sweden.
    Gunnarsson, Fredrik
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Moe, Johan
    Ericsson AB, Sweden.
    Zetterberg, Kristina
    Ericsson AB, Sweden.
    On Self-Optimization of the Random Access Procedure in 3G Long Term Evolution2009In: Proceedings of the 11th IFIP/IEEE International Symposium on Integrated Network Management, IEEE , 2009Conference paper (Refereed)
    Abstract [en]

    Operationally efficient radio networks typically feature a high degree of self-organization. This means less planning efforts and manual intervention, and a potential for better radio resource utilization when network elements adapts its operation to the observed local conditions. The focus in this paper is selfoptimization of the random access channel (RACH) in the 3G Long Term Evolution (LTE). A comprehensive tutorial about the RACH procedure is provided to span the complexity of the selfoptimization. Moreover, the paper addresses RACH key performance metrics and appropriate modeling of the various steps and components of the procedure. Finally, some coupling between parameters and key performance metrics as well as selfoptimization examples are presented together with a feasibility discussion. The main ambition with this workshop paper is to present and define a relevant set of self-optimization problems, rather than to provide a complete solution.

  • 245.
    Amirijoo, Mehdi
    et al.
    Ericsson AB, Sweden.
    Frenger, Pål
    Ericsson AB, Sweden.
    Gunnarsson, Fredrik
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Moe, Johan
    Ericsson AB, Sweden.
    Zetterberg, Kristina
    Ericsson AB, Sweden.
    Towards Random Access Channel Self-Tuning in LTE2009In: Proceedings of the 69th IEEE Vehicular Technology Conference, 2009, p. 1-5Conference paper (Refereed)
    Abstract [en]

    Future radio access networks are expected to show a high degree of self-organization. This paper addresses self-tuning of the random access channel (RACH) in the 3G Long Term Evolution (LTE). The feasibility of self-tuning is investigated by means of simulation, where the coupling between several parameters and the performance of RACH is provided. The conclusion of the simulations is that RACH self-tuning is indeed possible given that UE assisted measurements are available for the self-tuning mechanism.

  • 246.
    Amirijoo, Mehdi
    et al.
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Gunnarsson, Svante
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Hansson, Jörgen
    Software Engineering Institute, Carnegie Mellon University, Pittsburgh, PA, USA.
    Son, Sang H.
    University of Virginia, USA.
    Quantifying and Suppressing the Measurement Disturbance in Feedback Controlled Real-Time Systems2008In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 40, no 1, p. 44-76Article in journal (Refereed)
    Abstract [en]

    In the control of continuous and physical systems, the controlled system is sampled sufficiently fast to capture the dynamics of the system. In general, this property cannot be applied to the control of computer systems as the measured variables are often computed over a data set, e.g., deadline miss ratio. In this paper we quantify the disturbance present in the measured variable as a function of the data set size and the sampling period, and we propose a feedback control structure that suppresses the measurement disturbance. The experiments we have carried out show that a controller using the proposed control structure outperforms a traditional control structure with regard to performance reliability.

  • 247.
    Amirijoo, Mehdi
    et al.
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Hansson, Jörgen
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Gunnarsson, Svante
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Son, Sang H.
    University of Virginia, VA, USA.
    Enhancing Feedback Control Scheduling Performance by On-line Quantification and Suppression of Measurement Disturbance2005In: Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium, 2005, p. 2-11Conference paper (Refereed)
    Abstract [en]

    In the control of continuous and physical systems, the controlled system is sampled sufficiently fast to capture the system dynamics. In general, this property cannot be applied to the control of computer systems as the measured variables are often computed over a data set, e.g., deadline miss ratio. In this paper we quantize the disturbance present in the measured variable as a function of the sampling period and we propose a measurement disturbance suppressive control structure. The experiments we have carried out show that a controller using the proposed control structure outperforms a traditional control structure with regard to performance reliability and adaptation.

  • 248.
    Amirijoo, Mehdi
    et al.
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Hansson, Jörgen
    Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory. Linköping University, The Institute of Technology.
    Son, Sang H.
    University of Virginia, USA.
    Gunnarsson, Svante
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Experimental Evaluation of Linear Time-Invariant Models for Feedback Performance Control in Real-Time Systems2007In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 35, no 3, p. 209-238Article in journal (Refereed)
    Abstract [en]

    In recent years a new class of soft real-time applications operating in unpredictable environments has emerged. Typical for these applications is that neither the resource requirements nor the arrival rates of service requests are known or available a priori. It has been shown that feedback control is very effective to support the specified performance of dynamic systems that are both resource insufficient and exhibit unpredictable workloads. To efficiently use feedback control scheduling it is necessary to have a model that adequately describes the behavior of the system. In this paper we experimentally evaluate the accuracy of four linear time-invariant models used in the design of feedback controllers. We introduce a model (DYN) that captures additional system dynamics, which a previously published model (STA) fails to include. The accuracy of the models are evaluated by validating the models with regard to measured data from the controlled system and through a set of experiments where we evaluate the performance of a set of feedback control schedulers tuned using these models. From our evaluations we conclude that second order models (e.g., DYN) are more accurate than first order models (e.g. STA). Further we show that controllers tuned using second order models perform better than controllers tuned using first order models.

  • 249.
    Amlinger, Hanna
    Linköping University, Department of Electrical Engineering.
    Application of a New Software Tool for the Automated Test of Automotive Electronic Control Unit Software2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Testing plays a very important role for assuring the quality of developed software. In a modern vehicle, more and more of the functionality is controlled by software and the complexity of the software always increases. The expectations on automating the testing process are to save time and to reach an even higher quality.

    In this thesis, which was performed at ZF Friedrichshafen AG, a new tool for automated tests is studied. The tool is used for software in the loop simulation based system tests. The user specifies which outputs that shall be observed and which inputs that can be controlled. Based on these prerequisites, test cases are generated.

    It has been studied how to apply the tool, how the test case generation can be influenced, on which systems it successfully could be used and which results that could be reached with the tool. The tool has been evaluated on the hand of two real-life examples; the software of an automatic transmission and of a pressure controller, a module of this software. It was found that there are many interesting possibilities to apply the tool in order to support the present testing process.

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    FULLTEXT01
  • 250.
    Amselem, E.
    et al.
    Department of Physics, Stockholm University, Sweden .
    Bourennane, M.
    Department of Physics, Stockholm University, Stockholm University, Sweden .
    Budroni, C.
    Naturwissenschaftlich-Technische Fakultät, Universität Siegen, Germany .
    Cabello, A.
    Departamento de Física Aplicada II, Universidad de Sevilla, Spain .
    Guehne, O.
    Naturwissenschaftlich-Technische Fakultät, Universität Siegen, Germany .
    Kleinmann, M.
    Naturwissenschaftlich-Technische Fakultät, Universität Siegen, Germany .
    Larsson, Jan-Åke
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    Wiesniak, M.
    Institute of Theoretical Physics and Astrophysics, University of Gdańsk, Poland .
    Editorial Material: Comment on "State-Independent Experimental Test of Quantum Contextuality"2013In: Physical Review Letters, ISSN 0031-9007, E-ISSN 1079-7114, Vol. 110, no 7, p. 1-1Article in journal (Other academic)
    Abstract [en]

    In this Comment we argue that the experiment describedin the recent Letter does not allow one to make con-clusions about contextuality. Our main criticism is that themeasurement of the observables as well as the preparationof the state manifestly depend on the chosen context.Contrary to that, contextuality is about the behavior ofthesamemeasurement device in different experimentalcontexts.

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    Comment on "State-Independent Experimental Test of Quantum Contextuality
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