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  • 201.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Ronny
    Ericsson Microelectronics.
    Norling, Fredrik
    Ericsson Microelectronics.
    Full digital driving voice and audio load on an IC2002Inngår i: International Conference of Communications, Circuits and Systems,2002, 2002Konferansepaper (Fagfellevurdert)
  • 202.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Configuration-based architecture for high speed and general-purpose protocol processing1999Inngår i: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, s. 540-547Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

  • 203.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Olausson, Mikael
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    The ADSP-21535 Blackfin and speech coding2003Inngår i: Swedish System-on-Chip Conference SSoCC,2003, 2003Konferansepaper (Annet vitenskapelig)
  • 204.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Sohl, Joar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Parallel Programming and its architectures Based on data access separated algorithm Kernels2010Inngår i: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, E-ISSN 1947-3184, Vol. 1, nr 1, s. 65-85Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing. Copyright © 2010, IGI Global.

  • 205.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Hardware Architecture for a Multi Mode Block Interleaver2004Inngår i: International Conference on Circuits and Systems for Communications, ICCSC,2004, 2004Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We are interested in developing a programmable baseband processor for software defined radio and are trying to find configurable hardware blocks that can be used in multiple radio standards, including for example wireless LAN and 3G standards. This paper suggests an architecture for a multi mode block interleaver that is suitable e.g. for the IEEE 802.11a and 802.11g standards. Our implementation is based on a special matrix memory to which data is written as rows but read out as columns. To enable a comparison, an interleaver for theWireless LAN standard 802.11a has been implemented both using our suggested architecture and using a traditional interleaver implementation based on a bit memory. Our implementation reaches a significantly higher performance and a lower power consumption with no extra area. The price to pay is a small loss of generality.

  • 206.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Low-Power Baseband Processors for Communications2004Inngår i: Low-Power Electronics Design / [ed] Christian Piguet, CRC Press , 2004, 1, s. -912Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management. The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now.

  • 207.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implemenation of Programmable Baseband Processors2004Inngår i: CCIC,2004, 2004Konferansepaper (Fagfellevurdert)
  • 208.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Söderquist, Ingemar
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Fully flexible baseband DSP processors for future SDR/JTRS2005Inngår i: Western European Armaments Organization WEAO,2005, 2005Konferansepaper (Annet vitenskapelig)
  • 209.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Wang, Zhihua
    Tsinghua Univ, Elect Engn, Beijing, Peoples R China.
    Luo, Li
    BJTU, Beijing, Peoples R China.
    Editorial Material: SPECIAL ISSUE ON COMMUNICATION IC in CHINA COMMUNICATIONS, vol 12, issue 5, pp III-VI2015Inngår i: China Communications, ISSN 1673-5447, Vol. 12, nr 5, s. III-VIArtikkel i tidsskrift (Annet vitenskapelig)
    Abstract [en]

    n/a

  • 210.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Seger, Olle
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Sathe, Sumant
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Svensson, Erik
    SoC BUS: The solution of high communication bandwidth on chip and short TTM2002Inngår i: Real Time and Embedded Computing Conference,2002, 2002Konferansepaper (Fagfellevurdert)
  • 211.
    Lundkvist, Herman
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Yngve, Alexander
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Accelerated Simulation of Modelica Models Using an FPGA-Based Approach2018Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    This thesis presents Monza, a system for accelerating the simulation of modelsof physical systems described by ordinary differential equations, using a generalpurpose computer with a PCIe FPGA expansion card. The system allows bothautomatic generation of an FPGA implementation from a model described in theModelica programming language, and simulation of said system.Monza accomplishes this by using a customizable hardware architecture forthe FPGA, consisting of a variable number of simple processing elements. A cus-tom compiler, also developed in this thesis, tailors and programs the architectureto run a specific model of a physical system.Testing was done on two test models, a water tank system and a Weibel-lung,with up to several thousand state variables. The resulting system is several timesfaster for smaller models and somewhat slower for larger models compared to aCPU. The conclusion is that the developed hardware architecture and softwaretoolchain is a feasible way of accelerating model execution, but more work isneeded to ensure faster execution at all times.

  • 212.
    Löfström, Daniel
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Comparison of High Speed Vision Communication Standards2015Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Future development in high performance cameras and machine vision applications results in a need for faster vision communication standards. This thesis compares four high speed vision communication standards on the machine vision market. The standards considered are CoaXPress, GigE Vision over 10 Gigabit Ethernet, Camera Link HS and USB3 Vision, all which are capable of higher speeds than their forerunners. The standards are compared in general based on the theory available and with the help of the voting systems Borda count and the Kemeny-Young method. From the result of the general comparison two of the standards are chosen, CoaXPress and 10 GigE Vision, for an in depth comparison. The vision communication standards are tested on a Xilinx ZC706 development board for the Zynq-7000 SoC where resource allocation and power consumption are measured. The thesis gives an overview of the performance of the standards and with no obvious winner the voting system gives an unbiased comparison of the standards with interesting results.

  • 213.
    Magnus, Vestergren
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Automatic Takeoff and Landing of Unmanned Fixed Wing Aircrafts: A Systems Engineering Approach2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The purpose of this thesis is to extend an existing autopilot with automatic takeoff and landing algorithms for small fixed wing unmanned aircrafts. The work has been done from a systems engineering perspective and as for solution candidates this thesis has a bias towards solutions utilizing fuzzy logic. The coveted promises of fuzzy logic was primarily the idea to have a design that was easily tunable with very little knowledge beyond flight experience for a particular aircraft. The systems engineering perspective provided a way to structure and reason about the project where the problem has been decoupled from different solutions and the work has been divided in a way that would allow multiple aspects of the project to be pursued simultaneously. Though the fuzzy logic controllers delivered functional solutions the promises related to ease of tuning was not fulfilled in a landing context. This might have been a consequence of the designs attempted but in the end a simpler solution outperformed the implemented fuzzy logic controllers. Takeoff did not present the same issues in tuning but did require some special care to handle the initial low airspeeds in an hand launch.

  • 214.
    Magnusson, Maria
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Bildbehandling.
    Danielsson, Per-Erik
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Bildbehandling.
    Sunnegårdh, Johan
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Handling of Long Objects in Iterative Improvement of Non-Exact Reconstruction in Helical Cone-Beam CT2006Inngår i: IEEE Transactions on Medical Imaging, ISSN 0278-0062, E-ISSN 1558-254X, Vol. 25, nr 7, s. 935-940Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

     In medical helical cone-beam CT, it is common that the region-of-interest (ROI) is contained inside the helix cylinder, while the complete object is long and extends outside the top and the bottom of the cylinder. This is the Long Object Problem. Analytical reconstruction methods for helical cone-beam CT have been designed to handle this problem. It has been shown that a moderate amount of over-scanning is sufficient for reconstruction of a certain ROI. The over-scanning projection rays travel both through the ROI as well as outside the ROI. This is unfortunate for iterative methods since it seems impossible to compute accurate values for the projection rays which travel partly inside and partly outside the ROI. Therefore, it seems that the useful ROI will diminish for every iteration step. We propose the following solution to the problem. Firstly, we reconstruct volume regions also outside the ROI. These volume regions will certainly be incompletely reconstructed, but our experimental results show that they serve well for projection generation. This is rather counter-intuitive and contradictory to our initial assumptions. Secondly, we use careful extrapolation and masking of projection data. This is not a general necessity, but needed for the chosen iterative algorithm, which includes rebinning and iterative filtered backprojection. Our idea here was to use an approximate reconstruction method which gives cone-beam artifacts and then improve the reconstructed result by iterative filtered backprojection. The experimental results seem very encouraging. The cone-beam artifacts can indeed be removed. Even voxels close to the boundary of the ROI are as well enhanced by the iterative loop as those in the middle of the ROI.

  • 215.
    Mansour, Imene
    et al.
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska fakulteten.
    Frisk, Erik
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska fakulteten.
    Jemni, Adel
    Preparatory Inst Engn Studies Monastir, Tunisia.
    Krysander, Mattias
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Liouane, Noureddine
    Natl Engn Sch Monastir, Tunisia.
    State of Charge Estimation Accuracy in Charge Sustainable Mode of Hybrid Electric Vehicles2017Inngår i: IFAC PAPERSONLINE, ELSEVIER SCIENCE BV , 2017, Vol. 50, nr 1, s. 2158-2163Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The charge sustaining mode of a hybrid electric vehicle maintains the state of charge of the battery within a predetermined narrow band. Due to the poor system observability in this range, the state of charge estimation is tricky, and inadequate prior knowledge of the system uncertainties could lead to deterioration and divergence of estimates. In this paper, a comparative study of three estimators tuned based on the noise covariance matching technique is established in order to analyze their robustness in the state of charge estimation. Simulation results show a significant enhancement of filter accuracy using this adaptation. The adaptive particle filter has the best estimation results but it is vulnerable to model parameter uncertainties, further it is time consuming. On the other hand, the adaptive Unscented Kalman filter and the adaptive Extended Kalman filter show enough estimation accuracy, robustness for model uncertainty, and simplicity of implementation. (C) 2017, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

  • 216.
    Meher, Pramod Kumar
    et al.
    Independent Hardware Consultant.
    Chang, Chip-Hong
    Nanyang Technological University, Singapore, Singapore.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Vinod, A.P.
    Nanyang Technological University, Singapore, Singapore.
    Faust, Mattias
    mfnet gmbh, Switzerland.
    Shift‐Add Circuits for Constant Multiplications2017Inngår i: Arithmetic Circuits for DSP Applications / [ed] Pramod Kumar Meher, Thanos Stouraitis, John Wiley & Sons, 2017, s. 33-76Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    The optimization of shift‐and‐add network for constant multiplications is found to have great potential for reducing the area, delay, and power consumption of implementation of multiplications in several computation‐intensive applications not only in dedicated hardware but also in programmable computing systems. To simplify the shift‐and‐add network in single constant multiplication (SCM) circuits, this chapter discusses three design approaches, including direct simplification from a given number representation, simplification by redundant signed digit (SD) representation, and simplification by adder graph. Examples of the multiple constant multiplication (MCM) methods are constant matrix multiplication, discrete cosine transform (DCT) or fast Fourier transform (FFT), and polyphase finite impulse response (FIR) filters and filter banks. The given constant multiplication methods can be used for matrix multiplications and inner‐product; and can be applied easily to image/video processing and graphics applications. The chapter further discusses some of the shortcomings in the current research on constant multiplications, and possible scopes of improvement.

  • 217.
    Mellqvist, Tobias
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Kanders, Hans
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    One Million-Point FFT2018Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The goal of this thesis has been to implement a hardware architecture for FPGA that calculates the fast Fourier transform (FFT) of a signal using one million samples. The FFT has been designed using a single-delay feedback architecture withrotators and butterflies, including a three-stage rotator with one million rotation angles. The design has been implemented onto a single FPGA and has a throughput of 233 Msamples/s. The calculated FFT has high accuracy with a signal to quantization noise ratio (SQNR) of 95.6 dB.

  • 218.
    Moeller, Konrad
    et al.
    Univ Kassel, Germany.
    Kumm, Martin
    Univ Kassel, Germany.
    Garrido Gálvez, Mario
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Zipf, Peter
    Univ Kassel, Germany.
    Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits2018Inngår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, nr 3, s. 710-714Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a new method called optimal shift reassignment (OSR), used for reconfigurable multiplication circuits. These circuits consist of adders, subtractors, shifts, and multiplexers (MUXs). They calculate the multiplication of an input number by one out of several constants which can be selected dynamically during run-time. The OSR method is based on the idea that shifts can be placed at different positions along the circuit, while the calculated output constant stays the same. This differs from previous approaches, which were limited by the fact that all constants within the constant multiplier were forced to be odd. The OSR method subsequently releases this restriction. As a result, the number of required MUXs in the circuit can be reduced. This happens when the shift reassignment aligns the shift values of different inputs of an MUX. Experimental results show MUX savings of up to 50% and average savings between 11% and 16% using the OSR method compared to previous approaches.

  • 219.
    Mohammadi Sarband, Narges
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Garrido, Mario
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication2018Inngår i: PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), IEEE, Institute of Electrical and Electronics Engineers (IEEE), 2018, s. 134-139Konferansepaper (Fagfellevurdert)
    Abstract [sv]

    In this work, an approach for transposing solutions to the multiple constant multiplication (MCM) problem to obtain a sum of product (SOP) computation with minimum depth is proposed. The reason for doing this is that solving the SOP problem directly is highly computationally intensive when adder graph algorithms are used. Compared to using subexpression sharing algorithms, which has a lower computational complexity, directly for the SOP problem, it is shown that the proposed approach, as expected, results in lower complexity for the SOP. It is also shown that there is no obvious way to construct the MCM solution in such a way that the SOP solution has the minimum theoretical depth. However, the proposed approach guarantees minimum depth subject to the MCM solution given as input.

  • 220.
    Mollberg, Alexander
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Resource-Efficient and High-Performance Implementation of Object Tracking on a Programmable System-on-Chip2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development process. A system for interest point based object tracking that uses FAST for feature detection and BRIEF for feature description with the proposed smoothing modification is implemented on the FPGA. The design is described and important design choices are discussed.

  • 221.
    Murugesan, Somasekar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Benchmarking of Sleipnir DSP Processor, ePUMA Platform2011Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Choosing a right processor for an embedded application, or designing a new pro-cessor requires us to know how it stacks up against the competition, or sellinga processor requires a credible communication about its performance to the cus-tomers, which means benchmarking of a processor is very important. They arerecognized world wide by processor vendors and customers alike as the fact-basedway to evaluate and communicate embedded processor performance. In this the-sis, the benchmarking of ePUMA multiprocessor developed by the Division ofComputer Engineering, ISY, Linköping University, Sweden will be described indetails. A number of typical digital signal processing algorithms are chosen asbenchmarks. These benchmarks have been implemented in assembly code withtheir performance measured in terms of clock cycles and root mean square errorwhen compared with result computed using double precision. The ePUMA multi-processor platform which comprises of the Sleipnir DSP processor and Senior DSPprocessor was used to implement the DSP algorithms. Matlab inbuilt models wereused as reference to compare with the assembly implementation to derive the rootmean square error values of different algorithms. The execution time for differentDSP algorithms ranged from 51 to 6148 clock cycles and the root mean squareerror values varies between 0.0003 to 0.11.

  • 222.
    Nielsen, Emil
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Performance Evaluation of an easily retargeted C compiler using the LLVM framework2015Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    When considering processor architectures (either existing ones or when developing new ones), native code for functional testing and performance evaluation will generally be required. In theory, the work load involved in developing such code can be alleviated by compiling existing test cases written in a higher level language.

    This thesis focuses on evaluating the feasibility of this approach by developing a basic C compiler using the LLVM framework and porting it to a number of architectures, finishing by comparing the performance of the compiled code with existing results obtained using the CoreMark benchmark. The resulting comparison can serve as a guideline when deciding which approach to choose when taking on a new architecture. The developed compiler and its back end ports can also serve as reference implementations.

    While not conclusive, the final results indicate that the approach is highly feasible for certain applications on certain architectures.

  • 223.
    Nilsson, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design of multi-standard baseband processors2005Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. The ever changing wireless network industry also requires flexible and versatile baseband processors to be able to adapt quickly to new and updated standards. The convergence of mobile communication devices and systems require multi-standard capabilities in the processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM, CDMA and single carrier modulation with the same processing device. All this requires a programmable baseband processor because a pure fixed-function ASIC solution is not flexible enough. Furthermore, ASIC solutions for multi-standard baseband processing are less area efficient than their programmable counterparts since processing resources cannot efficiently be shared between different operations and standards. This project was initiated for the above mentioned reason as a continuation of a previous baseband processor project at the research group. Accordingly, this thesis is devoted to the design of area efficient, low clock rate, fully programmable baseband processors. A reduction of the clock rate will simplify the design of the processor as well as save power in the application. Since most multi-standard processing devices will be used in a mobile environment, low power is essential. Normally, extra computing resources must be added to a system designed for low clock rate operation compared to a regular solution, resulting in a higher area and complexity of the chip. In this project effort has been made to create efficient base architectures maintaining a low area and clock rate while also maintaining flexibility and processing capability. At the same time design methods for the required DSP execution units within the processor have been developed.

    Usually general baseband processing includes many tasks such as error control coding/ decoding, interleaving, scrambling etc, however in this thesis because of time and resource limitations, the focus is on the symbol related processing, although the bit manipulation and forward error correction tasks are also studied regarding acceleration.

    Delarbeid
    1. An accelerator structure for programmable multi-standard baseband processors
    Åpne denne publikasjonen i ny fane eller vindu >>An accelerator structure for programmable multi-standard baseband processors
    2004 (engelsk)Inngår i: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, s. 644-649Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-14525 (URN)0-88986-403-9 (ISBN)
    Konferanse
    Wireless Networks and Emerging Technologies(WNET 2004) July 8 – 10, 2004. Banff, Canada.
    Tilgjengelig fra: 2007-05-22 Laget: 2007-05-22 Sist oppdatert: 2013-11-06
    2. A fully programmable Rake-receiver architecture for multi-standard baseband processors
    Åpne denne publikasjonen i ny fane eller vindu >>A fully programmable Rake-receiver architecture for multi-standard baseband processors
    2005 (engelsk)Inngår i: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, s. 292-297Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

    Emneord
    CDMA, Rake, MRC, DSP, SDR
    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-14524 (URN)
    Konferanse
    The Intl. conference on Networks and Communication systems, NCS2005. Krabi, Thailand 2005.
    Tilgjengelig fra: 2007-05-22 Laget: 2007-05-22 Sist oppdatert: 2013-11-06
    3. Design methodology for memory-efficient multi-standard baseband processors
    Åpne denne publikasjonen i ny fane eller vindu >>Design methodology for memory-efficient multi-standard baseband processors
    2005 (engelsk)Inngår i: Asia Pacific Communication Conference, Perth, Australia, 2005, s. 28-32Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-14522 (URN)10.1109/APCC.2005.1554012 (DOI)0-7803-9132-2 (ISBN)
    Konferanse
    2005 Asia-Pacific Conference on Communications (APCC). 3-5 October, 2005. Perth, Australia.
    Tilgjengelig fra: 2007-05-22 Laget: 2007-05-22 Sist oppdatert: 2013-11-06
  • 224.
    Nilsson, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design of programmable multi-standard baseband processors2007Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated.

    In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures.

    A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.

  • 225.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Area efficient fully programmable baseband processors2007Inngår i: SAMOSVII Workshop; SAMOS, Greece, July 16-19, 2007Konferansepaper (Fagfellevurdert)
  • 226.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Multi-standard support in SIMT programmable baseband processors2006Inngår i: SSoCC Swedish System-on-chip Conference,2006, 2006Konferansepaper (Annet vitenskapelig)
  • 227.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Processor friendly peak-to-average reduction in multi-carrier systems2004Inngår i: Swedish system-on-Chip Conference, SSoCC 04,2004, 2004Konferansepaper (Annet vitenskapelig)
  • 228.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    A fully programmable Rake-receiver architecture for multi-standard baseband processors2005Inngår i: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, s. 292-297Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

  • 229.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    A Programmable SIMD-based Multi-standard Rake Receiver Architecture2005Inngår i: European Signal Processing Conference, EUSIPCO, Antalya, Turkey, 2005Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability with its associated flexibility will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and MRC-based channel equalization for several CDMA-based wireless transmission systems in software. Our processor is based on a DSP core with SIMD-computing clusters. We have mapped Rake receiver kernel-functions supporting several 3G standards to this micro-architecture and benchmarking shows that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA FDD/TDD-modes and HSDPA at clock rate not exceeding 76 MHz during soft handover conditions.

  • 230.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Acceleration in multi-standard baseband processors2005Inngår i: Radiovetenskap och Kommunikation,2005, 2005Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an architecture for fully programmable baseband processing, based on a programmable DSP processor and a number of configurable accelerators which communicate via a configurable network. Acceleration of common cycleconsuming DSP jobs is necessary in order to manage wide-band modulation schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband processor supporting a number of common Wireless LAN and 3G standards. Benchmarking show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 231.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    An 11 mm(2), 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12 mu m CMOS2009Inngår i: IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA: Vol 44, number 1, IEEE , 2009, Vol. 44, nr 1, s. 90-97Konferansepaper (Fagfellevurdert)
    Abstract [en]

    With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm(2) in a 0.12 mu m CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.

  • 232.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    An accelerator structure for programmable multi-standard baseband processors2004Inngår i: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, s. 644-649Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 233.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Simultaneous multistandard support in programmable baseband processors2006Inngår i: Proceedings of IEEE PRIME 2006, Otranto, Italy, 2006Konferansepaper (Fagfellevurdert)
  • 234.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wiklund, Daniel
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design methodology for memory-efficient multi-standard baseband processors2005Inngår i: Asia Pacific Communication Conference, Perth, Australia, 2005, s. 28-32Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.

  • 235.
    Nilsson, Emelie
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    DMA Controller for LEON3 SoC:s Using AMBA2013Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    A DMA Controller can offload a processor tremendously. A memory copy operation can be initiated by the processor and while the processor executes others tasks the memory copy can be fulfilled by the DMA Controller.

    An implementation of a DMA Controller for use in LEON3 SoC:s has been made during this master thesis. Problems that occurred while designing a controller of this type concerned AMBA buses, data transfers, alignment and interrupt handling.

    The DMA Controller supports AMBA and is attached to an AHB master and APB slave. The DMA Controller supports burst transfers to maximize data bandwidth. The source and destination address can be arbitrarily aligned. It supports multiple channels and it has interrupt generation on transfer completion along with interrupt masking.

    The implemented functionality works as intended. 

  • 236.
    Nilsson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska högskolan.
    Nyberg, Peter
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska högskolan.
    Sundström, Christofer
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska högskolan.
    Frisk, Erik
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska högskolan.
    Krysander, Mattias
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Robust Driving Pattern Detection and Identification with a Wheel Loader Application2014Inngår i: International journal of vehicle systems modelling and testing, ISSN 1745-6436, Vol. 9, nr 1, s. 56-76Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Information about wheel loader usage can be used in several ways to optimize customer adaption. First, optimizing the configuration and component sizing of a wheel loader to customer needs can lead to a significant improvement in e.g. fuel efficiency and cost. Second, relevant driving cycles to be used in the development of wheel loaders can be extracted from usage data. Third, on-line usage identification opens up for the possibility of implementing advanced look-ahead control strategies for wheel loader operation. The main objective here is to develop an on-line algorithm that automatically, using production sensors only, can extract information about the usage of a machine. Two main challenges are that sensors are not located with respect to this task and that significant usage disturbances typically occur during operation. The proposed method is based on a combination of several individually simple techniques using signal processing, state automaton techniques, and parameter estimation algorithms. The approach is found to berobust when evaluated on measured data of wheel loaders loading gravel and shot rock.

  • 237.
    Nordmark, Oskar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Turbo Code Performance Analysis Using Hardware Acceleration2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The upcoming 5G mobile communications system promises to enable use cases requiring ultra-reliable and low latency communications. Researchers therefore require more detailed information about aspects such as channel coding performance at very low block error rates. The simulations needed to obtain such results are very time consuming and this poses achallenge to studying the problem. This thesis investigates the use of hardware acceleration for performing fast simulations of turbo code performance. Special interest is taken in investigating different methods for generating normally distributed noise based on pseudorandom number generator algorithms executed in DSP:s. A comparison is also done regarding how well different simulator program structures utilize the hardware. Results show that even a simple program for utilizing parallel DSP:s can achieve good usage of hardware accelerators and enable fast simulations. It is also shown that for the studied process the bottleneck is the conversion of hard bits to soft bits with addition of normally distributed noise. It is indicated that methods for noise generation which do not adhere to a true normal distribution can further speed up this process and yet yield simulation quality comparable to methods adhering to a true Gaussian distribution. Overall, it is show that the proposed use of hardware acceleration in combination with the DSP software simulator program can in a reasonable time frame generate results for turbo code performance at block error rates as low as 10−9.

  • 238.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    A Programmable Network Interface Accelerator2003Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

    In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

    A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

    The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

    Delarbeid
    1. Configuration-based architecture for high speed and general-purpose protocol processing
    Åpne denne publikasjonen i ny fane eller vindu >>Configuration-based architecture for high speed and general-purpose protocol processing
    1999 (engelsk)Inngår i: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, s. 540-547Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100980 (URN)10.1109/SIPS.1999.822360 (DOI)
    Konferanse
    SIPS 1999, 20-22 October. Taipei, Taiwan
    Tilgjengelig fra: 2013-11-15 Laget: 2013-11-15 Sist oppdatert: 2013-11-15
    2. CRC generation for protocol processing
    Åpne denne publikasjonen i ny fane eller vindu >>CRC generation for protocol processing
    2000 (engelsk)Inngår i: Proceedings of NORCHIP 2000, 2000, s. 288-293Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-100981 (URN)
    Konferanse
    18th NORCHIP Conference, 6-7 November, 2000, Turku, Finland
    Tilgjengelig fra: 2013-11-15 Laget: 2013-11-15 Sist oppdatert: 2014-12-19
    3. Packet Classification and Termination in a Protocol Processor
    Åpne denne publikasjonen i ny fane eller vindu >>Packet Classification and Termination in a Protocol Processor
    2003 (engelsk)Konferansepaper, Publicerat paper (Annet vitenskapelig)
    Abstract [en]

    This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33275 (URN)19275 (Lokal ID)19275 (Arkivnummer)19275 (OAI)
    Konferanse
    Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-15
  • 239.
    Nordqvist, Ulf
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Power Efficient Packer Buffering in a Protocol Processor2003Inngår i: Swedish System-onChip Conference,2003, 2003Konferansepaper (Annet vitenskapelig)
  • 240.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Configurable CRC Generator2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 192-Konferansepaper (Fagfellevurdert)
  • 241.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    CRC generation for protocol processing2000Inngår i: Proceedings of NORCHIP 2000, 2000, s. 288-293Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

  • 242.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Comparative Study of Protocol Processors2002Inngår i: Conference on Computer Science and Systems Engineering,2002, 2002, s. 107-Konferansepaper (Fagfellevurdert)
  • 243.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Control path in a protocol processor2003Inngår i: Midwest symposium on circuits and systems MWCAS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 244.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Packet Classification and Termination in a Protocol Processor2003Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

  • 245.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Packet classification and termination in a protocol processor2003Inngår i: Network processor design - Issues and practices, vol 2 / [ed] Mark A. Franklin, Patrick Crowley , Haldun Hadimioglu, Peter Z. Onufryk, Elsevier , 2003, 1, s. 159-180Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. ·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

  • 246.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Power optimized packet buffering in a protocol processor2003Inngår i: International conference on electronic circuits and systems, ICECS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 247.
    Odelberg, David
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Holm, Carl Rasmus
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Distributed cipher chaining for increased security in password storage2014Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    As more services move on to the web and more people use the cloud for storage of important information, it is important that providers of such services can guarantee that information is kept safe. The most common way of protecting that data is to make it impossible to access without being authenticated as the user owning the data. The most common way for a user to authenticate and thereby becoming authorized to access the data, or service, is by making use of a password. The one trying to safeguard that password must make sure that it is not easy to come by for someone trying to attack the system. The most common way to store a password is by first running that password through a one way function, known as a hash function, that obfuscates it into something that does not at all look related to the password itself. Whenever a user tries to authenticate, they type in their password and it goes through the same function and the results are compared. While this model makes sure that the password is not stored in plain text it contains no way of taking action in case the database of hashed passwords is leaked. Knowing that it is nearly impossible to be fully protected from malevolent users, the ones trying to safe guard information always need to try to make sure that it is difficult to extract information about users' passwords. Since the 70s the password storage has to a large extent looked the same. What is researched and implemented in this thesis is a different way of handling passwords, where the main focus is on making sure there are countermeasures in case the database leaks. The model described and implemented consist of software that make use of the current best practices, with the addition of encrypting the passwords with a symmetric cipher. This is all done in a distributed way to move towards a paradigm where a service provider does not need to rely on one point of security. The end result of this work is a working proof-of-concept software that runs in a distributed manner to derive users' passwords to an obfuscated form. The system is at least as secure as best current practice for storing users passwords but introduces the notion of countermeasures once information has found its way into an adversary's hands.

  • 248.
    Ogniewski, Jens
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Ragnemalm, Ingemar
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    TEXTURE COMPRESSION IN MEMORY AND PERFORMANCE-CONSTRAINED EMBEDDED SYSTEMS2011Inngår i: Computer Graphics, Visualization, Computer Vision and Image Processing 2011 / [ed] Yingcai Xiao, 2011, s. 19-26Konferansepaper (Fagfellevurdert)
    Abstract [en]

    More embedded systems gain increasing multimedia capabilities, including computer graphics. Although this is mainly due to their increasing computational capability, optimizations of algorithms and data structures are important as well, since these systems have to fulfill a variety of constraints and cannot be geared solely towards performance. In this paper, the two most popular texture compression methods (DXT1 and PVRTC) are compared in both image quality and decoding performance aspects. For this, both have been ported to the ePUMA platform which is used as an example of energy consumption optimized embedded systems. Furthermore, a new DXT1 encoder has been developed which reaches higher image quality than existing encoders.

  • 249.
    Olausson, Mikael
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Hardware for speech and audio coding2004Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    While the Micro Processors (MPUs) as a general purpose CPU are converging (into Intel Pentium), the DSP processors are diverging. In 1995, approximately 50% of the DSP processors on the market were general purpose processors, but last year only 15% were general purpose DSP processors on the market. The reason general purpose DSP processors fall short to the application specific DSP processors is that most users want to achieve highest performance under minimized power consumption and minimized silicon costs. Therefore, a DSP processor must be an Application Specific Instruction set Processor (ASIP) for a group of domain specific applications.

    An essential feature of the ASIP is its functional acceleration on instruction level, which gives the specific instruction set architecture for a group of applications. Hardware acceleration for digital signal processing in DSP processors is essential to enhance the performance while keeping enough flexibility. In the last 20 years, researchers and DSP semiconductor companies have been working on different kinds of accelerations for digital signal processing. The trade-off between the performance and the flexibility is always an interesting question because all DSP algorithms are "application specific"; the acceleration for audio may not be suitable for the acceleration of baseband signal processing. Even within the same domain, for example speech CODEC (COder/DECoder), the acceleration for communication infrastructure is different from the acceleration for terminals.

    Benchmarks are good parameters when evaluating a processor or a computing platform, but for domain specific algorithms, such as audio and speech CODEC, they are not enough. The solution here is to profile the algorithm and from the resulting statistics make the decisions. The statistics also suggest where to start optimizing the implementation of the algorithm. The statistics from the profi ling has been used to improve implementations of speech and audio coding algorithms, both in terms of the cycle cost and for memory efficiency, i.e. code and data memory.

    In this thesis, we focus on designing memory efficient DSP processors based on instruction level acceleration methods and data type optimization techniques. Four major areas have been attacked in order to speed up execution and reduce memory The first one is instruction level acceleration, where consecutive instructions appear frequently and are merged together. By this merge the code memory size is reduced and execution becomes faster. Secondly, complex addressing schemes are solved by acceleration for address calculations, i.e. dedicated hardware are used for address calculations. The third area, data storage and precision, is speeded up by using a reduced floating point scheme. The number of bits is reduced compared to the normal IEEE 754 floating point standard. The result is a lower data memory requirement, yet enough precision for the application; an mp3 decoder. The fourth contribution is a compact way of storing data in a general CPU. By adding two custom instructions, one load and one store, the data memory efficiency can be improved without making the firmware complex. We have tried to make application specific instruction sets and processors and also tried to improve processors based on an available instruction set.

    Experiences from this thesis can be used for DSP design for audio and speech applications. They can additionally be used as a reference to a general DSP processor design methodology.

    Delarbeid
    1. Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.729
    Åpne denne publikasjonen i ny fane eller vindu >>Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.729
    2001 (engelsk)Inngår i: Proceedings of the 1st IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2001, s. 34-39Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    This paper makes accelerations on instruction level based on the three speech coding algorithms G.723.1, 6.3 kbit/s and 5.3 kbit/s and G.729 8 kbit/s with hardware implementation. All these three algorithms are proposed by the H.323 standard together with G.711 64 kbit/s and G.728 16 kbit/s. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions [I], [2]. Three hardware structures are proposed to increase the performance.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33605 (URN)19639 (Lokal ID)19639 (Arkivnummer)19639 (OAI)
    Konferanse
    The 1st IEEE International Symposium on Signal Processing and Information Technology, December 28-30, 2001, Cairo, Egypt
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-26
    2. Instruction and hardware acceleration for MP-MLQ in G.723.1
    Åpne denne publikasjonen i ny fane eller vindu >>Instruction and hardware acceleration for MP-MLQ in G.723.1
    2002 (engelsk)Inngår i: IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02)., 2002, s. 235-239Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-33543 (URN)10.1109/SIPS.2002.1049715 (DOI)19568 (Lokal ID)0-7803-7587-4 (ISBN)19568 (Arkivnummer)19568 (OAI)
    Konferanse
    IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02). San Diego, California, USA. October 16-18, 2002.
    Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-26
    3. Reduced floating point for MPEG1/2 layer III decoding
    Åpne denne publikasjonen i ny fane eller vindu >>Reduced floating point for MPEG1/2 layer III decoding
    2004 (engelsk)Inngår i: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, s. V-209-12 vol.5-Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-24100 (URN)10.1109/ICASSP.2004.1327084 (DOI)3672 (Lokal ID)0-7803-8484-9 (ISBN)3672 (Arkivnummer)3672 (OAI)
    Konferanse
    International Conference on Acoustics, Speech and Signal Processing (ICASSP'04). Montreal, Quebec, Canada. May 17-21 2004.
    Tilgjengelig fra: 2009-10-07 Laget: 2009-10-07 Sist oppdatert: 2015-02-18
    4. Bit memory instructions for a general CPU
    Åpne denne publikasjonen i ny fane eller vindu >>Bit memory instructions for a general CPU
    2004 (engelsk)Inngår i: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, s. 215-218Konferansepaper, Publicerat paper (Fagfellevurdert)
    Abstract [en]

    Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

    HSV kategori
    Identifikatorer
    urn:nbn:se:liu:diva-102009 (URN)10.1109/IWSOC.2004.1319881 (DOI)0-7695-2182-7 (ISBN)
    Konferanse
    The 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04). Banff, Alberta, Canada. July 19-21 2004.
    Tilgjengelig fra: 2013-11-26 Laget: 2013-11-26 Sist oppdatert: 2013-11-26
  • 250.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Edman, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Bit memory instructions for a general CPU2004Inngår i: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, s. 215-218Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

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