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  • 251.
    Jalili, Armin
    et al.
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Sayedi, Sayed Masoud
    Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs2011In: Microelectronics Journal, ISSN 0959-8324, Vol. 42, no 1, p. 158-164Article in journal (Refereed)
    Abstract [en]

    This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18‐μm CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels.

    Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.

  • 252.
    Janson, Robert
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Mottaghi, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    FPGA-design av en STDM-baserad multiplexer för seriell multiprotokollskommunikation2012Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    The remotely operated underwater vehicles that the client develops have needs of different kinds of data channels. In order to minimize the need of physical cable between the control unit and a ROV, a multiplex protocol has been developed. The protocol has been designed with the aim of using the bandwidth of the transferring link as efficient as possible.

    The different kinds of data channels used during this thesis project is; RS232, RS485 and CAN. ROM and FIFO-memories have been used to be able to effectively manage the different data channels. All the reading and sending of these channels have been implemented in FPGA-technology, the coding is made generic so that it will be easier to add more channels to the system in the future.

    The multiplex protocol is a modified version of the method STDM and it is a proprietary protocol. Calculations has been made in MatLab to ensure that the protocol does not exceed the maximal bandwidth that is available. The protocol utilizes the error-detecting technique CRC for the purpose of error detection.

    A PCB has been developed during this thesis project, the PCB is made so that the different data channels have connection with the FPGA circuit.

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  • 253.
    Jing Xu, Wei
    et al.
    Nanyang Technology University, Singapore .
    Jun Yu, Ya
    Nanyang Technology University, Singapore .
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 3, p. 764-777Article in journal (Refereed)
    Abstract [en]

    The paper proposes an optimization technique for the design of variable digital filters with simultaneously tunable bandedge and fractional delay using a fast filter bank (FFB) approach. In the FFB approach, full band signals are split into multibands, and each band is multiplied by a proper phase shift to realize the variable fractional delay. In the proposed technique, in the formulation of the optimization of the 0th stage prototype filter of the FFB, the ripples of the filters in the subsequent stages are all taken into consideration. In addition, a shaping filter is applied to the last retained band of the FFB to form the transition band of the variable filter, such that the transition width of each band in the FFB can be relaxed to reduce the computational complexity. In total three shaping filters, constructed from a prototype filter, can be shared by different bands, so that the extra cost incurred due to the shaping filter is low.

  • 254.
    Johan, Berneland
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and Construction of Relay-Based RF-SignalSwitching Module for High Signal Integrity2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis work consists of constructing and validating a module designed tofacilitate automatic testing of digitizers at SP Devices. The focus of the report isthe use of simulations of transmission lines to maximise signal integrity. Signalintegrity is discussed mainly from an electromagnetic point of view and the parametersaffecting the signal integrity are presented and discussed. It is shownthat simulations using 2D field solvers work well in the cases where 2D modelsare applicable, while 3D field solvers should be used in other cases. The importanceof simulating all transmission line features is seen in the resulting measurementsas the characteristic impedance misses the mark in the cases that are notsufficiently simulated.The design of a trigger generation circuitry is presented and the resulting mismatchbetween Spice simulations and results are discussed and analysed.

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    fulltext
  • 255.
    Johansson, Anders
    Linköping University, Department of Electrical Engineering, Electronics System.
    Evaluation of different CMOS processes using a circuit optimization tool2009Independent thesis Basic level (professional degree), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes.

    This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.

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    Evaluation of different CMOS processes using a circuit optimization tool
  • 256.
    Johansson, Emil
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Myhrman, Kim
    Linköping University, Department of Electrical Engineering, Electronics System.
    GSM/WCDMA Leakage Detection System2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Ericsson in Linkoping houses one of the largest test laboratories within thewhole Ericsson Company. Mainly, the laboratories contain equipment forGSM, WCDMA and LTE. To test these systems, a quite large number ofRadio Base Stations are needed. The RBS's are housed in a proportionatelysmall area. Instead of sending signals through the air, cables are used totransfer the RF signals. In this way the equipment communicating witheach other are well speci ed. However this may not be the case if leakageoccur.This thesis work is about developing a system for monitoring the radioenvironment and detect leakages in the test site. There is a need to de newhat a leakage really is and measurements needs to be performed in order toaccomplish this. This report describes how the work has proceeded towardsthe nal implemented solution.

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    FULLTEXT01
  • 257.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Polynomial-Based Time-Varying Filter Structure for the Compensation of Frequency-Response Mismatch Errors in Time-Interleaved ADCs2009In: IEEE JOURNAL OF SELECTED TOPICS IN SIGNAL PROCESSING, ISSN 1932-4553, Vol. 3, no 3, p. 384-396Article in journal (Refereed)
    Abstract [en]

    This paper introduces a structure for the compensation of frequency-response mismatch errors in M-channel time-interleaved analog-to-digital converters (ADCs). It makes use of a number of fixed digital filters, approximating differentiators of different orders, and a few variable multipliers that correspond to parameters in polynomial models of the channel frequency responses. Whenever the channel frequency responses change, which occurs from time to time in a practical time-interleaved ADC, it suffices to alter the values of these variable multipliers. In this way, expensive on-line filter design is avoided. The paper includes several design examples that illustrate the properties and capabilities of the proposed structure.

  • 258.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Farrow-structure-based reconfigurable bandpass linear-phase FIR filters for integer sampling rate conversion2011In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, no 1, p. 46-50Article in journal (Refereed)
    Abstract [en]

    A class of Farrow-structure-based reconfigurable bandpass finite-length impulse response (FIR) filters for integer sampling rate conversion is introduced. The converters are realized in terms of a number of fixed linear-phase FIR subfilters and two sets of reconfigurable multipliers that determine the passband location and conversion factor, respectively. Both Mth-band and general FIR filters can be realized, and the filters work equally well for any integer factor and passband location. Design examples are included demonstrating their efficiency compared to modulated regular filters. In addition, in contrast to regular filters, the proposed ones have considerably fewer filter coefficients that need to be determined in the filter design process.

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    FULLTEXT01
  • 259.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Fractional-Delay and Supersymmetric Mth-Band Linear-Phase FIR Filters Utilizing Partially Symmetric and Antisymmetric Impulse Responses2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 6, p. 366-370Article in journal (Refereed)
    Abstract [en]

    This brief considers fractional-delay finite-length impulse response (FIR) filters and a class of supersymmetric Mth-band linear-phase FIR filters utilizing partially symmetric and partially antisymmetric impulse responses. Design examples reveal significant multiplication savings, depending on the specification, as compared to traditional filters.

  • 260.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multirate IIR filter structures for arbitrary bandwidths2003In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, no 12, p. 1515-1529Article in journal (Refereed)
    Abstract [en]

    This paper introduces new multirate infinite-length impulse-response (IIR) filter structures for arbitrary bandwidths. The overall filters have the same input and output sample rates. Multirate techniques are only used internally in order to improve the efficiency. The overall filters make use of an IIR filter for the actual filtering,. periodic allpass filters for constructing complementary filters, and linear-phase finite-length impulse-response (FIR) filters for the sampling rate alterations. There are the following two main reasons for introducing the new filters: 1) they can be used to obtain so called high-speed IIR filters (i.e., filters able to operate at a high sample rate) with lower complexity than that achievable with single-rate high-speed filters and 2) they can be used to obtain approximately linear-phase filters with substantially lower complexity than that achievable with single-rate filters. The overall filters are designed by separately optimizing a number of linear-phase (possibly half-band) FIR filters, and one IIR filter being realizable as a parallel connection of two allpass filters. Design examples are included illustrating the usefulness of the proposed filters.

  • 261.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Compensation of Frequency-Response Mismatch Errors in Time-Interleaved ADCs2008Conference paper (Refereed)
    Abstract [en]

    This paper gives an overview of recent advances in compensation of frequency-response mismatch errors in time-interleaved ADCs. In particular, two methods are considered that are suitable for off-line and on-line calibration, respectively.

  • 262.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A realization of FIR filters with simultaneously variable bandwidth and fractional delay2012In: Signal Processing Conference (EUSIPCO), 2012, IEEE , 2012, p. 2178-2182Conference paper (Refereed)
    Abstract [en]

    This paper introduces a realization of finite-length impulse response (FIR) filters with simultaneously variable bandwidth and fractional delay (FD). The realization makes use of impulse responses which are two-dimensional polynomials in the bandwidth and FD parameters. Unlike previous polynomial-based realizations, it utilizes the fact that a variable FD filter is typically much less complex than a variable-bandwidth filter. By separating the corresponding subfilters in the overall realization, significant savings are thereby achieved. A design example, included in the paper, shows about 65 percent multiplication and addition savings compared to the previous polynomial-based realizations. Moreover, compared to a recently introduced alternative fast filter bank approach, the proposed method offers significantly smaller group delays and group delay errors.

  • 263.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Add-Equalize Structures for Linear-Phase Nyquist FIR Filter Interpolators and Decimators2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 6, p. 1766-1777Article in journal (Refereed)
    Abstract [en]

    This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (th-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted -norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures.

  • 264.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    FIR Filter With Variable Fractional Delay and Phase Shift: Efficient Realization and Design Using Reweighted l(1)-Norm Minimization2013Conference paper (Refereed)
    Abstract [en]

    This paper introduces a finite-length impulse response (FIR) digital filter having both a variable fractional delay (VFD) and a variable phase shift (VPS). The realization is reconfigurable online without redesign and without transients. It can be viewed as a generalization of the VFD Farrow structure that offers a VPS in addition to the regular VFD. The overall filter is composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. It is designed offline in an iterative manner, utilizing reweighted l(1)-norm minimization. This design procedure generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails.

  • 265.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Two Polynomial FIR Filter Structures With Variable Fractional Delay and Phase Shift2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 5, p. 1355-1365Article in journal (Refereed)
    Abstract [en]

    This paper introduces two polynomial finite-length impulse response (FIR) digital filter structures with simultaneously variable fractional delay (VFD) and phase shift (VPS). The structures are reconfigurable (adaptable) online without redesign and do not exhibit transients when the VFD and VPS parameters are altered. The structures can be viewed as generalizations of VFD structures in the sense that they offer a VPS in addition to the regular VFD. The overall filters are composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. A systematic design algorithm, based on iteratively reweighted l(1)- norm minimization, is proposed. It generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails. The paper considers two different structures, referred to as the basic structure and common-subfilters structure, and compares these proposals as well as the existing cascaded VFD and VPS structures, in terms of arithmetic complexity, delay, memory cost, and transients. In general, the common-subfilters structure is superior when all of these aspects are taken into account. Further, the paper shows and exemplifies that the VFDPS filters under consideration can be used for simultaneous resampling and frequency shift of signals.

  • 266.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Lahti, Jimmie
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Tree-Structured Linear-Phase Nyquist FIR Filter Interpolators and Decimators2012In: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), IEEE , 2012, p. 2329-2332Conference paper (Refereed)
    Abstract [en]

    This paper introduces a new class of linear-phase Nyquist (Mth-band) FIR interpolators and decimators based on tree structures. Through design examples, it is shown that the proposed converter structures have a substantially lower computational complexity than the conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist converters, although the proposed ones tend to have a somewhat higher complexity. A main advantage of the proposed structures is however that they can be used for arbitrary integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters.

  • 267.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Linear-phase FIR interpolation, decimation, and M th-band filters utilizing the farrow structure2005In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 52, no 10, p. 2197-2207Article in journal (Refereed)
    Abstract [en]

    This paper introduces novel linear-phase finite-impulse response (FIR) interpolation, decimation, and Mth-band filters utilizing the Farrow structure. In these new overall filters, each polyphase component (except for one term) is realized using the Farrow structure with a distinct fractional delay. The corresponding interpolation/decimation structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. The main advantage of the proposed structures is that they are flexible as to the conversion factors, and this also for an arbitrary set of integer factors, including prime numbers. In particular, they can simultaneously implement several converters at a low cost. The proposed filters can be used to generate both general filters and Mth-band filters for interpolation and decimation by the integer factor M. (In this paper, a general filter for interpolation and decimation by M means a filter having a bandwidth of approximately p/M without the restriction that p/M be included in the transition band. This is in contrast to ah Mth-band filter whose transition band does include p/M.) In both cases, the overall filter design problem can be posed as a convex problem, the solution of which is globally optimum. Design examples are included in the paper illustrating the properties and potentials of the proposed filters. © 2005 IEEE.

  • 268.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Mth-band linear-phase FIR filter interpolators and decimators utilizing the Farrow structure2004In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 3, IEEE , 2004, p. 129-132Conference paper (Other academic)
    Abstract [en]

    This paper introduces Mth-band linear-phase FIR filter interpolators and decimators utilizing the Farrow structure. In these new overall structures, each polyphase component (except for the pure delay term) is a Farrow structure with a distinct fractional delay. The overall structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. Many of these multiplier coefficients are trivial and it is possible to further reduce the complexity by utilizing symmetries. The proposed converter structures are more efficient than conventional single-stage converters structures are more efficient than conventional single-stage converters but less efficient than multistage converters in terms of arithmetic operations required per sample. However, the main advantages of the proposed structures are that they can be used also for conversions with prime number and that they are flexible as to the conversion factors. In particular, they can simultaneously implement several converters at a low cost. The multistage converters are not fully flexible since they can be designed using linear programming which generates optimum filters in the minimax sense. Design examples are included.

  • 269.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Two-Rate Based Structures for Computationally Efficient Wide-Band FIR Systems2013In: Digital Filters and Signal Processing / [ed] Fausto Pedro García Márquez and Noor Zaman, InTech, 2013, p. 189-212Chapter in book (Refereed)
    Abstract [en]

    Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability.  This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide.

  • 270.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Adjustable fractional-delay FIR filters using the Farrow structure and multirate techniques2006In: Asia Pacific Conference on Circuits and Systems,2006, 2006, p. 1055-1058Conference paper (Refereed)
    Abstract [en]

    The Farrow structure can be used for efficient realization of adjustable fractional-delay finite-length impulse response (FIR) filters, but, nevertheless, its implementation complexity grows rapidly as the bandwidth approaches the full bandwidth. To reduce the complexity, a multirate approach can be used. In this approach, the input signal is first interpolated by a factor of two via the use of a fixed half-band linearphase FIR filter. Then, the actual fractional-delay filtering takes place. Finally, the so generated signal is downsampled to retain the original input/output sampling rate. In this way, the bandwidth of the fractional-delay filter used is halved compared to the overall bandwidth. Because the complexity of halfband linear-phase FIR filter interpolators is low, the overall complexity can be reduced. In this paper, we present more implementation details, design trade-offs, and comparisons when the filters are implemented using multiple constant multiplication techniques, which realize a number of constant multiplications with a minimum number of adders and subtracters.

  • 271.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Hermanowicz, Ewa
    A complex variable fractional-delay FIR filter structure2007In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 54, no 9, p. 785-789Article in journal (Refereed)
    Abstract [en]

    This brief introduces a structure for complex variable fractional delay (FD) finite-length impulse response (FIR) filters. The structure is derived from a real variable FD FIR filter and is constituted by a set of fixed real linear-phase FIR filters and two multiply-accumulate chains containing variable multipliers. In this way the implementation complexity and delay may be reduced in comparison with the cascade approach which hitherto has been used for the same purpose. A design example is included to demonstrate the benefits of the new structure. © 2007 IEEE.

  • 272.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Hermanowicz, Ewa
    Adjustable fractional-delay filters utilizing the Farrow structure and multirate techniques2006In: Sixth Int. Workshop Spectral Methods Multirate Signal Processing,2006, 2006Conference paper (Refereed)
    Abstract [en]

    The Farrow structure can be used for efficient realization of adjustable fractional-delay FIR filters, but despite its efficiency compared to other approaches, its implementation complexity grows rapidly as the bandwidth approaches p. To reduce the complexity, a multirate approach has been proposed. In this approach, the input signal is first interpolated by a factor of two via the use of a fixed half-band linear-phase FIR filter. Then, the actual fractional-delay filtering takes place. Finally, the so generated signal is downsampled to retain the original input/output sampling rate. In this way, the bandwidth of the fractional-delay filter used is halved compared to the overall bandwidth. Because the complexity of half-band linear-phase FIR filter interpolators is low, the overall complexity can be reduced. In this paper, we give further details of the multirate approach that have not been published before. In addition, we introduce the use of an approximately linear-phase IIR filter instead of a linear-phase FIR filter in the interpolation process in order to reduce the complexity even further. Design examples are included demonstrating this point.

  • 273.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hermanowicz, Ewa
    Gdansk University of Technology, Poland .
    Two-Rate Based Low-Complexity Variable Fractional-Delay FIR Filter Structures2013In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN 1549-8328, Vol. 60, no 1, p. 136-149Article in journal (Refereed)
    Abstract [en]

    This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient because most of the overall arithmetic complexity is due to the HB filter which is common to all Farrow-structure subfilters. This paper extends and generalizes existing results. Firstly, frequency-response masking (FRM) HB filters are utilized which offer further complexity reductions. Secondly, both linear-phase and low-delay subfilters are treated and combined which offers trade-offs between the complexity, delay, and magnitude response overshoot which is typical for low-delay filters. Thirdly, the HB filter is replaced by a general filter which enables additional frequency-response constraints in the upper frequency band which normally is treated as a dont-care band. Wide-band design examples (90, 95, and 98% of the Nyquist band) reveal arithmetic complexity savings between some 20 and 85% compared with other structures, including infinite-length impulse response structures. Hence, the VFD filter structures proposed in this paper exhibit the lowest arithmetic complexity among all hitherto published VFD filter structures.

  • 274.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg , Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Least-Squares Filter Design Technique for the Compensation of Frequency Response Mismatch Errors in Time-Interleaved A/D Converters2008In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN 1549-7747 , Vol. 55, no 11, p. 1154-1158Article in journal (Refereed)
    Abstract [en]

    This paper introduces a least-squares filter design technique for the compensation of frequency response mismatch errors in M-channel time-interleaved analog-to-digital converters. The overall compensation system is designed by determining M filter impulse responses analytically through M separate matrix inversions. The proposed technique offers an alternative to least-squares techniques that determine all filters simultaneously. Several design examples are included for illustration.

  • 275.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Flexible frequency-band reallocation networks based on variable oversampled complex-modulated filter banks2005In: IEEE International Conference on Acoustics Speech and Signal Processing,2005, 2005, p. iii/973-iii/976Conference paper (Refereed)
    Abstract [en]

    An important issue in the next-generation satellite-based communication systems is the satellite on-board reallocation of information which calls for digital flexible frequency-band reallocation (FFBR) networks. This paper introduces a new class of FFBR networks based on variable oversampled complex-modulated filter banks (FBs). The new class can outperform previously existing ones when flexibility, low complexity and inherent parallelism, perfect frequency-band reallocation, and simplicity are considered simultaneously.

  • 276.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Flexible frequency-band reallocation networks using variable oversampled complex-modulated filter banks2007In: EURASTP journal an applied signal processing, ISSN 1110-8657, E-ISSN 1687-0433, Vol. 2007Article in journal (Refereed)
    Abstract [en]

    A crucial issue in the next-generation satellite-based communication systems is the satellite on-board reallocation of information which requires digital flexible frequency-band reallocation (FBR) networks. This paper introduces a new class of flexible FBR networks based on variable oversampled complex-modulated filter banks (FBs). The new class can outperform the previously existing ones when all the aspects flexibility, low complexity and inherent parallelism, near-perfect frequency-band reallocation, and simplicity are considered simultaneously.

  • 277.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Linear programming design of linear-phase FIR filters with variable bandwidth2003In: IEEE International Symposium on Circuits and Systems,2003, 2003, p. III-554-III-557Conference paper (Refereed)
    Abstract [en]

    This paper considers the design of linear-phase FIR digital filters that have a variable bandwidth whereas the phase response is fixed. For this purpose, we employ a structure in which the overall transfer function is a weighted linear combination of fixed subfilters and where the weights are directly determined by the bandwidth. We introduce a linear programming design technique which generates globally optimal overall filters in the minimax (Chebyshev) sense. Further, both the cases where the subfilters are of equal and different orders, respectively, are treated. Earlier, only the equal-order case has been considered.

  • 278.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    On adjustable fractional delay FIR filters and their design2001In: European Conference on Circuits Theory and Design,2001, 2001Conference paper (Refereed)
  • 279.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    On the design of adjustable fractional delay FIR filters2003In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 50, no 4, p. 164-169Article in journal (Refereed)
    Abstract [en]

    This brief considers minimax design of adjustable fractional delay finite-impulse response (FIR) filters. We employ a filter structure that, in the paper by Vesma and SaramΣki in 1997, is referred to as the modified Farrow structure which makes use of a number of linear-phase FIR subfilters. Previously, only the cases where all subfilters are of equal orders have been considered. In this brief, we propose a design technique that in general produces subfilters of different orders which results in a lower overall arithmetic complexity. Design examples are included, illustrating the efficiency of the proposed design technique.

  • 280.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Reconstruction of a class of nonuniformly sampled and decimated bandlimited signals2002In: IEEE International Symposium on Circuits and Systems,2002, 2002, p. II-604-II-607Conference paper (Refereed)
    Abstract [en]

    This paper introduces a system for reconstructing a class of nonuniformly sampled and decimated bandlimited signals. This system makes use of a number of real-valued multipliers and one digital filter. One advantage of the new system is that it easily can achieve perfect reconstruction in the whole frequency band. A drawback is that it requires that the signals be oversampled by a factor that exceeds the theoretical value.

  • 281.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Reconstruction of nonuniformly sampled bandlimited signals by means of time-varying discrete-time FIR filters2006In: EURASTP journal an applied signal processing, ISSN 1110-8657, E-ISSN 1687-0433, Vol. 2006Article in journal (Refereed)
    Abstract [en]

    This paper deals with reconstruction of nonuniformly sampledbandlimited continuous-time signals using time-varyingdiscrete-time finite-length impulse response (FIR) filters. Themain theme of the paper is to show how a slight oversamplingshould be utilized for designing the reconstruction filters in aproper manner. Based on a time-frequency function, it is shownthat the reconstruction problem can be posed as one that resemblesan ordinary filter design problem, both for deterministic signalsand random processes. From this fact, an analytic least-squaredesign technique is then derived. Furthermore, for an importantspecial case, corresponding to periodic nonuniform sampling, it isshown that the reconstruction problem alternatively can be posedas a filter bank design problem, thus with requirements on adistortion transfer function and a number of aliasing transferfunctions. This eases the design and offers alternative practicaldesign methods as discussed in the paper. Several design examplesare included that illustrate the benefits of the proposed designtechniques over previously existing techniques.

  • 282.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Reconstruction of nonuniformly sampled bandlimited signals using digital fractional delay filters2001In: IEEE International Symposium on Circuits and Systems,2001, 2001, p. 593-596Conference paper (Refereed)
    Abstract [en]

    This paper considers the problem of reconstructing nonuniformly sampled bandlimited signals using a synthesis system composed of digital fractional delay filters. The overall system can be viewed as a generalization of time-interleaved ADC systems. By generalizing these systems, it is possible to eliminate the errors that are introduced in practice due to time-skew errors

  • 283.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Reconstruction of nonuniformly sampled bandlimited signals using digital fractional delay filters: Error and quantization noise analysis2001In: European Conference on Circuits Theory and Design,2001, 2001Conference paper (Refereed)
  • 284.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vengattaramane, Kameswaran
    Least-squares and minimax design of polynomial impulse response FIR filters for reconstruction of two-periodic nonuniformly sampled signals2007In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 54, no 4, p. 877-888Article in journal (Refereed)
    Abstract [en]

    This paper proposes polynomial impulse response finite-impulse response filters for reconstruction of two-periodic nonuniformly sampled signals. The foremost advantages of using these reconstruction filters are that on-line filter design thereby is avoided and subfilters with fixed dedicated multipliers can be employed in an implementation. The overall implementation cost can in this way be reduced substantially in applications where the sampling pattern changes from time to time. The paper presents two different design techniques that yield optimum filters in the least-squares and minimax senses, respectively. Design examples are included that illustrate the benefits of the proposed filters. © 2007 IEEE.

  • 285.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vengattaramane, Kameswaran
    Reconstruction of M-periodic nonuniformly sampled signals using multivariate impulse response time-varying FIR filters2006In: European Signal Processing Conference,2006, 2006Conference paper (Refereed)
    Abstract [en]

    This paper introduces multivariate polynomial impulse response time-varying FIR filters for reconstruction of M-periodic nonuniformly sampled signals. The main advantages of these reconstruction filters are that 1) they do not require on-line filter design, and 2) most of their multipliers are fixed and can thus be implemented using low-cost dedicated multiplier elements. This is in contrast to existing filters that require on-line design as well as many general multipliers in the implementation. By using the proposed filters, the overall implementation cost may therefore be reduced in applications where the sampling pattern changes now and then. Design examples are included demonstrating the usefulness of the proposed filters.

  • 286.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vengattaramane, Kameswaran
    Reconstruction of two-periodic nonuniformly sampled signals using polynomial impulse response time-varying FIR filters2006In: IEEE International Symposium on Circuits and Systems,2006, 2006Conference paper (Refereed)
    Abstract [en]

    This paper introduces polynomial impulse response time-varying FIR filters for reconstruction of two-periodic nonuniformly sampled signals. The main advantages of using these reconstruction filters are that on-line filter design is avoided, and filters with fixed dedicated multipliers can be used in an implementation (except for a few general multipliers). This is in contrast to existing filters that require on-line design as well as general multipliers in the implementation. By using the proposed filters, the overall implementation cost can therefore be reduced dramatically in applications where the sampling pattern changes now and then.

  • 287.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    High-speed lattice wave digital filters for interpolation and decimation1996In: Proc. National Conf. on Radio Science and Communication, RVK'96, 1996, p. 543-547Conference paper (Other academic)
    Abstract [en]

    Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.

  • 288.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Filter structures composed of all-pass and FIR filters for interpolation and decimation by a factor of two1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 7, p. 896-905Article in journal (Refereed)
    Abstract [en]

    This paper introduces filter structures for interpolation and decimation by a factor of two. The structures are derived by using the frequency-response masking approach, in which the overall filter makes use of a periodic model filter, its complementary filter, and two masking filters. The periodic model filters are obtained by replacing each delay element in a model filter with M delay elements in cascade. The model filter is a half-band infinite-impulse response (IIR) filter composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. In the final interpolator and decimator structures the filtering takes plate at the lowest of the two sampling rates involved. The corresponding overall filter can be designed by separately optimizing a half-band IIR filter and a linear-phase FIR filter. Both nonlinear-phase and approximately linear-phase filters are considered. One advantage of the proposed filter structures over conventional half-band IIR filter structures is that their maximal sample frequency is M times higher, which may be utilized to increase the speed in an implementation and/or to reduce the power consumption via power supply voltage scaling techniques. In the case of approximately linear-phase filters, the computational complexity can be reduced as well. Several design examples are included demonstrating the properties and advantages of the proposed filter structures

  • 289.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    High-speed recursive digital filters based on frequency masking techniques1999In: National Conf. Radio Science RVK,1999, 1999, p. 357-361Conference paper (Refereed)
    Abstract [en]

    High-speed recursive digital filters are of interest for applications focusing on high-speed as well as low power consumption because excess speed can be traded for low power consumption through the use of power supply voltage scaling techniques. This paper gives an overview of high-speed recursive digital filters based on frequency masking techniques.

  • 290.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    High-speed recursive digital filters based on the frequency-response masking approach2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 1, p. 48-61Article in journal (Refereed)
    Abstract [en]

    The frequency-response masking approach for high-speed recursive infinite-impulse response (IIR) digital filters is introduced. In this approach, the overall filter consists of a periodic model filter, its power-complementary periodic filter, and two masking filters. The model filters are composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. The transfer functions of the all-pass filters are functions of zM, which implies that the maximal sample frequency for the overall filter is M times that of the corresponding conventional IIR filter. The maximal sample frequency can be increased to an arbitrary level for arbitrary bandwidths. The overall filter can be designed by separately optimizing the model and masking filters with the aid of conventional approximation techniques. The obtained overall filter also serves as a good initial filter for further optimization. Both nonlinear-phase and approximately linear-phase filters are considered. By using the new approach, the potential problems of pole-zero cancellations, which are inherent in algorithm transformation techniques, are avoided. Further, robust filters under finite-arithmetic conditions can always be obtained by using wave-digital all-pass filters and non-recursive FIR filters. Several design examples are included illustrating the properties of the new filters.

  • 291.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    High-speed recursive filter structures composed of identical all-pass subfilters for interpolation, decimation, and QMF banks with perfect magnitude reconstruction1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 1, p. 16-28Article in journal (Refereed)
    Abstract [en]

    High-speed recursive filter structures for interpolation and decimation with factors of two, and quadrature mirror filter (QMF) banks with perfect magnitude reconstruction, are proposed. The structures are composed of identical all-pass subfilters that are interconnected via extra multipliers. For the case of interpolation and decimation filters, the overall transfer function corresponds in the simplest case to several half-band infinite-impulse response (IIR) filters in cascade. To achieve a smaller passband ripple than for a cascade design, a design procedure that has been used earlier for single-rate filters is used. In this approach, the design is split into designs of a prototype finite-impulse response (FIR) filter and a half-band IIR filter. For the case of QMF banks, the design is again separated into designs of a prototype FIR filter and a half-band IIR filter. One major advantage of the proposed filter structures over the corresponding conventional (half-band filter) structures is that the required coefficient word length for the all-pass filters is substantially reduced, implying that the maximal sample frequency can he substantially increased for a given VLSI technology. Further, for interpolation and decimation, the arithmetic complexity may be reduced in comparison with both the conventional structures and straightforward cascade structures. Simple recurrence formulas for computation of the interconnecting multipliers, given the overall transfer function, are derived. Several examples are included which compare the proposed structures with the corresponding conventional and straightforward cascade structures.

  • 292.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wave digital filter structures for high-speed narrow-band and wide-band filtering1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 6, p. 726-741Article in journal (Refereed)
    Abstract [en]

    Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in parallel with an all-pass filter. The overall filters can be designed by separately designing the model and masking filters. The filters obtained in this approach also serve as good initial filters for further optimization. Both nonlinear and approximately linear phase filters are considered. One major advantage of the new filters over the corresponding conventional filters is that they have a substantially higher maximal sample frequency. In the case of approximately linear phase, the computational complexity can also be reduced. Further, the use of bireciprocal lattice wave digital (WD) masking filters also makes it possible to reduce the complexity, compared with the case in which FIR masking filters are used. Several design examples and a discussion of finite wordlength effects are included for demonstrating the properties of the new filters.

  • 293. Order onlineBuy this publication >>
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Power and Low complexity Constant Multiplication using Serial Arithmetic2006Licentiate thesis, monograph (Other academic)
    Abstract [en]

    The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplication using serial arithmetic. The possibility to reduce the complexity and energy consumption is investigated. The main difference between serial and parallel arithmetic, which is of interest here, is that a shift operation in serial arithmetic require a flip-flop, while it can be hardwired in parallel arithmetic.

    The possible ways to connect a certain number of adders is limited, i.e., for single-constant multiplication, the number of possible structures is limited for a given number of adders. Furthermore, for each structure there is a limited number of ways to place the shift operations. Hence, it is possible to find the best solution for each constant, in terms of complexity, by an exhaustive search. Methods to bound the search space are discussed. We show that it is possible to save both adders and shifts compared to CSD serial/parallel multipliers. Besides complexity, throughput is also considered by defining structures where the critical path, for bit-serial arithmetic, is no longer than one full adder.

    Two algorithms for the design of multiple-constant multiplication using serial arithmetic are proposed. The difference between the proposed design algorithms is the trade-offs between adders and shifts. For both algorithms, the total complexity is decreased compared to an algorithm for parallel arithmetic.

    The impact of the digit-size, i.e., the number of bits to be processed in parallel, in FIR filters is studied. Two proposed multiple-constant multiplication algorithms are compared to an algorithm for parallel arithmetic and separate realization of the multipliers. The results provide some guidelines for designing low power multiple-constant multiplication algorithms for FIR filters implemented using digit-serial arithmetic.

    A method for computing the number of logic switchings in bit-serial constant multipliers is proposed. The average switching activity in all possible multiplier structures with up to four adders is determined. Hence, it is possible to reduce the switching activity by selecting the best structure for any given constant. In addition, a simplified method for computing the switching activity in constant serial/parallel multipliers is presented. Here it is possible to reduce the energy consumption by selecting the best signed-digit representation of the constant.

    Finally, a data dependent switching activity model is proposed for ripple-carry adders. For most applications, the input data is correlated, while previous estimations assumed un-correlated data. Hence, the proposed method may be included in high-level power estimation to obtain more accurate estimates. In addition, the model can be used as cost function in multiple-constant multiplication algorithms. A modified model based on word-level statistics, which is accurate in estimating the switching activity when real world signals are applied, is also presented.

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  • 294. Order onlineBuy this publication >>
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Power and Low Complexity Shift-and-Add Based Computations2008Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.

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  • 295.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    DeBrunner, Linda
    FAMU-FSU College of Engineering.
    Estimation of the switching activity in shift-and-add based computations2009In: IEEE International Symposium on Circuits and Systems, Piscataway, 2009, p. 3054-3057Conference paper (Refereed)
    Abstract [en]

    In this work, we propose a switching activity model for constant multipliers. The model can also be used for other architectures that are composed by full adders. Hence, the proposed model is suitable to be used in power consumption aware design algorithms. An important category is algorithms for the multiple-constant multiplication (MCM) problem. The model is shown to agree well with simulations, especially for carry-save arithmetic.

  • 296.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, A.G
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic2004In: Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, Volume 1, IEEE , 2004, p. 197-200Conference paper (Other academic)
    Abstract [en]

    In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.

  • 297.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew
    School of Surveying Spatial Information Systems UNSW, Sydney, Australia.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Trade-offs in low power multiplier blocks using serial arithmetic2005In: National Conf. Radio Science RVK,2005, Linköping: RVK , 2005, p. 271-274Conference paper (Refereed)
    Abstract [en]

    In this paper trade-offs in multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity, logic depth, and power consumption. A new algorithm that reduces the number of shifts while the number of adders is on average the same is presented. Hence, the total complexity is reduced for multiplier blocks implemented using serial arithmetic, where shift operations has a cost. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that need to be considered is logic depth.

  • 298.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity2005In: European Conf. Circuit Theory Design,2005, Cork: IEEE , 2005, p. III/465-Conference paper (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM) has been an active research area for the last decade. Most work so far have only considered the number of additions to realize a number of constant multiplications with the same input. In this work, we consider the number of full and half adder cells required to realize those additions, and a novel complexity measure is proposed. The proposed complexity measure can be utilized for all types of constant operations based on shifts, additions and subtractions. Based on the proposed complexity measure a novel MCM algorithm is presented. Simulations show that compared with previous algorithms, the proposed MCM algorithm have a similar number of additions while the number of full adder cells are significantly reduced.

  • 299.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Approximation of elementary functions using a weighted sum of bit-products2006In: IEEE Int. Symp. Circuits Syst.,2006, Piscataway, NJ: IEEE , 2006, p. 795-Conference paper (Refereed)
    Abstract [en]

    In this work a novel approach for approximating elementary functions is presented. By rewriting the function as a sum of weighted bit-products an efficient implementation is obtained. For most functions a majority of the bit-products can be neglected and still obtain good accuracy. The method is suitable for high-speed implementation of fixed-point functions.

  • 300.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Bit-Level Optimization of Shift-and-Add Based FIR Filters2007In: IEEE International Conference on Electronics, Circuits and Systems,2007, Piscataway, NJ: IEEE , 2007, , p. 713-716p. 713-716Conference paper (Refereed)
    Abstract [en]

    Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

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