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  • 251.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Eilert, Johan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Reduced floating point for MPEG1/2 layer III decoding2004Inngår i: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, s. V-209-12 vol.5-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

  • 252.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Instruction and hardware acceleration for MP-MLQ in G.723.12002Inngår i: IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02)., 2002, s. 235-239Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.

  • 253.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.7292001Inngår i: Proceedings of the 1st IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2001, s. 34-39Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper makes accelerations on instruction level based on the three speech coding algorithms G.723.1, 6.3 kbit/s and 5.3 kbit/s and G.729 8 kbit/s with hardware implementation. All these three algorithms are proposed by the H.323 standard together with G.711 64 kbit/s and G.728 16 kbit/s. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions [I], [2]. Three hardware structures are proposed to increase the performance.

  • 254.
    Pasha, Muhammad Touqir
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Fahim Ul Haque, Muhammad
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten. NED Univ Engn and Technol, Pakistan.
    Ahmad, Jahanzeb
    Intel Corp, England.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A Modified All-Digital Polar PWM Transmitter2018Inngår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, nr 2, s. 758-768Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

  • 255.
    Pasha, Muhammad Touqir
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Fahim Ul Haque, Muhammad
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten. NED Univ Engn and Technol, Pakistan.
    Ahmad, Jahanzeb
    Intel Corp, England.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    An All-Digital PWM Transmitter With Enhanced Phase Resolution2018Inngår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, nr 11, s. 1634-1638Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    An all-digital pulse width modulated (PWM) transmitter using outphasing is proposed. The transmitter uses PWM to encode the amplitude, and outphasing for enhanced phase control. In this way, the phase resolution of the transmitter is doubled. The proposed scheme was implemented using Stratix IV FGPA and class-D PAs fabricated in a 130 nm standard CMOS. From the measurement results, a spectral performance improvement is observed due to the enhanced phase resolution. As compared to an all-digital polar PWM transmitter, the error vector magnitude for proposed transmitter is reduced by 4.1% and the adjacent channel leakage ratio shows an improvement of 5.6 dB for a 1.4 MHz LTE up-link signal for a carrier frequency of 700 MHz at the saturated output power of 25 dBm.

  • 256.
    Patriksson, Alfred
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Radio signal DOA estimation: Implementing radar signal direction estimation on an FPGA.2019Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    This master’s thesis covers the design and implementation of a monopulse directionof arrival (DOA) estimation algorithm on an FPGA. The goal is to implement a complete system that is capable of estimating the bearing of an incident signal. In order to determine the estimate quality both a theoretical and practical noise analysis of the signal chain is performed.

    Special focus is placed on the statistical properties of the transformation from I/Q-demodulated signals with correlated noise to a polar representation. The pros and cons for three different methods of calculating received signal phasors are also covered.The system is limited to two receiving channels which constrains this report to a 2D analysis. In addition the used hardware is limited to C-band signals. We show that an FPGA implementation of monopulse techniques is definitely viable and that an SNR higher than ten dB allows for a gaussian approximation of the polar representationof an I/Q signal.

  • 257.
    Persson, Stefan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    FPGA Design Tools -: the Challenges of Reporting Performance Data2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Since its introduction in the 1980s, field-programmable gate arrays have seen a growing use over the years. Nowadays FPGAs are found in everything from planetary rovers and base transceiver stations to bitcoin miners. With the technological advancements and the growth of the market, there has been a steady flow of new models with increasing capacity. To make it possible to use this capacity in an efficient way, also the software tools have been improved.

    The applications in research have grown and so has the will to compare both the speed and size between different implementations that try to solve the same or similar problem. However, how to make a good comparison is not well defined. Since few research papers have source code available, such comparisons are hard to make and there is a high risk of comparing apples to pears.

    In this thesis, we will study the impact of different software settings and design constraints on the FPGA design flows to better understand how to report research results. This will be done by running selected designs through different EDA tools, using various settings and finally analyse the data the tools provide. At the end we will begin to define guidelines for how to report and compare implementation data, to give a good account of their performance compared to other designs.

  • 258.
    Pettersson, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Parallel Instruction Decoding for DSP Controllers with Decoupled Execution Units2019Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Applications run on embedded processors are constantly evolving. They are for the most part growing more complex and the processors have to increase their performance to keep up. In this thesis, an embedded DSP SIMT processor with decoupled execution units is under investigation. A SIMT processor exploits the parallelism gained from issuing instructions to functional units or to decoupled execution units. In its basic form only a single instruction is issued per cycle. If the control of the decoupled execution units become too fine-grained or if the control burden of the master core becomes sufficiently high, the fetching and decoding of instructions can become a bottleneck of the system.

    This thesis investigates how to parallelize the instruction fetch, decode and issue process. Traditional parallel fetch and decode methods in superscalar and VLIW architectures are investigated. Benefits and drawbacks of the two are presented and discussed. One superscalar design and one VLIW design are implemented in RTL, and their costs and performances are compared using a benchmark program and synthesis. It is found that both the superscalar and the VLIW designs outperform a baseline scalar processor as expected, with the VLIW design performing slightly better than the superscalar design. The VLIW design is found to be able to achieve a higher clock frequency, with an area comparable to the area of the superscalar design.

    This thesis also investigates how instructions can be encoded to lower the decode complexity and increase the speed of issue to decoupled execution units. A number of possible encodings are proposed and discussed. Simulations show that the encodings have a possibility to considerably lower the time spent issuing to decoupled execution units.

  • 259.
    Pettersson, Tobias
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Synchronization of flywheel position between autonomous devices2012Independent thesis Advanced level (degree of Master (One Year)), 20 poäng / 30 hpOppgave
    Abstract [en]

    More computing power will be required in Scania’s future engine control units. Calculations is therefore needed to be performed on new hardware such as an FPGA. One problem that arises is synchronization of flywheelposition. This master thesis examines the opportunities existing Scania hardware has to perform synchronization of flywheel position. Different concepts for synchronization have been developed and compared with each other. One of the concepts have been implemented and made possible witha PCB-adapter. The results show that synchronization is possible within given real-time requirements. Finally, an analysis to series production has been made. It show the challenges that an FPGA will face when integrated into a future engine control unit.

  • 260.
    Pishgah, Sepehr
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Adaptation of The ePUMA DSP Platform for Coarse Grain Configurability2011Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Configurable devices have become more and more popularnowadays. This is because they can improve the system performance inmany ways. In this thesis work it is studied how introduction of coarse grain configurability can improve the ePUMA, the low power highspeed DSP platform, in terms ofperformance and power consumption. This study takes two DSP algorithms, Fast Fourier Transform (FFT) and FIR filtering asbenchmarks to study the effect of this new feature. Architectures are presented for calculation of FFT and FIR filters and it is shown how they can contribute to the system performance. Finally it is suggestedto consider coarse grain configurability as an option for improvement of the system.

  • 261.
    Qin, An
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Design and Implementation of a Source Code Profiling Toolset for Embedded System Analysis2010Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The market needs for embedded or mobile devices were exploding in the last few years. Customers demand for devices that not only have high capacity of managing various complex jobs, but also can do it fast. Manufacturers therefore, are looking for a new field of processors that fits the special needs of embedded market, for example low power consumption, highly integrated with most components, but also provides the ability to handle different use cases. The traditional ASICs satisfied the market with great performance-per-watt but limited scalability. ASIP processors on the other hand, impact the new market with the ability of high-speed optimized general computing while energy efficiency is only slightly lower than ASICs.

    One essential problem in ASIP design is how to find the algorithms that can be accelerated. Hardware engineers used to optimize the instruction set manually. But with the toolset introduced in this thesis, design automation can be made by program profiling and the development cycle can be trimmed therefore reducing the cost. Profiling is the process of exposing critical parts of a certain program via static code analysis or dynamic performance analysis. This thesis introduced a code profiler that targeted at discovering repetition section of a program through static and dynamic analysis. The profiler also measures the payload of each loop and provides profiling report with a user friendly GUI client.

  • 262.
    Ragnemalm, Ingemar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Computing The Euclidean Distance Transform on the ePUMA Parallel Hardware2011Inngår i: Computer Graphics, Visualization, Computer Vision and Image Processing 2011 / [ed] Yingcai Xiao, 2011, s. 228-232Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The ePUMA architecture is a novel parallel architecture being developed as a platform for low-power computing, typically for embedded or hand-held devices. As part of the exploration of the platform, we have implemented the Euclidean Distance Transform. We outline the ePUMA architecture and describe how the algorithm was implemented.

  • 263.
    Ragnemalm, Ingemar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Adapting the ePUMA Architecture for Hand-held Video Games2012Inngår i: International Journal of Computer Information Systems and Industrial Management Applications, ISSN 2150-7988, Vol. 4, s. 153-160Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The ePUMA architecture is a novel parallel archi- tecture being developed as a platform for low-power computing, typically for embedded or hand-held devices. It was originally designed for radio baseband processors for hand-held devices and for radio base stations. It has also been adapted for executing high definition video CODECs. In this paper, we investigate the possibilities and limitations of the platform for real-time graphics, with focus on hand-held gaming.

  • 264.
    Ragnemalm, Ingemar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Towards using the ePUMA architecture for hand-held video games2010Inngår i: COMPUTER GRAPHICS,  VISUALIZATION, COMPUTER VISION  AND IMAGE PROCESSING 2010, 2010, s. 380--384Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The ePUMA architecture is a novel parallel architecture being developed as a platform for low-power computing,

    typically for embedded or hand-held devices. It was originally designed for radio baseband processors for hand-held

    devices and for radio base stations. It has also been adapted for executing high definition video CODECs. In this paper,

    we investigate the possibilities and limitations of the platform for real-time graphics, with focus on hand-held gaming.

  • 265.
    Rasool, Muhammad Ahsan
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Jamal, Abdul
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Quality of freeware antivirus software2011Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    War between malware and antimalware software started two decade back and have adopted the modern techniques with the evolution of technological development in the field of information technology. This thesis was targeted to analyze the performance of freeware antivirus programs available in the market. Several tests were performed to analyze the performance with respect to the core responsibilities of these software’s to scan and detect the viruses and also prevent and eradicate form them. Although irrelevant for common users may be but very important for technical professionals, many tests were performed to analyze the quality of these softwares with respect to their effects on the system it-self like utilization and engagement of precious resources, processing times and also system slowdown because of monitoring techniques. The results derived from these tests show not only the performance and quality of these softwares but also enlighten some areas to be focused for further analysis.

  • 266.
    Sadeghifar, Mohammad Reza
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten. Ericsson AB, Sweden.
    Bengtsson, Hakan
    Ericsson AB, Sweden.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC2019Inngår i: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 66, s. 128-134Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital EA modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

    Fulltekst tilgjengelig fra 2021-03-12 08:04
  • 267.
    Sadeghifar, Mohammad Reza
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten. Ericsson AB, Sweden.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics2019Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 99, nr 2, s. 287-298Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

  • 268.
    Sadeghifar, Mohammad Reza
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter2014Inngår i: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, s. 2465-2468Konferansepaper (Fagfellevurdert)
    Abstract [en]

    An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

  • 269.
    Sandberg, Hampus
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Radiation Hardened System Design with Mitigation and Detection in FPGA2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    FPGAs are attractive devices as they enable the designer to make changes to the system during its lifetime. This is important in the early stages of development when all the details of the final system might not be known yet. In a research environment like at CERN there are many FPGAs used for this very reason and also because they enable high speed communication and processing. The biggest problem at CERN is that the systems might have to operate in a radioactive envi- ronment which is very harsh on electronics. ASICs can be designed to withstand high levels of radiation and are used in many places but they are expensive in terms of cost and time and they are not very flexible. There is therefore a need to understand if it is possible to use FPGAs in these places or what needs to be done to make it possible.

    Mitigation techniques can be used to avoid that a fault caused by radiation is disrupting the system. How this can be done and the importance of under- standing the underlying architecture of the FPGA is discussed in this thesis. A simulation tool used for injecting faults into the design is proposed in order to verify that the techniques used are working as expected which might not always be the case. The methods used during simulation which provided the best protec- tion against faults is added to a system design which is implemented on a flash based FPGA mounted on a board. This board was installed in the CERN Proton Synchrotron for 99 days during which the system was continuously monitored. During this time 11 faults were detected and the system was still functional at the end of the test. The result from the simulation and hardware test shows that with reasonable effort it is possible to use commercially available FPGAs in a radioactive environment. 

  • 270.
    Sandstedt, Adam
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Implementation and analysis of a virtual platform based on an embedded system2014Independent thesis Advanced level (degree of Master (Two Years)), 300 hpOppgave
    Abstract [en]

    The complexity among embedded systems has increased dramatically in recent years. During the same time has the capacity of the hardware grown to astonishing levels. These factors have contributed to that software has taken a leading role and time-consuming role in embedded system development.Compared with regular software development, embedded development is often more restrained by factors such as hardware performance and testing capability. A solution to some of these problem has been proposed and that is a concept called virtual platforms. By emulating the hardware in a software environment, it is possible to avoid some of the problems associated with embedded software development. For example is it possible to execute a system faster than in reality and to provide a more controllable testing environment. This thesis presents a case study of an application specific virtual platform. The platform is based on already existing embedded system that is located in an industrial control system.  The virtual platform is able to execute unmodified application code at a speed twice of the real system, without causing any software faults. The simulation can also be simulated at even higher speed if some accuracy losses are regarded as acceptable.The thesis presents some tools and methods that can be used to model hardware on a functional level in an software environment. The thesis also investigates the accuracy of the virtual platform by comparing it with measurements from the physical system. In this case are the measurements mainly focused of the data transactions in a controller area network bus (CAN).

  • 271.
    Sandvik, Fredrik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Tingstam, Olle
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Design and Prototyping of a Scalable Contactor Platform Adapted to State-of-the-Art Functions2015Independent thesis Advanced level (professional degree), 20 poäng / 30 hpOppgave
    Abstract [en]

    The goal of the thesis is to investigate and propose a new design for a contactor platform, both in terms of hardware and embedded software, which incorporates support to implement new state-of-the-art functions. The platform must support a wide range of contactors from basic ones with only core functions to advanced contactors using modern microcontrollers to provide efficient, quick and reliable operation.

     

    Further, a significant focus of the thesis is on the interaction between electrical engineering and computer engineering. The electronics needs to interact seamlessly with a microcontroller running a versatile software to provide industry-leading performance. To achieve this, the software and hardware is evaluated with focus to develop an optimal platform.

     

    The proposed embedded software uses development techniques rarely used in embedded applications such as UML code generation, compile-time initiation of objects and an object-oriented design, while maintaining the performance of traditional embedded programming. The thesis also provides suggestions to hardware changes to further improve to the contactor’s operation.

  • 272. Sathe, Sumant
    et al.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Design of a switching node (router) for on-chip networks2003Inngår i: Int Conference on ASIS ASICON,2003, 2003Konferansepaper (Fagfellevurdert)
  • 273.
    Siverskog, Jacob
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Evaluation of partial reconfiguration for FPGA debugging2010Independent thesis Advanced level (professional degree), 20 poäng / 30 hpOppgave
    Abstract [en]

    Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis.

    Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware.

    In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on.

    One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.

  • 274.
    Skarman, Frans
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    High Level Synthesis for Optimising Hybrid Electric Vehicle Fuel Consumption Using FPGAs and Dynamic Programming2019Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    The fuel usage of a hybrid electric vehicle can be reduced by strategically combining the usage of the combustion engine with the electric motor. One method to determine an optimal split between the two is to use dynamic programming. However, the amount of computations grows exponentially with the amount of states which makes its usage difficult on sequential hardware. This thesis project explores the usage of FPGAs for speeding up the required computations to possibly allow the optimisation to run in real time in the vehicle. A tool to convert a vehicle model to a hardware description language was developed and evaluated. The current version does not run fast enough to run in real time, but some optimisations which would allow that are proposed.

  • 275.
    Sohl, Joar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories2015Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced. Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.

    Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.

    More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?

    Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance  with power efficiency and silicon cost that is comparable to ASICs. The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.

    One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software. Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.

    This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to generate code from.

  • 276.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Conflict-free data access for multi-bank memory architectures using padding2013Inngår i: High Performance Computing (HiPC), 2013, IEEE , 2013, s. 425-432Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For high performance computation memory access is a major issue. Whether it is a supercomputer, a GPGPU device, or an Application Specific Instruction set Processor (ASIP) for Digital Signal Processing (DSP) parallel execution is a necessity. A high rate of computation puts pressure on the memory access, and it is often non-trivial to maximize the data rate to the execution units. Many algorithms that from a computational point of view can be implemented efficiently on parallel architectures fail to achieve significant speed-ups. The reason is very often that the speed-up possible with the available execution units are poorly utilized due to inefficient data access. This paper shows a method for improving the access time for sequences of data that are completely static at the cost of extra memory. This is done by resolving memory conflicts by using padding. The method can be automatically applied and it is shown to significantly reduce the data access time for sorting and FFTs. The execution time for the FFT is improved with up to a factor of 3.4 and for sorting by a factor of up to 8.

  • 277.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Automatic Permutation for Arbitrary Static Access Patterns2012Inngår i: Parallel and Distributed Processing with Applications (ISPA), 2012, IEEE , 2012, s. 215-222Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A significant portion of the execution time on current SIMD and VLIW processors is spent on data access rather than instructions that perform actual computations. The ePUMA architecture provides features that allow arbitrary data elements to be accessed in parallel as long as the elements reside in different memory banks. Using permutation to move data elements that are accessed in parallel, the overhead from memory access can be greatly reduced; and, in many cases completely removed. This paper presents a practical method for automatic permutation based on Integer Linear Programming (ILP). No assumptions are made about the structure of the access patterns other than their static nature. Methods for speeding up the solution time for periodic access patterns and reusing existing solutions are also presented. Benchmarks for e.g. FFTs show speedups of up to 3.4 when using permutation compared to regular implementations.

  • 278.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture2009Inngår i: ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS, Springer Berlin/Heidelberg, 2009, s. 408-419Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper introduces a novel master-multi-SIMD on-chip multi-core architecture for embedded signal processing. The parallel architecture and its memory subsystem are described in this paper. We evaluate the large size matrix multiplication performance on this parallel architecture and compare it with a SIMD-extended data parallel architecture. We also examine how well the new architecture scales for different numbers of SIMD co-processors. The experimental results show that the ePUMA architecture's memory subsystem can effectively hide the data access overhead. With its 8-way SIMD data path and multi-SIMD parallel execution, the ePUMA architecture improves the performance of matrix multiplication with a speedup of 45x from the conventional SIMD extension.

  • 279.
    Stavström, Marcus
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Evaluation of FPGA based Test Systems2015Independent thesis Advanced level (professional degree), 20 poäng / 30 hpOppgave
    Abstract [en]

    This master thesis report covers an investigation of how FPGA based hardware can be used to create customizable measurement instruments, for test of electrical equipment in JAS 39 Gripen. The investigation is done at Saab Support and Services in Arboga.

    Electrical equipment are gradually replacing functions, which previously have been obtained by other systems, in safety critical environments. Since the functions are safety critical, they require regular testing in order to verify proper operation. The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is an example of such system. Proper operation of the avionics in it are essential in order to maintain flying safety.

    There already exist systems today that can verify the functionality of electronics in JAS 39 Gripen. However, there are a number of scenarios where those test systems are somewhat inflexible. More flexible test systems are often desired. This flexibility can be obtained by using congurable hardware, suggestively with FPGAs. This approach is investigated in this master thesis.

  • 280.
    Stenholm, Roland
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Time-Multiplexed Channel Switches for Dynamic Frequency Band Reallocation2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    A partially parallel reconfigurable channel switch is constructed for use in DFBR. Its permutation can be changed while running without any interruption in the streams of data. Three approaches are tried: one based on asorting network, one based on memories and multiplexers and one based on a Clos network. Variants with the pattern stored in memories and in shift registers are tried. They are implemented in automatically generated Verilog and synthesized for an FPGA. Their cost in terms of area use, memory use and maximum clock frequency is compared and the results show that the Clos based approach is superior in all aspects and that pattern data should not be saved in shift registers. The work is open source and available for download at https://github.com/channelswitch/channelswitch.

  • 281.
    Ström, Henrik
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Parallel FPGA Implementation of Image Convolution2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    Image convolution is a common algorithm that can be found in most graphics editors. It is used to filter images by multiplying and adding pixel values with coefficients in a filter kernel. Previous research work have implemented this algorithm on different platforms, such as FPGAs, CUDA, C etc. The performance of these implementations have then been compared against each other. When the algorithm has been implemented on an FPGA it has almost always been with a single convolution. The goal of this thesis was to investigate and in the end present one possible way to implement the algorithm with 16 parallel convolutions on a Xilinx Spartan 6 LX9 FPGA and then compare the performance with results from previous work. The final system performs better than multi-threaded implementations on both a GPU and CPU.

  • 282.
    Ståhl, Johan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Kollisionsdetekteringssystem för autonom robot2015Independent thesis Basic level (degree of Bachelor), 10,5 poäng / 16 hpOppgave
    Abstract [sv]

    Examensarbetet har utförts på företaget Husqvarna AB vid avdelning Concept & Features electric products (EN-NEP). Uppdraget var att utvärdera en alternativ kollisionsmetod till deras robotgräsklippare. Metoden som utvärderats går ut på att detektera kollision med hjälp av samplad data från en accelerometer samt samplad strömnivå från de bägge drivhjulens motorer.

    Den metod som används för att detektera kollision på nuvarande robotar fungerar väl men kräver att robotens kaross och chassi rör sig ifrån varandra för att krock skall detekteras. För att kunna reducera antalet komponenter och priset på roboten är andra metoder intressanta att utvärdera för uppdragsgivaren.

    En algoritm har designats i simulationsmiljö som sedan testats på ”riktigt” genom implementation i en Raspberry Pi som kommunicerar med robotgräsklipparen. Om den implementerade algoritmen detekterat krock på den samplade datan skickas ett meddelande till roboten att utföra sitt inbyggda krockmönster.

    Resultatet som erhölls var ett fungerande system med stor potential. Med fortsatt arbete skulle metoden kunna bli en framtida ersättare alternativt ett komplement till nuvarande metod.

  • 283.
    Svangård, Bo
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Power management in embedded ARM HW integrated with Embedded Linux2009Independent thesis Basic level (university diploma), 20 poäng / 30 hpOppgave
    Abstract [en]

    Today, more and more embedded hardware devices are reaching the market and consumers with a demand for smaller and better devices than yesterday. Increasing the performance of a device decreases the operating time since more power is consumed, still, decreasing the size of the device also decreases operating time as the battery size decreases.To allow the performance to increase and the size of the device to decrease, the designer must nd techniques allowing the hardware to consume less power during normal usage of a device than during the peak usage.In this thesis an implementation of an ARM based microprocessor system is presented and used for measuring and evaluation of the power consumption possibilities of the system.

  • 284.
    Svensk, Gustav
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Bus System for Coresonic SIMT DSP2016Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    This thesis consists of designing and implementing a bus system for a specific computersystem for MediaTek Sweden AB . The focus of the report is to show the considerations andchoices made in the design of a suitable bus system. Implementation details describe howthe system is constructed. The results show that it is possible to maintain a high bandwidthin many parts of the system if an appropriate topology is chosen. If all units in a bus systemare synchronous it is difficult to reach low latency in the communication.

  • 285.
    Svensson, Christer
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Presenting efficient hardware solutions for SDR terminals.2006Inngår i: Software Defined Radio 2006,2006, 2006Konferansepaper (Fagfellevurdert)
  • 286.
    Svensson, Christian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    High-Speed Storage Encryption over Fibre Channel2013Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    This thesis focused on testing whether persistent encryption of Fibre Channel is doable and what kind of security it provides. It has been shown that intercepting, analysing and modifying Fibre Channel traffic is possible without any noticeable performance loss as long as latency is kept within certain boundaries. If latency are outside those boundaries extreme performance loss are to be expected. This latency demand puts further restrictions on the cryptography to be used.

    Two platforms were simulated, implemented and explained. One for intercepting and modifying Fibre Channel and one for analysing Fibre Channel traffic using Linux and Wireshark.

  • 287.
    Svensson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Gunnarsson, Svante
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska högskolan.
    A Design-Build-Test course in electronics based on the CDIO framework for engineering education2012Inngår i: International Journal of Electrical Engineering Education, ISSN 0020-7209, E-ISSN 2050-4578, Vol. 49, nr 4, s. 349-364Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A Design-Build-Test (DBT) course in electronics is presented. The course is designed based on the CDIO (Conceive-Design-Implement-Operate) framework for engineering education. It is part of the curriculum of two engineering programs at Linköping University, Sweden, where it has been given successfully for a number of years. The cornerstones of the course consist of carefully designed learning outcomes based on the CDIO Syllabus, a structured project management model such that the project tasks are carried out according to professional and industry-like routines, with well-designed organisation of the staff supporting the course, and challenging project tasks.

  • 288.
    Svensson, Tomas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Gunnarsson, Svante
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska högskolan.
    Teaching Project Courses in Large Scale Using Industry Like Methods - Experiences After Ten Years2012Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    A Design-Build-Test (DBT) project course in electronics is presented. The course was developed during the first years of the CDIO Initiative, and it has been given successfully for almost ten years within two engineering programs at Linköping University. More than 2000 students have passed the course, and it is considered to be one of the most popular and also demanding courses within these programs. The key factors that have contributed to the success of the course are:

    • Clearly defined learning outcomes.
    • A suitable and well working course organization.
    • A systematic method for project management.
    • Challenging project tasks of sufficient complexity.
    • Laboratory workspaces with modern equipment and high availability.

    The aim of the paper is to describe these key factors in more detail based on the experiences that have been gained during the almost ten years the course has been given.

  • 289.
    Sánchez Yagüe, Mónica
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Information extraction and validation of CDFG in NoGap2013Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    A Control Data Flow Graph (CDFG) is a Directed Acyclic Graph (DAG) in which a node can be either an operation node or a control node. The target of this kind of graph is to capture allt he control and data flow information of the original hardware description while preserving the various dependencies.

    This kind of graph is generated by Novel Generator of Accelerators and Processors (NoGap), a design automation tool for Application Specific Instruction-set Processor (ASIP) and accelerator design developed by Per Karlström from the Department of Electrical Engineering of Linköping University.

    The aim of this project is to validate the graph, check if it fulfills the requirements of its definition. If it does not, it is considered an error and the running process will be aborted. Moreover, useful information will be extracted from the graph for futute work.

  • 290.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design of Programmable Baseband Processors2005Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc.

    These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates.

    One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes, and different trade-offs between data rate and mobility.

    So far, programmable baseband solutions have mostly been used in high end systems such as mobile telephony base stations since the cost and power consumption have been considered too high for handheld terminals.

    In this work a new low power and low silicon area programmable baseband processor architecture aimed for multi-mode terminals is presented. The architecture is based on a customized DSP core and a number of hardware accelerators connected via a configurable network. The architecture offers a good tradeoff between flexibility and performance through an optimized instruction set, efficient hardware acceleration of carefully selected functions, low memory cost, and low control overhead.

    One main contribution of this work is a study of important issues in programmable baseband processing such as software-hardware partitioning, instruction level acceleration, low power design, and memory issues. Further contributions are a unique optimized instruction set architecture, a unique architecture for efficient integration of hardware accelerators in the processor, and mapping of complete baseband applications to the presented architecture.

    The architecture has been proven in a manufactured demonstrator chip for wireless LAN applications. Wireless LAN firmware has been developed and run on the chip at full speed. Silicon area and measured power consumption have proven to be similar to that of a non-programmable ASIC solution.

  • 291.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Suitable Channel Equalization Scheme for IEEE 802.11b2003Inngår i: Swedish System-on-Chip Conference,2003, 2003Konferansepaper (Annet vitenskapelig)
  • 292.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Low Area and Low Power Programmable Baseband Processor Architecture2005Inngår i: International workshop on SoC for real-time applications,2005, 2005Konferansepaper (Fagfellevurdert)
  • 293.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Programmable DSP core for Baseband Processing2005Inngår i: IEEE Northeast Workshop on Circuits and Systems NEWCAS,2005, 2005Konferansepaper (Fagfellevurdert)
  • 294.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implementation of a Programmable Baseband Processor2005Inngår i: Radiovetenskap och Kommunikation RVK,2005, 2005Konferansepaper (Fagfellevurdert)
  • 295.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Olausson, Mikael
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A General DSP processor at the cost of 23k gates and 1/2 a man-year design time2003Inngår i: International Conference on Acoustics, Speech and Signal Processing,2003, 2003, s. 657-Konferansepaper (Fagfellevurdert)
  • 296.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Seger, Olle
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Converged Hardware Solution for FFT, DCT and Walsh Transform2003Inngår i: International Symposium on Signal Processing and its Applications,2003, 2003, s. 609-Konferansepaper (Fagfellevurdert)
  • 297.
    Tomasson, Orri
    Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implementation of Elementary Functions for a Fixed Point SIMD DSP Coprocessor2010Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    This thesis is about implementing the functions for reciprocal, square root, inverse square root and logarithms on a DSP platform.

    A multi-core DSP platform that consists of one master processor core and several SIMD coprocessor cores is currently being designed by a team at the Computer Engineering Department of Linköping University.

    The SIMD coprocessors’ arithmetic logic unit (ALU) has 16 multipliers to support vector multiplication instructions. By efficiently using the 16 multipliers, it is possible to evaluate polynomials very fast. The ALU does not have (hardware) support for floating point arithmetic, so the challenge is to get good precision by using fixed point arithmetic.

    Precise and fast solutions to implement the mathematical functions are found by converting the fixed point input to a soft floating point format before polynomial approximation, choosing a polynomial based on an error analysis of the polynomial approximation, and using Newton-Raphson or Goldschmidt iterations to improve the precision of the polynomial approximations.

    Finally, suggestions are made of changes and additions to the instruction set architecture, in order to make the implementations faster, by efficiently using the currently existing hardware.

  • 298.
    Tosteberg, Joakim
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Axelsson, Thomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Development of a Wireless Video Transfer System for Remote Control of a Lightweight UAV2012Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
    Abstract [en]

    A team of developers from Epsilon AB has developed a lightweight remote controlledquadcopter named Crazyflie. The team wants to allow a pilot to navigate thequadcopter using video from an on-board camera as the only guidance. The masterthesis evaluates the feasibility of mounting a camera module on the quadcopter andstreaming images from the camera to a computer, using the existing quadcopterradio link. Using theoretical calculations and measurements, a set of requirementsthat must be fulfilled for such a system are identified. Using the requirementsas a basis, various camera products are investigated and the findings presented.A design to fulfill the requirements, using the found products, is proposed. Theproposed design is then implemented and evaluated.

    It is found that the Crazyflie system has the resources necessary to transferan image stream with the quality required for navigation. Furthermore, theimplementation is found to provide the required functionality. From the evaluationseveral key factors of the design that can be changed to further improve theperformance of an implementation are identified. Ideas for future work andimprovements are proposed and possible alternative approaches are presented.

  • 299.
    Touqir Pasha, Muhammad
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Haque, Muhammad Fahim Ul
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Ahmad, Jahanzeb
    University of the West of England, UK.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    An All-Digital Polar PWM Transmitter2018Konferansepaper (Annet vitenskapelig)
  • 300.
    Ul Haque, Muhammad Fahim
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Johansson, Ted
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Large dynamic range PWM transmitter2016Konferansepaper (Annet (populærvitenskap, debatt, mm))
345678 251 - 300 of 362
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