liu.seSearch for publications in DiVA
Change search
Refine search result
45678910 301 - 350 of 602
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 301.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Conversion and addition in logarithmic number systems using a sum of bit-products2006In: IEEE NorChip Conf.,2006, Linköping: IEEE , 2006, , p. 39-42p. 39-42Conference paper (Refereed)
    Abstract [en]

    Computations in logarithmic number systems require realizations of four different elementary functions. In this work we utilize a recently proposed approximation method based on weighted sums of bit-products to realize these functions. It is shown that the considered method can be used to efficiently realize the different functions. However, a transformation is proposed to improve the results for functions with logarithmic characteristics.

  • 302.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Estimation of switching activity for ripple-carry adders adopting the dual bit type method2005In: Swedish System-on-Chip Conf.,2005, Tammsvik: SSoCC , 2005Conference paper (Other academic)
    Abstract [en]

    In this work a model for estimation of the switching activity in ripple-carry adders is presented. The model is based on word-level statistics, such as mean, variance, and correlation, of the two input signals to be added. It is shown that the proposed model gives accurate results when the two-s-complement represented inputs are real world signals.

  • 303.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of elementary functions for logarithmic number systems2008In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, no 4, p. 295-304Article in journal (Refereed)
    Abstract [en]

     Computations in logarithmic number systems require realisations of four different elementary functions. In the current paper the authors use a recently proposed approximation method based on weighted sums of bit-products to realise these functions. It is shown that the considered method can be used to efficiently realise the different functions. Furthermore, a transformation is proposed to improve the results for functions with logarithmic characteristics. Implementation results shows that significant savings in area and power can be obtained using optimisation techniques. 

  • 304.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of low-complexity FIR filters using serial arithmetic2005In: IEEE Int. Symp. Circuits Syst.,2005, Piscataway, NJ: IEEE , 2005, p. II/1449-Conference paper (Refereed)
    Abstract [en]

    The effects of digit-size on FIR filters implemented using multiplier block techniques are studied. Two different multiplier block algorithms are considered, one that minimizes the number of adders without considering the number of shifts and one that minimizes the number of shifts while keeping the number of adders low. Results on area, sample rate, and power consumption are presented, focusing on the arithmetic parts of the FIR filter.

  • 305.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Low power architectures for sine and cosine computation using a sum of bit-products2005In: IEEE NorChip Conf.,2005, Oulu: IEEE , 2005, p. 161-Conference paper (Refereed)
    Abstract [en]

    Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products are used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The effects of this removal and also the finite worldlength representation of the weights has also been discussed in previous work. The objective of this work is to study different ways to split the architecture into sub-blocks that may be disabled to decrease the power consumption.

  • 306.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-complexity bit-serial constant-coefficient multipliers2004In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 3, IEEE , 2004, p. 649-652Conference paper (Other academic)
    Abstract [en]

    In this work we investigate the possibilities to minimize the complexity of bit-serial constant-coefficient multipliers. This is done in terms of number of required building blocks, which includes adders and flip-flops. The multipliers are described using a graph representation. We show that it is possible to find a minimum set of graphs that are required to get optimal results for the different multiplier types. The complexity cost for these multipliers are then investigated. Most results are compared to multipliers that adopt the commonly used canonic signed-digit representation.

  • 307.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multiple Constant Multiplication for Digit-Serial Implementation of Low Power FIR Filters2006In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 1001-1008Article in journal (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.

  • 308.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power estimation for bit-serial constant coefficient multipliers2004In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
    Abstract [en]

    In this work a model for estimation of the power consumption in bit-serial, constant coefficient multipliers is presented. The multipliers are implemented using shift-add operations. Model parameters for the required components, i.e., flip-flops and full-adders, are derived. The power for a multiplier is obtained by summing the power for all components included in the corresponding network of shifts and adders.

  • 309.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power Estimation for Ripple-Carry Adders with Correlated Input Data2004In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2004, 2004, p. 662-674Conference paper (Other academic)
    Abstract [en]

    In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation

  • 310.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power estimation for ripple-carry adders with correlated input data2004In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings / [ed] Enrico Macii, Vassilis Paliouras and Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, p. 662-674Chapter in book (Refereed)
    Abstract [en]

    In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

  • 311.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Switching activity estimation for shift-and-add based constant multipliers2008In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., Piscataway, NJ: IEEE , 2008, , p. 676-679p. 676-679Conference paper (Refereed)
    Abstract [en]

    In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

  • 312.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Switching activity in bit-serial constant coefficient multipliers2004In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 2, IEEE , 2004, p. 469-472Conference paper (Other academic)
    Abstract [en]

    In this paper a method for computing the switching activity in bit-serial constant-coefficient multipliers is presented. The multipliers are described using a graph representation. It is shown that the average switching activity in all multipliers with up to four adders can be determined. Most of the switching activities can be obtained directly from the derived formulas and the remaining by using look-up tables. The switching activities are useful to estimate the power consumption, and makes it possible to choose the best power saving multiplier structure.

  • 313.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Switching activity in bit-serial constant coefficient serial/parallel multipliers2003In: IEEE NorChip Conf.,2003, Piscataway, NJ: IEEE , 2003, p. 260-Conference paper (Refereed)
    Abstract [en]

    In this work a method for computing the switching activity in bit-serial, constant-coefficient serial/parallel multipliers is presented. We derive a function for the switching activities, which is useful to estimate and optimise the power consumption. This makes it possible to choose a power saving coefficient representation.

  • 314.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Trade-offs in multiplier block algorithms for low power digit-serial FIR filters2006In: WSEAS Int. Conf. Circuits,2006, Athens: WSEAS , 2006Conference paper (Refereed)
    Abstract [en]

    In this paper trade-offs in digit-serial multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity and adder depth. Among the three algorithms is a new algorithm that reduces the number of shifts while the number of adders is on average the same. Hence, the total complexity is reduced for multiplier blocks implemented using digit-serial arithmetic, where shift operations have a hardware cost. An example implementation is used to compare the power consumption for five approaches: the three algorithms, using separate multipliers based on CSD representation, and an algorithm based on subexpression sharing. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that needs to be considered is adder depth. Furthermore, digit-serial shifts will reduce glitch propagation.

  • 315.
    Johansson, Thomas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Thalin, Patrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Lindblad, Ulrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    DESIGN OF A SCALABLE DSP PROCESSOR2005In: RVK,2005, Proceedings: RVK , 2005Conference paper (Refereed)
    Abstract [en]

    This paper describes the design of an on-going implementation of a fixed-point DSP processor with variable word length. Based on the top-down design approach described in [1], we discuss the approach based on a sequence of models and stepwise refinements. The pros and cons of selecting different models are investigated as they are compared with each other. For the purpose of validation, a flexible framework has been developed. It allows regression testing and dynamic changing of the test data set and model to be tested. Using the tools, the output is then automatically compared with the expected result as provided by the golden model. The project status today is a synthezisable VHDL model validated using backannotation and VITAL libraries

  • 316.
    Johansson, Thomas
    et al.
    Linköping University, Department of Electrical Engineering.
    Thalin, Patrik
    Linköping University, Department of Electrical Engineering.
    Lindblad, Ulrik
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Development and validation of a scalable DSP core2004In: Swedish System-on-Chip Conference 2004,2004, Båstad: SSOCC , 2004Conference paper (Refereed)
  • 317.
    Johanssson, Stefan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, Department of Electrical Engineering.
    Precision Amplifier for Applications in Electrical Metrology2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master's thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution. To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 μV/V, the phase error is less than 20 μrad, and the input Rp is over 10 MΩ. This is performance in line with the required to make accurate measurements possible at 100 kHz and over that.

    Download full text (pdf)
    FULLTEXT01
  • 318.
    Jones, Omar
    Linköping University, Department of Electrical Engineering, Electronics System.
    DESIGN AND DEVELOPMENT OF AN EMBEDDED DC MOTOR CONTROLLER USING A PID ALGORITHM2010Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    This project was held at London South Bank University in the UK, with corporation with staff from Linköping University in Sweden as Bachelor thesis.

    This report will guide you through the used techniques in order to achieve a successful cooler/Fan project with a minimum budget and good energy saving methods.

    The steps of setting the used software and components are supported with figures and diagrams. You will find full explanation of the used components and mathematics, in additional to a complete working code.

    Download full text (pdf)
    FULLTEXT01
  • 319.
    Kariyannavar, Kiran
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Connecting the human body - Models, Connections and Competition2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Capacitive communication using human body as a electrical channel has attracted much attention in the area of personal area networks (PANs) since its introduction by Zimmerman in 1995. The reason being that the personal information and communication appliances are becoming an integral part of our daily lives. The advancement in technology is also helping a great deal in making them interesting,useful and very much affordable. If we interconnect these body-based devices with capacitive communication approach in a manner appropriate to the power, size, cost and functionality, it lessens the burden of supporting a communication channel by existing wired and wireless technologies. More than that, using body as physical communication channel for a PAN device compared to traditional radio transmission seems to have a lot of inherent advantages in terms of power and security etc. But still a lot of feasibility and reliability issues have to be addressed before it is ready for prime time. This promising technology is recently sub-classified into body area networks (BAN) and is currently under discussion in the IEEE 802.15.6 Task Group for addressing the technical requirements to unleash its full potential for BANs. This could play a part in Ericsson's envision of  50 billion connections by 2020. This thesis work is part of the main project to investigate the models, interface and derive requirements on the analog-front-end (AFE) required for the system. Also to suggest a first order model of the AFE that suits this communication system.In this thesis work the human body is modeled along with interfaces and transceiver to reflect the true condition of the system functioning. Various requirements like sensitivity, dynamic range, noise figure and signal-to-noise ratio (SNR) requirements are derived based on the system model. An AFE model based on discrete components is simulated, which was later used for proof of concept. Also a first order AFE model is developed based on the requirements derived. The AFE model is simulated under the assumed interference and noise conditions. The first order requirements for the submodules of the AFE are also derived. Future work and challenges are discussed.

    Download full text (pdf)
    ConnectedMe_Subproject2
  • 320.
    Karlsson, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Software Acoustic Modem2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The task of this master thesis is to develop a communication system for underwater communication with acoustic waves using simple hardware to keep cost low and time to market short. Simple hardware means trying to do most of the work in digital domain instead of analog domain, modern DSP/FPGA/microprocessors/processors contain much processing power. The communication range should be 100 meters underwater, and should be able to transmit the wanted data at least once every couple of seconds.

    • 100 meters range
    • Raw data rate of one-two kbit/s
    • Use as little analog circuitry as possible
    • Use o the shelf transducer

    Using little analog circuitry and an o shelf transducer will lower the cost of the hardware, the development will also be easier and flexible.

    Download full text (pdf)
    fulltext
  • 321.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A robust non-overlapping two-phase clock generator2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper (Other academic)
  • 322.
    Karlsson, Magnus
    et al.
    Dept. of Tech., Univ. Kalmar.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Digit-serial/parallel multipliers with improved throughput and latency2006In: Proc. 2006 IEEE Int. Symp. Circuits and Systems, ISCAS'06, 2006Conference paper (Refereed)
    Abstract [en]

    Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding.

  • 323.
    Karlsson, Magnus
    et al.
    ISY .
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Kulesza, W.
    A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers2004In: Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS'04, 2004, p. 425-428Conference paper (Refereed)
    Abstract [en]

    Fixed coefficient digit-serial/parallel multipliers are presented. The multipliers are based on unfolded bit-serial/parallel multipliers in combination with canonic signed-digit coding of the fixed coefficient. The unfolding yields long critical paths, which cannot be pipelined due to the feed back carry loops, and carry-look-ahead techniques cannot be applied efficiently since the propagating sum path will increase. By using canonic signed-digit code the multiplier gains higher throughput and lower latency since the critical path is reduced without pipelining. Hence, the throughput is increased with between 56 and 150 percent compared with two's complement coded coefficients, and for the digit-sizes {2,3,4} it has the same throughput as the corresponding digit-serial adder.

  • 324.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Kulesza, W.
    n/a.
    A non-overlapping two-phase clock generator with adjustable duty cycle2003In: Electronic Proc. Nat. Symp. on Microwave Technique and High Speed Electronics, GHz'03, 2003Conference paper (Other academic)
    Abstract [en]

    In this paper, a new robust non-overlapping two-phase clock generator with adjustable duty cycle is proposed. The generator is based on a differential negative edge trigged D flip-flop and has small area and power consumption. The maximal clock rate and delay are also improved reaching a clock frequency of 1.0 GHz in a standard 0.35 µm CMOS process. The new clock generator is inherently glitch and spike free and robust against slow clock transitions, that reduces the design effort significantly.

  • 325.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Kulesza, W.
    n/a.
    Design of digit-serial pipelines with merged logic and latches2003In: Proc. NORCHIP'03, 2003, p. 68-71Conference paper (Refereed)
  • 326.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Kulesza, W.
    n/a.
    Ripple-carry versus carry-look-ahead digit-serial adders2003In: Proc. NORCHIP'03, 2003, p. 264-267Conference paper (Refereed)
  • 327.
    Karlsson, Magnus
    et al.
    Dept. Tech., Univ. Kalmar.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Kulesza, Wlodek
    Dept. Tech., Univ. Kalmar.
    Algorithm transformations in design of digit-serial FIR filters2005In: IEEE Workshop Signal Processing Systems Design and Implementation, SIPS'05, 2005, , p. 81-86p. 81-86Conference paper (Refereed)
    Abstract [en]

    Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.

  • 328.
    Karlsson, Magnus
    et al.
    ISY .
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Kulesza, Wlodek
    Univ. Kalmar.
    Pipelining of digit-serial processing elements in recursive digital filters2004In: Proc. 6th Nordic Signal Processing Symp., NORSIG'04, 2004, , p. 129-132p. 129-132Conference paper (Refereed)
    Abstract [en]

    In this paper, performance trade-offs between throughput, and energy consumption, in implementation of recursive digital filters are presented. Digit-serial arithmetic with different degree of pipelining are used in the implementions. As a demonstration object, a bireciprocal third-order lattice wave digital filter is used. Simulations with HSPICE show that a maximum throughput is obtained using pipelined processing elements with a digit-size equal to the fractional bits in the filter coefficient. The use of non-pipelined processing elements yields minimum energy consumption. A trade-off between throughput and energy consumption can be made by pipelining only some of the processing elements.

  • 329.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A robust differential logic style with NMOS logic nets1997In: Proc. IEE Int. Workshop on Signal Processing, IWSSIP'97, 1997, p. 61-64Conference paper (Refereed)
    Abstract [en]

    In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.

  • 330.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and implementation of a complex multiplier using distributed arithmetic1997In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'97, 1997, p. 222-231Conference paper (Refereed)
    Abstract [en]

    We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm2 in a double-metal 0.8 μm process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively

  • 331.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of bit-serial adders using robust differential logic1997In: Proc. NORCHIP'97, 1997, p. 366-373Conference paper (Refereed)
    Abstract [en]

    In this paper two bit-serial carry save adders are implemented using a recently proposed differential logic style. The clocking scheme uses a single clock phase with non-precharged stages of logic that may be merged with the latches or the flip-flops. A novel flip-flop structure is used in one of the adders, which significantly lowers the number of clocked transistors. The logic style used in the adder realizations suits high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS. The logic style is also robust for clock slope and yields a data noise margin equal to Vdd/2. The adders reached a maximal clock frequency of 300 MHz in a 0.8 mm process with a 3.0 V power supply voltage.

  • 332.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-swing charge recycle bus drivers1998In: Proc. 1998 IEEE Int. Symp. on Circuits and Systems, ISCAS'98, 1998, p. II-117-II-120Conference paper (Refereed)
    Abstract [en]

    In this paper two robust bus drivers combining low-swing and semi-adiabatic charge recycling technique are presented. The drivers use a novel concept with Schmitt-triggers as voltage sensors. Hence, voltage references are not required. The drivers reduces the power consumption by 55 and 72 percent, respectively.

  • 333.
    Karlsson, Magnus
    et al.
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Novel low-swing bus-drivers and charge-recycle architectures1997In: IEEE Workshop on Signal Processing Systems, SIPS 97, 1997, p. 141-150Conference paper (Refereed)
    Abstract [en]

    In this paper novel single-rail low-swing bus-drivers based on schmitt-triggers as voltage level sensors are presented. Two novel 4-transistor schmitt-triggers with non-symmetrical trigger-voltage levels are also proposed. The power dissipation for the single rail low-swing bus-driver is reduced by 48 percent compared to a full-swing driver. Finally, two novel semi-adiabatic charge-recycle circuits are proposed. The power savings for these circuits are 45 and 65 percent, respectively. A data rate of 200 Mbit/s per driver has been reached in a double metal 0.8 μm process.

  • 334.
    Karlsson, Sara
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Micro NPU for Baseband Interconnect2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The aim of this work is to investigate the possibility to implement a configurable NPU (Network Processing Unit) in the next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture). The NPU is constructed so that it can be configured for either Ethernet or xIO-s, as either a transmitter or a receiver. The motive for doing the work is that many protocols have similar functions and there could be possible advantages to have a configurable protocol choice in future hardware.

    A model of a NPU will be created in SystemC using the TLM 2.0 interface. The model will be analyzed to evaluate its complexity regarding a possible modification to also make it configurable for CPRI.

    The result that is presented is that it would be possible to implement a configurable NPU in the future EMCAs. The result is based on the conclusion that the protocols use many similar functions and most of the blocks could be made configurable for use with different protocols. Configurable blocks would benefit a configurable NPU as it would require fewer resources than separate blocks for each protocol.

    Download full text (pdf)
    fulltext
  • 335.
    Kashif, Ahsan-Ullah
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials.
    Arnborg, T.
    Johansson, Thomas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Wahab, Qamar Ul
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials.
    A new large signal simulation technique to study non-linear effects of microwave power transistor2007In: International Semiconductor Device Research Symposium 2007 ISDRS-07,2007, IEEE , 2007Conference paper (Refereed)
  • 336.
    Keller, Markus
    Linköping University, Department of Electrical Engineering, Electronics System.
    Connecting a DE2 board with a 5-6k interface board containing an ADC for digital data transmission2011Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    The goal of this bachelor thesis work was to establish a cable connection between an analogue interface board, containing a 16 bit analogue to digital converter, and a DE2 board in order to allow for digital data transmission between the two boards.

    The DE2 board includes an FPGA which was configured to contain a Nios II softcore microprocessor for handling the tasks of reading and saving the 16 bit digital words transmitted over the cable as well as controlling the analogue to digital converter on the interface board.

    During the project work various tasks had to be fulfilled which included soldering the cable for parallel transmission of the 16 bit digital data words and the control signals between the boards as well as adjusting the analogue interface board with the correct voltage supplies and jumper settings. Furthermore the hardware circuit insidethe FPGA had to be configured and the program running on the Nios II processor had to be written in C language.

    Download full text (pdf)
    FULLTEXT01
  • 337.
    Keshmiri, Vahid
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Study of the Memristor Models and Applications2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Before 1971, all the electronics were based on three basic circuit elements. Until a professor from UCBerkeley reasoned that another basic circuit element exists, which he called memristor; characterized bythe relationship between the charge and the flux-linkage. A memristor is essentially a resistor withmemory. The resistance of a memristor (memristance) depends on the amount of current that is passingthrough the device. In 2008, a research group at HP Labs succeeded to build an actual physical memristor. HP's memristorwas a nanometer scale titanium dioxide thin film, composed of two doped and undoped regions,sandwiched between two platinum contacts. After this breakthrough, a huge amount of research startedwith the aim of better realization of the device and discovering more possible applications of thememristor. In this report, it is attempted to cover a proper amount of information about the history, introduction,implementation, modeling and applications of the device. But the main focus of this study is onmemristor modeling. Four papers on modeling of the memristor were considered, and since there wereno cadence models available in the literature at the time, it was decided to develop some cadencemodels. So, cadence models from the mentioned papers were designed and simulated. From the samemodeling papers some veriloga models were written as well. Unfortunately, due to some limitation of thedesign tool, some of the models failed to provide the expected results, but still the functioning modelsshow satisfactory results that can be used in the circuit simulations of memristors.

    Download full text (pdf)
    fulltext
  • 338.
    Khalid, Muhammad Umer
    Linköping University, Department of Electrical Engineering, Electronics System.
    Multilevel Gain Cell Arrays for Fault-Tolerant VLSI Systems2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Embedded memories dominate area, power and cost of modern very large scale integrated circuits system on chips ( VLSI SoCs). Furthermore, due to process variations, it becomes challenging to design reliable energy efficient systems. Therefore, fault-tolerant designs will be area efficient, cost effective and have low power consumption. The idea of this project is to design embedded memories where reliability is intentionally compromised to increase storage density.

    Gain cell memories are smaller than SRAM and unlike DRAM they are logic compatible. In multilevel DRAM storage density is increased by storing two bits per cell without reducing feature size. This thesis targets multilevel read and write schemes that provide short access time, small area overhead and are highly reliable. First, timing analysis of reference design is performed for read and write operation. An analytical model of write bit line (WBL) is developed to have an estimate of write delay. Replica technique is designed to generate the delay and track variations of storage array. Design of replica technique is accomplished by designing replica column, read and write control circuits. A memory controller is designed to control the read and write operation in multilevel DRAM. A multilevel DRAM is with storage capacity of eight kilobits is designed in UMC 90 nm technology. Simulations are performed for testing and results are reported for energy and access time. Monte Carlo analysis is done for variation tolerance of replica technique. Finally, multilevel DRAM with replica technique is compared with reference design to check the improvement in access times.

    Download full text (pdf)
    mldram
  • 339.
    Khan, Azam
    Linköping University, Department of Electrical Engineering, Electronics System.
    Algorithm study and Matlab model for  CCITT Group4 TIFF Image Compression2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Smart cameras are part of many automated system for detection and correction in various systems. They can be used for detecting unwanted particles inside a fuel tank or may be placed on an airplane engine to provide protection from any approaching obstacle. They can also be used to detect a finger print or other biometric identification on a document or in some video domain. These systems usually have a very sensitive fast processing nature, to stop some ongoing information or extract some information. Image compression algorithms are used  for  the  captured  images to enable fast communication between different nodes i.e. the cameras and the processing units. Nowadays these algorithms are very popular with sensor based smart camera. The challenges associated with these networks are fast communication of these images between different nodes or to a centralized system. Thus a study is provided for an algorithm used for this purpose. In-depth study and Matlab modeling of CCITT group4 TIFF is the target of this thesis. This work provides detail study about the CCITT TIFF algorithms and provides a Matlab model for the compression algorithm for monochrome images.

    The compressed images will be of a compression ratio about 1:15 which will help in fast communication and computation of these images.  A developed set of 8 test images with different characteristics in size and dimension is compressed by the Matlab model implementing the CCITT group4 TIFF. These compressed images are then compared to same set of images compressed by other algorithms to compare the compression ratio.

     

    Download full text (pdf)
    FULLTEXT02
  • 340.
    Khan, Muhammad Awais
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Study on the Aliasing-image Problem in I/Q Modulators Employing RF-DACs2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In today’s world of high-speed communication, data-converters are playing a vital role. The purpose of this project is to analyze the aliasing image problem that occurs in quadrature I/Q modulators utilizing radio frequency digital-to-analog converters (RF-DACs). The RF-DAC is considered to be high-speed DAC that operates in higher GHz region. These high performance DACs are becoming the most essential part of the upcoming future communication devices like next generation radars and telecommunication systems. Some I/Q modulators are implemented in this thesis. The aim is to identify the unwanted signal that is trying to distort the desired output.

    In this thesis, the work is divided into two main parts. First is the aliasing image verification and second is the implementation of the I/Q modulators. Begin with the assessment of the aliasing image through sketching the spectrum using Matlab tools. Also mathematically the calculation is derived to support the flow. In the next part, four different architectures are implemented focusing on image rejection ratio (IRR) calculation while the maximum achievable rejection ratio is 119 dB using the RF-DAC. Lastly the effect of discrete local oscillation (LO) is shown. A comparison plot is drawn, comparing the effect of a discrete-LO at different bit levels vs. IRR variation. It shows a nice picture of IRR dependence on the perfect matching and not on the signal shaping. 

    Download (pdf)
    Masters thesis
  • 341.
    Khan, Shehryar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Awan, Muhammad Asfandyar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Study on Zero-Crossing-Based ADCs for Smart Dust Applications2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.

    Download full text (pdf)
    fulltext
  • 342.
    Kihlgren, Alexander
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    System för avlyssning, modifiering och överföring av analoga signaler2013Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [sv]

    I detta examensarbete har ett system utvecklats som samplar och digitaliserar en högfrekvent analog signal och lagrar de samplade värdena i ett minne. Systemet genererar en analog utsignal genom att antingen direkt omvandla de samplade värdena eller genom att använda sampels lagrade i minnet som källa för omvandlingen. Det går då att använda systemet både som en passiv länk eller som en signalkälla.

    En triggfunktion har implementerats för att på ett effektivt sätt ge möjlighet att fylla minnet med för användaren intressanta delar av en signal. Arbetet går även ut på att undersöka om ett FPGA-kort av typen Stratix II DSP Development Kit är ett lämpligt utvecklingskort för att ta fram en prototyp av systemet. Kortet har undersökts med avseende på olika begränsningar för det utvecklade systemet, till exempel vilka frekvenser en insignal kan samplas i.

    Ett annat användningsområdet för systemet är möjligheten att få alla sampels lagrade på kortet presenterat i en textfil på en ansluten PC. Detta för att ge möjlighet att analysera eller modifiera den lagrade signalen och därefter kunna kopiera tillbaka filens innehåll till FPGA-kortet. Härmed kan en modifierad eller egen signal användas som källa till utsignalen och helt ersätta systemets insignal.

    Download full text (pdf)
    System för avlyssning, modifiering och överföring av analoga signaler
  • 343.
    Korishe, Abdulah
    Linköping University, Department of Electrical Engineering, Electronics System.
    A Driver Circuit for Body-Coupled Communication2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The main concept of Body-Coupled Communication (BCC) is to transmit the electrical information through the human body as a communication medium by means of capacitive coupling. Nowadays the current research of wireless body area network are expanding more with the new ideas and topologies for better result in respect to the low power and area, security, reliability and sensitivity since it is first introduced by the Zimmerman in 1995. In contrast with the other existing wireless communication technology such as WiFi, Bluetooth and Zigbee, the BCC is going to increase the number of applications as well as solves the problem with the cell based communication system depending upon the frequency allocation. In addition, this promising technology has been standardized by a task group named IEEE 802.15.6 addressing a reliable and feasible system for low power in-body and on-body nodes that serves a variety of medical and non medical applications.

    The entire BAN project is divided into three major parts consisting of application layer, digital baseband and analog front end (AFE) transceiver. In the thesis work a strong driver circuit for BCC is implemented as an analog front end transmitter (Tx). The primary purpose of the study is to transmit a strong signal as the signal is attenuated by the body around 60 dB. The Driver circuit is cascaded of two single-stage inverter and an identical inverter with drain resistor. The entire driver circuit is designed with ST65 nm CMOS technology with 1.2 V supply operated at 10 MHz frequency, has a driving capability of 6 mA which is the basic requirement. The performance of the transmitter is compared with the other architecture by integrating different analysis such as corner analysis, noise analysis and eye diagram. The cycle to cycle jitter is 0.87% which is well below to the maximum point and the power supply rejection ratio (PSRR) is 65 dB indicates the good emission of supply noise. In addition, the transmitter does not require a filter to emit the noise because the body acts like a low pass filter.

    In conclusion the findings of the thesis work is quite healthy compared to the previous work. Finally, there is some point to improve for the driver circuit in respect to the power consumption, propagation delay and leakage power in the future.   

    Download full text (pdf)
    A Driver Circuit for Body-Coupled Communication
  • 344.
    Kota Rajasekhar, Rakesh
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Parallel Hardware for Sampling Based Nonlinear Filters in FPGAs2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Particle filters are a class of sequential Monte-Carlo methods which are used commonly when estimating various unknowns of the time-varying signals presented in real time, especially when dealing with nonlinearity and non-Gaussianity in BOT applications. This thesis work is designed to perform one such estimate involving tracking a person using the road information available from an IR surveillance video. In this thesis, a parallel custom hardware is implemented in Altera cyclone IV E FPGA device utilizing SIRF type of particle filter. This implementation has accounted how the algorithmic aspects of this sampling based filter relate to possibilities and constraints in a hardware implementation. Using 100MHz clock frequency, the synthesised hardware design can process almost 50 Mparticles/s. Thus, this implementation has resulted in tracking the target, which is defined by a 5-dimensional state variable, using the noisy measurements available from the sensor.

    Download full text (pdf)
    fulltext
  • 345.
    Kulig, Gabriel
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wallin, Gustav
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    R/2R DAC Nonlinearity Compensation2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The resistor ladder (R/2R) digital-to-analogue converter (DAC) architecture is often used in high performance audio solutions due to its low-noise performance. Even high-end R/2R DACs suffer from static nonlinearity distortions. It was suspected that compensating for these nonlinearities would be possible. It was also suspected that this could improve audio quality in audio systems using R/2R DACs for digital-to-analogue (A/D) conversion.

    Through the use of models of the resistor ladder architecture a way of characterizing and measuring the faults in the R/2R DAC was created. A compensation algorithm was developed in order to compensate for the nonlinearities. The performance of the algorithm was simulated and an implementation of it was evaluated using an audio evaluation instrument.

    The results presented show that it is possible to increase linearity in R/2R DACs by compensating for static nonlinearity distortions. The increase in linearity can be quite significant and audible for the trained ear.

    Download full text (pdf)
    fulltext
  • 346.
    Källström, Petter
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-Complexity Rotators for the FFT Using Base-3 Signed Stages2012In: APCCAS 2012 : 2012 IEEE Asia Pacific Conference on Circuits and Systems, Piscataway, N.J., USA: IEEE , 2012, p. 519-522Conference paper (Refereed)
    Abstract [en]

    Rotations by angles that are fractions of the unit circle find applications in e.g. fast Fourier transform (FFT) architectures. In this work we propose a new rotator that consists of a series of stages. Each stage calculates a micro-rotation by an angle corresponding to a power-of-three fractional parts. Using a continuous powers-of-three range, it is possible to carry out all rotations required. In addition, the proposed rotators are compared to previous approaches, based of shift-and-add algorithms, showing improvements in accuracy and number of adders.

    Download full text (pdf)
    fulltext
  • 347.
    Källström, Petter
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Magnitude Scaling for Increased SFDR in DDFS2011In: 29th Norchip Conference, Lund, Sweden, 14-15 November 2011, IEEE , 2011, p. 1-4Conference paper (Refereed)
    Abstract [en]

    When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding.This results in uncontrolled rounding of up to 0.5 LSB, causing some noise.In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB.

    Download full text (pdf)
    fulltext
  • 348.
    Lababidi, Mohamed
    Linköping University, Department of Electrical Engineering, Electronics System.
    Designing a Low Power Regulator for Smart Dust2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The revolutionary progress that happened recently in the micro-electro mechanicalsystems (MEMS) field and the complementary metal-oxide-semiconductor(CMOS) integrated circuits has made it possible to produce low-cost, low-powerand small size processing circuits. Utilizing wireless communication theory allowsthose circuits to send their data over a network. This wireless sensor network isknown as "Smart Dust".

    Each wireless sensor node in the network is indicated as "mote". It consistsof several components: sensors, micro-processors, radio transceivers and a powermanagement unit. The power management unit can be divided into several partsincluding battery, power control and regulator. The purpose of the regulator is tosupply a constant reliable voltage to the other parts in the mote as most of thedevices have voltage limits that need to be considered to guarantee producing arobust long-life mote.

    In this thesis designing a low-power regulator is investigated. The goal of thethesis is to design a regulator that can handle the high-voltage acquired froman energy harvest unit using only 65-nm core transistors. This allows an easierproduction process that results in a low-cost fully-integrated chip. The regulatorarchitecture to be used is a simple linear regulator.

    The report highlights the theoretical background, the challenges of the analogdesign and presents the results of the simulation that were ran using cadence designsystem software on schematic level.

    Download full text (pdf)
    fulltext
  • 349.
    Laddomada, Massimiliano
    et al.
    California State University Los Angeles.
    Jovanovic Dolecek, Gordana
    University of Sarajevo.
    Yong Ching, Lim
    USN.
    Luo, Fa-Long
    Element CXI Inc.
    Renfors, Markku
    TUT.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Advanced techniques on multirate signal processing for digital information processing2011In: IET Signal Processing, ISSN 1751-9675, E-ISSN 1751-9683, Vol. 5, no 3, p. 313-315Article in journal (Other academic)
  • 350.
    Lahti, Jimmie
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Tree-Structured Linear-Phase Nyquist FIR Filter Interpolators and Decimators2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The master thesis is based upon a new type of linear-phase Nyquist finitie impulse responseinterpolator and decimator implemented using a tree-structure. The tree-structure decreasesthe complexity, considerably, compared to the ordinary single-stage interpolator structure.The computational complexity is comparable to a multi-stage Nyquist interpolator structure,but the proposed tree-structure has slightly higher delay. The tree-structure should still beconsidered since it can interpolate with an arbitrary number and all subfilters operate at thebase rate which is not the case for multi-stage Nyquist interpolators.

    Download full text (pdf)
    Tree-Structured_Linear-Phase_Nyquist_Interpolator
45678910 301 - 350 of 602
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf