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  • 301.
    Liu, Dake
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nordqvist, Ulf
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Configuration-based architecture for high speed and general-purpose protocol processing1999In: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, p. 540-547Conference paper (Refereed)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

  • 302.
    Liu, Dake
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Söderquist, Ingemar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Fully flexible baseband DSP processors for future SDR/JTRS2005In: Western European Armaments Organization WEAO,2005, 2005Conference paper (Other academic)
  • 303.
    Lopez, Sergio
    et al.
    Elektroniska komponenter Linköpings universitet.
    Otero, Sergio
    Elektroniska komponenter Linköpings universitet.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Direct sampling receiver font-end for the VHF band.2005In: RadioVetenskap och Kommunikation,2005, 2005, p. 281-284Conference paper (Refereed)
  • 304.
    Maddula, Ravi
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Near threshold operation of 16-bit adders in 65nm CMOStechnology2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The main objective of the thesis is to implement different architectures of 16-bit adders such as; Ripple CarryAdder (RCA), Manchester Carry Chain Adder (MCCA) and Kogge Stone Adder (KSA), in 65nm CMOS technology and to study their performance in terms of power, operating frequency and speed at near threshold operating regions. The performance of these adders are evaluated and compared with each other and a final conclusion is made as to which adder structure is more suitable for implementation in a 65nmtechnology for low power applications. Several optimisation techniques are performed for the adders to reduce the delay and power consumption. Propagation delay is the most critical or essential parameter to be considered, hence, to minimise the delay of the adder, a technique called sizing and ordering are required for the transistors. The purpose of the thesis is to make a fair comparison among adders over several metrics which include linearity, delay and power.

    Simulation results of MCCA achieved a greater significant performance upon or over RCA and KSA, and proved it is the best suitable adder for low power applications.

  • 305.
    Malmqvist, Robert
    et al.
    FOI, Linköping.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    SiGe BiCMOS LNA´s and tunable active filter for future wide-band multi-purposte array antennas.2003In: GigaHerz 2003,2003, 2003Conference paper (Other academic)
  • 306.
    Malmqvist, Robert
    et al.
    FOI.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Samuelsson, Carl
    FOI.
    Alfredson, Mattias
    FOI.
    Some important aspects on the design of active microwave filters using standard RF silicon process technologies.2004In: European Microwave Conference,2004, Piscataway: IEEE, Inc. , 2004, p. 941-Conference paper (Refereed)
  • 307.
    Mamor, M
    et al.
    Chalmers Univ Technol, Dept Phys, MC2, S-41296 Gothenburg, Sweden Univ Pretoria, Dept Phys, ZA-0002 Pretoria, South Africa Gothenburg Univ, S-41296 Gothenburg, Sweden Natl Def Res Estab, Dept Microwave Technol, S-58111 Linkoping, Sweden Chalmers Univ Technol, Dept Microelect ED, Solid State Elect Lab, S-41296 Gothenburg, Sweden.
    Ouacha, H
    Chalmers Univ Technol, Dept Phys, MC2, S-41296 Gothenburg, Sweden Univ Pretoria, Dept Phys, ZA-0002 Pretoria, South Africa Gothenburg Univ, S-41296 Gothenburg, Sweden Natl Def Res Estab, Dept Microwave Technol, S-58111 Linkoping, Sweden Chalmers Univ Technol, Dept Microelect ED, Solid State Elect Lab, S-41296 Gothenburg, Sweden.
    Willander, Magnus
    Linköping University, The Institute of Technology. Linköping University, Department of Science and Technology.
    Auret, FD
    Chalmers Univ Technol, Dept Phys, MC2, S-41296 Gothenburg, Sweden Univ Pretoria, Dept Phys, ZA-0002 Pretoria, South Africa Gothenburg Univ, S-41296 Gothenburg, Sweden Natl Def Res Estab, Dept Microwave Technol, S-58111 Linkoping, Sweden Chalmers Univ Technol, Dept Microelect ED, Solid State Elect Lab, S-41296 Gothenburg, Sweden.
    Goodman, SA
    Chalmers Univ Technol, Dept Phys, MC2, S-41296 Gothenburg, Sweden Univ Pretoria, Dept Phys, ZA-0002 Pretoria, South Africa Gothenburg Univ, S-41296 Gothenburg, Sweden Natl Def Res Estab, Dept Microwave Technol, S-58111 Linkoping, Sweden Chalmers Univ Technol, Dept Microelect ED, Solid State Elect Lab, S-41296 Gothenburg, Sweden.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Sveinbjornsson, E
    Chalmers Univ Technol, Dept Phys, MC2, S-41296 Gothenburg, Sweden Univ Pretoria, Dept Phys, ZA-0002 Pretoria, South Africa Gothenburg Univ, S-41296 Gothenburg, Sweden Natl Def Res Estab, Dept Microwave Technol, S-58111 Linkoping, Sweden Chalmers Univ Technol, Dept Microelect ED, Solid State Elect Lab, S-41296 Gothenburg, Sweden.
    High-energy He-ion irradiation-induced defects and their influence on the noise behavior of Pd/n-Si1-xGex Schottky junctions2000In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 76, no 25, p. 3750-3752Article in journal (Refereed)
    Abstract [en]

    We report on the electrical properties of defects introduced by high-energy 5.4 MeV He ions in n-type strained n-SiGe and the impact of this irradiation on the noise properties of Pd/n-Si1-xGex Schottky barrier diodes (SBDs). From the deep level transient spectroscopy measurements, the main defects EA1 and EA2 are observed in both Si and Si0.96Ge0.04 and have energy levels at 0.24 and 0.44 eV, respectively, below the conduction band. EA1 and EA2 have been correlated with the V-V and the P-V pairs, respectively. For both defects EA1 and EA2, the energy level position is found to be the same for x = 0 and 0.04, indicating that such levels are pinned to the conduction band. Furthermore, the impact of the high-energy He-ion irradiation on the electrical noise properties of Pd/n-Si1-xGex SBDs is also studied. From the noise experimental data, the main noise source observed in these irradiated diodes was attributed to the generation-recombination noise inducing an abnormal peak in their noise spectra at around f(1) = 180 Hz. This peak is found to be independent of Ge concentration. (C) 2000 American Institute of Physics. [S0003-6951(00)02125-2].

  • 308.
    Manoj, S.
    et al.
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Differential current sense amplifier.2005Patent (Other (popular science, discussion, etc.))
  • 309.
    Medury, Aditya Sankar
    et al.
    Dpt of Electrical and Computer Engineering University of Alabama.
    Carlsson, Ingvar
    Elektroniska komponenter, ISY Linköpings universitet.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Stensby, John
    Dpt of Electrical and Computer Engineering University of Alabama.
    Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops.2005In: International Conference on VLSI design,2005, Piscaway: IEEE Computer Society press , 2005, p. 842-Conference paper (Refereed)
  • 310.
    Mehdi, Ghulam
    et al.
    CESAT, Islamabad, Pakistan.
    Ahsan, Naveed
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Altaf, Amjad
    CESAT, Islamabad, Pakistan.
    Eghbali, Amir
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering.
    A 403-MHz fully differential class-E amplifier in 0.35 um CMOS for ISM band applications2008In: IEEE East-West Design Test Symposium 2008,2008, 2008, p. 239-242Conference paper (Refereed)
  • 311.
    Mehmood, Nasir
    et al.
    Electronic Devices Linköping University.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An energy-efficient 32-bit multiplier architecture in 90-nm CMOS.2006In: 24th Norchip Conference,2006, IEEE , 2006, p. 35-Conference paper (Refereed)
  • 312.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A CMOS implementation of min-max circuits in current mode and a sample fuzzy application.2004In: IEEE Fuzzy Systems Symposium,2004, Piscataway: IEEE , 2004, p. 941--946Conference paper (Refereed)
  • 313.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Circuit Techniques for On-Chip Clocking and Synchronization2006Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.

    This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.

    List of papers
    1. A New Mesochronous Clocking Scheme for Synchronization in SoC
    Open this publication in new window or tab >>A New Mesochronous Clocking Scheme for Synchronization in SoC
    2004 (English)In: Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS), 2004, Vol. 6, p. 605-608Conference paper, Published paper (Refereed)
    Abstract [en]

    Future System-on-Chips (SoCs) need a new strategy for synchronization and clocking. In large-scale and high-speed systems, the traditional globally synchronous approach is not longer viable, due to severe wire delays. Instead new solutions as "Globally Asynchronous, Locally Synchronous" (GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this paper we present such an approach together with a circuit solution in 0.18 μm CMOS process that allows clocking frequencies up to 5 GHz.

    Series
    , ISSN 1057-7122
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14042 (URN)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05
    2. A Study of Injection Locking in Ring Oscillators
    Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
    2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper, Published paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

    Keywords
    injection locking, ring oscillators, phase noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    3. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, p. 464-467Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    4. A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
    Open this publication in new window or tab >>A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
    2006 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, p. 257-260Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

    Keywords
    CMOS
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14045 (URN)10.1109/SOCC.2006.283893 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    5. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

    Keywords
    quadrature VCO, tuning range, coupled ring oscillators, CMOS
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
  • 314.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    EMI reduction by resonant clock distribution networks2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 315.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power Low-Jitter Clock Generation and Distribution2008Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded.

    The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz.

    In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz.

    List of papers
    1. A Study of Injection Locking in Ring Oscillators
    Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
    2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper, Published paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

    Keywords
    injection locking, ring oscillators, phase noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    2. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

    Keywords
    quadrature VCO, tuning range, coupled ring oscillators, CMOS
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    3. First-Harmonic Injection-Locked Ring Oscillators
    Open this publication in new window or tab >>First-Harmonic Injection-Locked Ring Oscillators
    2006 (English)In: Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), 10-13 September, San José, CA, USA, 2006, p. 733-736Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

    Keywords
    CMOS integrated circuits, frequency multipliers, harmonic oscillators (circuits), injection locked oscillators, logic circuits
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14893 (URN)10.1109/CICC.2006.320927 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    4. A Study of First-Harmonic Injection Locking for On-chip Applications
    Open this publication in new window or tab >>A Study of First-Harmonic Injection Locking for On-chip Applications
    (English)Manuscript (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14894 (URN)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    5. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, p. 464-467Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    6. Jitter Characteristic in Charge Recovery Resonant Clock Distribution
    Open this publication in new window or tab >>Jitter Characteristic in Charge Recovery Resonant Clock Distribution
    2007 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, p. 1618-1625 Article in journal (Refereed) Published
    Abstract [en]

    This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, jitter, resonators
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14898 (URN)10.1109/JSSC.2007.896691 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    7. Low-Power Bufferless Resonant Clock Distribution Networks
    Open this publication in new window or tab >>Low-Power Bufferless Resonant Clock Distribution Networks
    2007 (English)In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, p. 960-963Conference paper, Published paper (Refereed)
    Abstract [en]

    The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

    Place, publisher, year, edition, pages
    Montreal: ReSMiQ, 2007
    Keywords
    CMOS integrated circuits, VLSI, clocks, timing jitter
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14900 (URN)10.1109/MWSCAS.2007.4488725 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
  • 316.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Simultaneous switching noise reduction by resonant clock distribution networks2014In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 47, no 2, p. 242-249Article in journal (Refereed)
    Abstract [en]

    Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.

  • 317.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS2006In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, p. 257-260Conference paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

  • 318.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.5-GHz DLL-based multiphase clock generator in 90-nm CMOS.2008In: Swedish System-on-Chip Conference SSoCC.,2008, 2008Conference paper (Other academic)
  • 319.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, p. 86-89Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.   

  • 320.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode2009In: IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN 0018-9200, Vol. 44, no 7, p. 1907-1913Article in journal (Refereed)
    Abstract [en]

    This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.

  • 321.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Study of First-Harmonic Injection Locking for On-chip ApplicationsManuscript (Other academic)
  • 322.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Study of Injection Locking in Ring Oscillators2005In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

  • 323.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators2006In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

  • 324.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    EMI reduction by resonant clock distribution networks2010In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE , 2010, p. 977-980Conference paper (Refereed)
    Abstract [en]

    In today's automotive vehicles, electromagnetic interference (EMI) from electronic circuits has become a serious concern. The discussion in this paper proves that a clock signal generated by a resonant clock distribution network exhibits better EMI performance compared to that of a conventional buffer-driven clock network. This discussion is supported by analyzing different clock spectrums and using a simple model of simultaneous switching noise (SSN). According to simulation results presented in a 90-nm CMOS process, using a sinusoidal clock instead of a trapezoidal one, the magnitude of the first tone in the spectrum of SSN is reduced at least by 6.7 dB.

  • 325.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    First-harmonic injection locking in ring oscillators.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 326.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    First-Harmonic Injection-Locked Ring Oscillators2006In: Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), 10-13 September, San José, CA, USA, 2006, p. 733-736Conference paper (Other academic)
    Abstract [en]

    This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

  • 327.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Injection-Locked Ring Oscillators.2005In: SSoCC 2005,2005, 2005Conference paper (Other academic)
  • 328.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A multi-segment clocking scheme to reduce on-chip EMI2011In: IEEE International SoC Conference (SoCC), Taipei, Taiwan: IEEE , 2011, p. 251-255Conference paper (Refereed)
    Abstract [en]

    This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.

  • 329.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jitter Characteristic in Charge Recovery Resonant Clock Distribution2007In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, p. 1618-1625 Article in journal (Refereed)
    Abstract [en]

    This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

  • 330.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jitter Characteristic in Resonant Clock Distribution2006In: Proceedings of the 32nd ESSCIRC conference 18-22 September 2006, 2006, p. 464-467Conference paper (Refereed)
  • 331.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power Bufferless Resonant Clock Distribution Networks2007In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, p. 960-963Conference paper (Refereed)
    Abstract [en]

    The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

  • 332.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-power low-jitter bufferless resonant clocking.2007In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper (Refereed)
  • 333.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sadeghifar, Mohammad Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Fredriksson, P.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jansson, C.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Niklaus, F.
    FAUN AB.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low-noise readout circuit in 0.35-μm CMOS for low-cost uncooled FPA infrared network camera2009In: Infrared Technology and Applications XXXV, Proceedings of SPIE - The International Society for Optical Engineering, vol 7298, SPIE - International Society for Optical Engineering, 2009, Vol. 7298, article id 72982FConference paper (Refereed)
    Abstract [en]

    This paper describes a differential readout circuit technique for uncooled Infrared Focal Plane Arrays (IRFPA) sensors. The differential operation allows an efficient rejection of the common-mode noise during the biasing and readout of the detectors. This has been enabled by utilizing a number of blind and thermally-isolated IR bolometers as reference detectors. In addition, a pixel-wise detector calibration capability has been provided in order to allow efficient error corrections using digital signal processing techniques. The readout circuit for a 64×64 test bolometer-array has been designed in a standard 0.35-μm CMOS process. Circuit simulations show that the analog readout at 60 frames/s consumes 30 mW from a 3.3-V supply and results in a noise equivalent temperature difference (NETD) of 125 mK for f/1 infrared optics.

  • 334.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A New Mesochronous Clocking Scheme for Synchronization in SoC2004In: Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS), 2004, Vol. 6, p. 605-608Conference paper (Refereed)
    Abstract [en]

    Future System-on-Chips (SoCs) need a new strategy for synchronization and clocking. In large-scale and high-speed systems, the traditional globally synchronous approach is not longer viable, due to severe wire delays. Instead new solutions as "Globally Asynchronous, Locally Synchronous" (GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this paper we present such an approach together with a circuit solution in 0.18 μm CMOS process that allows clocking frequencies up to 5 GHz.

  • 335.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Söderquist, Ingemar
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reliability Challenges in Avionics due to Silicon Aging2012In: 2012 IEEE 15TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS and SYSTEMS (DDECS), IEEE , 2012, p. 342-347Conference paper (Refereed)
    Abstract [en]

    Todays aviation systems are strongly dependent on electronics. Avionics (i.e., aviation electronics) should be highly reliable due to the nature of their applications. CMOS technology, which is widely used in the fabrication of integrated circuits, is continuously scaled to achieve higher performance and higher integration density (i.e., the well-known Moores law). This scaling property creates new challenges in reliability of avionics. As an example, the aging process is speeded up resulting in shorter time to wear-out. This paper investigates reliability challenges in design of avionics caused by silicon aging. It is shown that in the circuits and systems designed in modern CMOS technology, aging phenomenon have to be considered as a serious concern.

  • 336.
    Mohsin, Taif
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of a predriver for an EDMOS-based Class-D power amplifier2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis addresses the potential of implementing a predriver for class-D power amplifier for WLAN in 65 nm CMOS technology. In total, eight different predrivers have been created using Cadence Virtuoso CAD tools. All designs have been tested using Agilent's Advance Design System (ADS) and simulated using the ADS-Cadence dynamic link. Furthermore, a comparison between the eight designs and the reference design has been done. The examined parameters were output power (Pout), efficiency, and effective area consumption.

    The simulation results show that most of the proposed designs obtain higher output power, higher efficiency, and lower effective area than the reference design. For the reference design, output power of 34.2 dBm, efficiency of 20.8 %, and effective area of 63952 um2 were obtained. For design No.1, the effective area was 31511um2, which was almost half of the area occupied by the reference design. For design No.3, the efficiency was 71.2 %, which was almost 3 and half times higher than the efficiency of the reference design. Furthermore, all designs, except design NO.7, gave more or less the same output power (around 34.4 dBm).

  • 337.
    Mu, Fenghao
    et al.
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Linearized Sub-Optimum Method of Long Wire Interconnections with Uniform Wire Driver1998In: In proceedings of: IEEE International Symposium on Circuits and Systems, 1998, p. 252-255Conference paper (Refereed)
    Abstract [en]

    A simple analysis is made on the delay for a uniform long wire interconnection with distributed RC property. The optimal widths of wire and transistor are investigated under different constraints. The analysis is based on an improved switch model and Elmore delay model. A linearized relation between wire width and transistor width is suggested. Performance comparison is made between the absolute optimum and the suggested method by plotting the loci of the optimum solutions. Results show that the linearized relation can achieve a suboptimum solution quite close to the absolute optimum, and it can be used in the delay calculation.

  • 338. Mu, Fenghao
    et al.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Self-tested self-synchronization circuit for mesochronous clocking2001In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 48, no 2, p. 129-140Article in journal (Refereed)
    Abstract [en]

    In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-╡m CMOS. Comparison is made between STSS-1 and STSS-2.

  • 339.
    Najari, Omid
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Arnborg, Torkel
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Wideband inductorless LNA employing simultaneous 2nd and 3rd order distortion cancellation2010In: Proc. Norchip, Tampere: IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz-5GHz.

  • 340.
    Natarajan, Sreedhar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Emerging Memory Technologies - Mainstream or Hearsay?2005In: IEEE VLSI-TSA International Symposium on VLSI Design,2005, 2005, p. 222-Conference paper (Refereed)
  • 341.
    Natarajan, Sreedhar
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    High Performance and SER Insensitive Memories. Invited paper.2003In: SPIE´s International Symposium on Microelectronics, MWMS, and Nanotechnology, Perth, Australia, 9-12 December., 2003Conference paper (Other academic)
  • 342.
    Natarajan, Sreedhar
    et al.
    MoSys.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Mainstream memory technologies in deep submicron.2004In: IEEE Melecon 2004,2004, Zagreb: University of Zagreb , 2004, p. 175-Conference paper (Refereed)
  • 343.
    Natarajan, Sreedhar
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    SoC Versus SIP: What Makes Sense? Invited paper.2003In: SPIE´s Internatioanl Symposium on Microelectronics, MWMS, and Nanotechnology, Perth, Australia, 9-12 December, 2003Conference paper (Other academic)
  • 344.
    Natarajan, Sreedhar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ultra low power ferroElectric memory for SpC.2003In: Microelectronics: Design, Technology, and Packaging.,2003, Bellingham, WA, USA: SPIE The International Society for Optical Engineering , 2003, p. 144-Conference paper (Refereed)
  • 345.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Design considerations for interface circuits to low-voltage piezoelectric energy harvesters2014Conference paper (Refereed)
    Abstract [en]

    In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm2 and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.

  • 346.
    Nilsson, Emil
    et al.
    Halmstad University.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Envelope Detector for Wake-Up Radio2011In: Swedish System-on-Chip Conference (SSOCC), IEEE Solid-State Circuits Society, 2011Conference paper (Other academic)
  • 347.
    Nilsson, Emil
    et al.
    Halmstad University.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Envelope detector sensitivity and blocking characteristics2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 802-805Conference paper (Refereed)
    Abstract [en]

    This paper presents analytical expressions for the sensitivity of a low power envelope detector driven by a weak RF signal in the presence of a blocking signal. The envelope detector has been proposed for low power Wake-Up radios in applications such as RFID and wireless sensor systems. The theoretical results are verified with simulations of a modern short channel MOS transistor in a commonly used circuit topology. A discussion around a tutorial example of a radio frontend, consisting of an LNA and a detector, is presented. It is shown that the sensitivity of a low power envelope detector can reach -62 dBm with a low power LNA and in presence of a CW blocker.

  • 348.
    Nilsson, Emil
    et al.
    Halmstad University, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Power Consumption of Integrated Low-Power Receivers2014In: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, ISSN 2156-3357, Vol. 4, no 3, p. 273-283Article in journal (Refereed)
    Abstract [en]

    With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.

  • 349.
    Nilsson, Emil
    et al.
    Centre for Research on Embedded Systems (CERES) and Laboratory of Mathematics, Physics, and Electrical Engineering, Halmstad University, Halmstad, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer2013In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, ISSN 2156-3357, Vol. 3, no 1, p. 5-12Article in journal (Other academic)
    Abstract [en]

    An ultra-low power wake-up radio receiver using no oscillators is described. The radio utilizes an envelope detector followed by a baseband amplifier and is fabricated in a 130-nm complementary metal-oxide-semiconductor process. The receiver is preceded by a passive radio-frequency voltage transformer, also providing 50 Ω antenna matching, fabricated as transmission lines on the FR4 chip carrier. A sensitivity of -47 dBm with 200 kb/s on-off keying modulation is measured at a current consumption of 2.3 μ A from a 1 V supply. No trimming is used. The receiver accepts a -13 dBm continuous wave blocking signal, or modulated blockers 6 dB below the sensitivity limit, with no loss of sensitivity.

  • 350.
    Nordqvist, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    On protocol processing.2001In: Conference on Computer Science and Systems Engineering.,2001, 2001, p. 83-89Conference paper (Other academic)
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