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  • 301.
    Gabrielsson, Erik O.
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Janson, Per
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Tybrandt, Klas
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Simon, Daniel T.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Berggren, Magnus
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    A Four-Diode Full-Wave Ionic Current Rectifier Based on Bipolar Membranes: Overcoming the Limit of Electrode Capacity2014Ingår i: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 26, nr 30, s. 5143-5147Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Full-wave rectification of ionic currents is obtained by constructing the typical four-diode bridge out of ion conducting bipolar membranes. Together with conjugated polymer electrodes addressed with alternating current, the bridge allows for generation of a controlled ionic direct current for extended periods of time without the production of toxic species or gas typically arising from electrode side-reactions.

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  • 302.
    Gabrielsson, Erik O.
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Tybrandt, Klas
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Berggren, Magnus
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Polyphosphonium-Based Ion Bipolar Junction Transistors2014Ingår i: Biomicrofluidics, ISSN 1932-1058, E-ISSN 1932-1058, Vol. 8, nr 6, s. 064116-Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Advancements in the field of electronics during the past few decades have inspired the use of transistors in a diversity of research fields, including biology and medicine. However, signals in living organisms are not only carried by electrons, but also through fluxes of ions and biomolecules. Thus, in order to implement the transistor functionality to control biological signals, devices that can modulate currents of ions and biomolecules, i.e. ionic transistors and diodes, are needed. One successful approach for modulation of ionic currents is to use oppositely charged ion-selective membranes to form so called ion bipolar junction transistors (IBJTs). Unfortunately, overall IBJT device performance has been hindered due to the typical low mobility of ions, large geometries of the ion bipolar junction materials, and the possibility of electric field enhanced (EFE) water dissociation in the junction. Here, we introduce a novel polyphosphonium-based anion-selective material into npn-type IBJTs. The new material does not show EFE water dissociation and therefore allows for a reduction of junction length down to 2 μm, which significantly improves the switching performance of the ion transistor to 2 s. The presented improvement in speed as well the simplified design will be useful for future development of advanced iontronic circuits employing IBJTs, for example addressable drug-delivery devices.

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  • 303.
    Gallay, Lucie
    Linköpings universitet, Institutionen för systemteknik.
    Implementation of an FFT algorithm using a soft processor core2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This report deals with the modeling of a part of the communication system based on the IEEE 802.11a standard which represents the next generation of wireless LAN with greater scalability, better interference immunity and significantly higher speed, up to 54 Mbps.

    802.11a uses Orthogonal Frequency Division Multiplexing (OFDM) where modulation is performed by an IFFT and the demodulation by an FFT.

    After modeling the FFT in Matlab and C, the FFT implementation has been validated using a soft microprocessor core by Xilinx (Microblaze) and the results were compared.

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  • 304.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, nr 3, s. 201-210Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 305.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, nr 3, s. 201-210Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunicationapplications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigmadeltamodulators are needed to meet the dynamic performance requirements. This paper presents an oversamplingDAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the highorderone-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limitcycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. Fromour analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator havenon-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients isprovided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented ina 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 306.
    Garcia Torre, Fernando
    Linköpings universitet, Institutionen för systemteknik.
    Investigation of IEEE Standard 802.11 Medium Access Control (MAC) Layer in ad-hoc2006Självständigt arbete på avancerad nivå (magisterexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    This thesis involved a research of mechanisms of MAC layer in the ad-hoc networks environment, the ad-hoc networks in the terminology of the standard are called IBSS Independent Basic Service, these type of networks are very useful in real situation where there are not the possibility of display a infrastructure, when there isn’t a network previous planning.

    The connection to a new network is one of the different with the most common type of Wireless Local Area Networks (WLAN) that are the ones with infrastructure. The connection is established without the presence of a central station, instead the stations discover the others with broadcast messages in the coverage area of each station. In the context of standard 802.11 networks the communication between the stations is peer to peer, only with one hop. To continue with initiation process is necessary the synchronization between the different stations of his timers.

    The other capital mechanism that is treated is the medium access mechanism, to hold a shared and unreliable medium, all the heavy of this issue goes to the distributed coordination function DCF.

    In this moment there is an emergent technology, WIMAX or standard IEEE 802.16, like the standard 802.11 is a wireless communication protocol. Some comparison between the MAC layer mechanisms would be realized between these two standards

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  • 307.
    Garrido Gálvez, Mario
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    A New Representation of FFT Algorithms Using Triangular Matrices2016Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 63, nr 10, s. 1737-1745Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.

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  • 308.
    Garrido Gálvez, Mario
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    The Feedforward Short-Time Fourier Transform2016Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, nr 9, s. 868-872Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief presents the feedforward short-time Fourier transform (STFT). This new approach is based on reusing the calculations of the STFT at consecutive time instants. This leads to significant savings in hardware components with respect to fast Fourier transform based STFTs. Furthermore, the feedforward STFT does not have the accumulative error of iterative STFT approaches. As a result, the proposed feedforward STFT presents an excellent tradeoff between hardware utilization and performance.

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  • 309.
    Garrido Gálvez, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Andersson, Rikard
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem. Linköpings universitet, Tekniska högskolan.
    Qureshi, Fahad
    Tampere University of Technology, Finland.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Multiplierless Unity-Gain SDF FFTs2016Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 24, nr 9, s. 3003-3007Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this brief, we propose a novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. Conversely, this brief proposes unity-gain FFTs without compensation circuits, even when using nonunity-gain rotators. This is achieved by a joint design of rotators, so that the entire FFT is scaled by a power of two, which is then shifted to unity. This reduces the amount of hardware resources of the FFT architecture, while having high accuracy in the calculations. The proposed approach can be applied to any FFT size, and various designs for different FFT sizes are presented.

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  • 310.
    Garrido Gálvez, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Huang, Shen-Jui
    Novatek Corp, Taiwan.
    Chen, Sau-Gee
    Natl Chiao Tung Univ, Taiwan.
    Feedforward FFT Hardware Architectures Based on Rotator Allocation2018Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, nr 2, s. 581-592Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.

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  • 311.
    Garrido Gálvez, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Unnikrishnan, Nanda K.
    Univ Minnesota, MN 55455 USA.
    Parhi, Keshab K.
    Univ Minnesota, MN 55455 USA.
    A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals2018Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, nr 11, s. 1693-1697Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log(2) N - 2 real adders, log(2) N - 2 real multipliers, and N + 9 log(2) N - 19 real delay elements, where N represents the size of the FFT.

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  • 312.
    Garrido, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Acevedo, Miguel
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Challenging the Limits of FFT Performance on FPGAs2014Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.

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  • 313.
    Garrido, Mario
    et al.
    Universidad Politecnica de Madrid, Spain.
    Grajal, J.
    Universidad Politecnica de Madrid, Spain.
    Efficient Memoryless Cordic for FFT Computation2007Ingår i: Efficient Memoryless Cordic for FFT Computation, IEEE , 2007, s. II-113-II-116Konferensbidrag (Refereegranskat)
    Abstract [en]

    A new memoryless CORDIC algorithm for the FFT computation is proposed in this paper. This approach calculates the direction of the micro-rotations from the control counter of the FFT, so the area of the rotator hardly depends on the number of rotations, which is particularly suitable for the computation of FFTs of a high number of points. Moreover, the new CORDIC presents other advantages such as the simplification of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic gain of the CORDIC algorithm. Additionally, the VLSI implementation of the algorithm is a pipeline architecture with high performance in terms of speed, throughput and latency.

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  • 314.
    Garrido, Mario
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Grajal, Jesus
    Univ Politecn Madrid, Spain.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Optimum Circuits for Bit-Dimension Permutations2019Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, nr 5, s. 1148-1160Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform, bit reversal, matrix transposition, stride permutations, and Viterbi decoders.

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  • 315.
    Garrido, Mario
    et al.
    Department of Signal, Systems and Radiocommuncations, Universidad Politecnica de Madrid, Madrid, Spain.
    Parhi, Keshab. K.
    University of Minnesota, USA.
    Grajal, Jesus
    Department of Signal, Systems and Radiocommuncations, Universidad Politecnica de Madrid, Madrid, Spain.
    A Pipelined FFT Architecture for Real-Valued Signals2009Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 56, nr 12, s. 2634-2643Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.

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  • 316.
    Ghani Zadegan, Farrokh
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Analysis and Optimization for Testing Using IEEE P16872010Självständigt arbete på avancerad nivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

     The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors, and the Test Access Port of IEEE Standard 1149.1 mainly used for board test. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path. SIBs make it possible to construct a multitude of different P1687 networks for the same set of instruments, and provide flexibility in test scheduling. The work presented in this thesis consists of two parts. In the first part, analysis regarding test application time is given for P1687 networks while making use of two test schedule types, namely concurrent and sequential test scheduling. Furthermore, formulas and novel algorithms are presented to compute the test time for a given P1687 network and a given schedule type. The algorithms are implemented and employed in extensive experiments on realistic industrial designs. In the second part, design of IEEE P1687 networks is studied. Designing the P1687 network that results in the least test application time for a given set of instruments, is a time-consuming task in the absence of automatic design tools. In this thesis work, novel algorithms are presented for automated design of P1687 networks which are optimized with respect to test application time and the required number of SIBs. The algorithms are implemented and demonstrated in experiments on industrial SOCs. 

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  • 317.
    Ghosh, Arpan
    et al.
    Linköpings universitet, Matematiska institutionen, Matematik och tillämpad matematik. Linköpings universitet, Tekniska fakulteten.
    Kozlov, Vladimir
    Linköpings universitet, Matematiska institutionen, Matematik och tillämpad matematik. Linköpings universitet, Tekniska fakulteten.
    Nazarov, Sergey
    Linköpings universitet, Matematiska institutionen, Matematik och tillämpad matematik. Linköpings universitet, Tekniska fakulteten. St Petersburg State Univ, Russia; RAS, Russia.
    Rule, David
    Linköpings universitet, Matematiska institutionen, Matematik och tillämpad matematik. Linköpings universitet, Tekniska fakulteten.
    A TWO-DIMENSIONAL MODEL OF THE THIN LAMINAR WALL OF A CURVILINEAR FLEXIBLE PIPE2018Ingår i: Quarterly Journal of Mechanics and Applied Mathematics, ISSN 0033-5614, E-ISSN 1464-3855, Vol. 71, nr 3, s. 349-367Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    We present a two-dimensional model describing the elastic behaviour of the wall of a curved flexible pipe. The wall has a laminate structure consisting of several anisotropic layers of varying thickness and is assumed to be much smaller in thickness than the radius of the channel which itself is allowed to vary. Our two-dimensional model takes the interaction of the wall with any surrounding or supporting material and the fluid flow into account and is obtained via a dimension reduction procedure. The curvature and twist of the pipes axis as well as the anisotropy of the laminate wall present the main challenges in applying the dimension reduction procedure so plenty of examples of canonical shapes of pipes and their walls are supplied with explicit systems of differential equations at the end.

  • 318.
    Gising, Andreas
    Linköpings universitet, Institutionen för systemteknik.
    MALLS - Mobile Automatic Launch and Landing Station for VTOL UAVs2008Självständigt arbete på avancerad nivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    The market for vertical takeoff and landing unmanned aerial vehicles, VTOL UAVs, is growing rapidly. To reciprocate the demand of VTOL UAVs in offshore applications, CybAero has developed a novel concept for landing on moving objects called MALLS, Mobile Automatic Launch and Landing Station. MALLS can tilt its helipad and is supposed to align to either the horizontal plane with an operator adjusted offset or to the helicopter skids. Doing so, eliminates the gyroscopic forces otherwise induced in the rotordisc as the helicopter is forced to change attitude when the skids align to the ground during landing or when standing on a jolting boat with the rotor spun up. This master’s thesis project is an attempt to get the concept of MALLS closer to a quarter scale implementation. The main focus lies on the development of the measurement methods for achieving the references needed by MALLS, the hori- zontal plane and the plane of the helicopter skids. The control of MALLS is also discussed. The measurement methods developed have been proved by tested implementations or simulations. The theories behind them contain among other things signal filtering, Kalman filtering, sensor fusion and search algorithms. The project have led to that the MALLS prototype can align its helipad to the horizontal plane and that a method for measuring the relative attitude between the helipad and the helicopter skids have been developed. Also suggestions for future improvements are presented.

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  • 319.
    Gladh, Susanna
    Linköpings universitet, Institutionen för systemteknik, Datorseende.
    Visual Tracking Using Deep Motion Features2016Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    Generic visual tracking is a challenging computer vision problem, where the position of a specified target is estimated through a sequence of frames. The only given information is the initial location of the target. Therefore, the tracker has to adapt and learn any kind of object, which it describes through visual features used to differentiate target from background. Standard appearance features only capture momentary visual information. This master’s thesis investigates the use of deep features extracted through optical flow images processed in a deep convolutional network. The optical flow is calculated using two consecutive images, and thereby captures the dynamic nature of the scene. Results show that this information is complementary to the standard appearance features, and improves performance of the tracker. Deep features are typically very high dimensional. Employing dimensionality reduction can increase both the efficiency and performance of the tracker. As a second aim in this thesis, PCA and PLS were evaluated and compared. The evaluations show that the two methods are almost equal in performance, with PLS actually receiving slightly better score than the popular PCA. The final proposed tracker was evaluated on three challenging datasets, and was shown to outperform other state-of-the-art trackers.

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  • 320.
    Goman, Anna
    Linköpings universitet, Institutionen för systemteknik.
    Waveform Generator Implemented in FPGA with an Embedded Processor2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more.

    The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz.

    The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.

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  • 321.
    Gommans, HHP
    et al.
    Eindhoven University of Technology, Netherlands.
    Kemerink, Martijn
    Eindhoven University of Technology, Netherlands.
    Schilders, WHA
    Eindhoven University of Technology, Netherlands.
    Universality of ac conduction for generalized space-charge transport in ordered solids2005Ingår i: Physical Review B. Condensed Matter and Materials Physics, ISSN 1098-0121, E-ISSN 1550-235X, Vol. 72, nr 16, artikel-id 165110Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    On numerous nonmetallic systems, the ac conductivity is observed to follow an approximate power law behavior sigma(omega)=omega(s) with 0 amp;lt; s amp;lt;= 1. We show that the presence of nonlimiting, i.e., ohmic, contacts on the sample necessarily leads to these characteristics. The ac conductivity curves are obtained by the numerical solution of the complete set of time-dependent drift-diffusion equations. The calculated ac conductivity curves can be converted into quasiuniversal master curves by application of the Taylor-Isard scaling law for an arbitrary temperature dependence of the mobility. Our results demonstrate that space-charge transport can lead to the commonly observed power law and scaling behaviors without incorporating disorder. Nevertheless, the implications of disorder are discussed and they are expected to increase the range over which the power law behavior extends.

  • 322.
    Gomony, Manil Dev
    Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem.
    An adaptive solution for power efficiency and QoS optimization in WLAN 802.11n2010Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    The wide spread use of IEEE Wireless LAN 802.11 in battery operated mobile devices introduced the need of power consumption optimization while meeting Quality-of-Service (QoS) requirements of applications connected through the wireless network. The IEEE 802.11 standard specifies a baseline power saving mechanism, hereafter referred to as standard Power Save Mode (PSM), and the IEEE 802.11e standard specifies the Automatic Power Save Delivery (APSD) enhancement which provides support for real-time applications with QoS requirements. The latest amendment to the WLAN 802.11 standard is the IEEE 802.11n standard which enables the use of much higher data rates by including enhancements in the Physical and MAC Layer. In this thesis, different 802.11n MAC power saving and QoS optimization possibilities are analyzed comparing against existing power saving mechanisms.

    Initially, the performance of the existing power saving mechanisms PSM and Unscheduled-APSD (UAPSD) are evaluated using the 802.11n process model in the OPNET simulator and the impact of frame aggregation feature introduced in the MAC layer of 802.11n was analyzed on these power saving mechanisms. From the performance analysis it can be concluded that the frame aggregation will be efficient under congested network conditions. When the network congestion level increases, the signaling load in UAPSD saturates the channel capacity and hence results in poor performance compared to PSM. Since PSM cannot guarantee the minimum QoS requirements for delay sensitive applications, a better mechanism for performance enhancement of UAPSD under dynamic network conditions is proposed.

    The functionality and performance of the proposed algorithm is evaluated under different network conditions and using different contention settings. From the performance results it can be concluded that, by using the proposed algorithm the congestion level in the network is reduced dynamically thereby providing a better power saving and QoS by utilizing the frame aggregation feature efficiently.

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  • 323.
    Gong, Shaofang
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska fakulteten.
    Östh, Joakim
    Serban, Adriana
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska fakulteten.
    Karlsson, Magnus
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska fakulteten.
    Six-port Modulators for High Speed Data2016Ingår i: GigaHertz Symposium 2016, Linköping, 2016, s. 65-Konferensbidrag (Refereegranskat)
    Abstract [en]

    Results from our recent study on six-port modulators and demodulators for high speed data transmission have shown that the six-port radio technology has the potential to catch up the speed of the Internet. This is due to the fact that the binary baseband data, either electrical or optical, can be converted directly to high order modulated RF signal without any D/A conversion. The six-port modulators and demodulators can also be designed with differential circuitry to improve the signal-to-noise ration and dynamic range. In addition, antennae and radio front-end components can be integrated on the same substrate with the six-port modulator and demodulator.

  • 324.
    González, David Muñoz
    Linköpings universitet, Institutionen för systemteknik.
    Discovering unknown equations that describe large data sets using genetic programming techniques2005Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    FIR filters are widely used nowadays, with applications from MP3 players, Hi-Fi systems, digital TVs, etc. to communication systems like wireless communication. They are implemented in DSPs and there are several trade-offs that make important to have an exact as possible estimation of the required filter order.

    In order to find a better estimation of the filter order than the existing ones, genetic expression programming (GEP) is used. GEP is a Genetic Algorithm that can be used in function finding. It is implemented in a commercial application which, after the appropriate input file and settings have been provided, performs the evolution of the individuals in the input file so that a good solution is found. The thesis is the first one in this new research line.

    The aim has been not only reaching the desired estimation but also pave the way for further investigations.

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  • 325.
    Grelsson, Bertil
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorseende. Linköpings universitet, Tekniska fakulteten.
    Felsberg, Michael
    Linköpings universitet, Institutionen för systemteknik, Datorseende. Linköpings universitet, Tekniska fakulteten.
    Performance boost in Convolutional Neural Networks by tuning shifted activation functions2017Rapport (Övrigt vetenskapligt)
    Abstract [en]

    The Exponential Linear Unit (ELU) has been proven to speed up learning and improve the classification performance over activation functions such as ReLU and Leaky ReLU for convolutional neural networks. The reasons behind the improved behavior are that ELU reduces the bias shift, it saturates for large negative inputs and it is continuously differentiable. However, it remains open whether ELU has the optimal shape and we address the quest for a superior activation function.

    We use a new formulation to tune a piecewise linear activation function during training, to investigate the above question, and learn the shape of the locally optimal activation function. With this tuned activation function, the classification performance is improved and the resulting, learned activation function shows to be ELU-shaped irrespective if it is initialized as a RELU, LReLU or ELU. Interestingly, the learned activation function does not exactly pass through the origin indicating that a shifted ELU-shaped activation function is preferable. This observation leads us to introduce the Shifted Exponential Linear Unit (ShELU) as a new activation function.

    Experiments on Cifar-100 show that the classification performance is further improved when using the ShELU activation function in comparison with ELU. The improvement is achieved when learning an individual bias shift for each neuron.

  • 326.
    Guillen, Carlos Alonso
    Linköpings universitet, Institutionen för systemteknik.
    Implementation of the IEEE 802.11a MAC layer in C language2004Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    Wireless communication is being developed in the last years day by day, there are several standards that talks about it. We are going to go through the IEEE standard 802.11 which talks about wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. Looking this more carefully we will study MAC specifications and its environment.

    The work that ISY department at Institute of Technology of Linkoping University has proposed is to design a MAC sublayer implementation for WLANs using C language programming and testing it with the test environment called “test bench”. This test bench will simulate LLC sublayer and PHY layer, in this way, our MAC implementation will has to interact with it. Therefore we will simulate a wireless network where we are going to have a short number of stations and we are going to look at carefully the MAC sublayer response in an ad hoc network.

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  • 327.
    Gunasekaren, Shankar
    Linköpings universitet, Institutionen för systemteknik.
    A synthesizable verilog model of serial protocol engine for USB 1.1 device2007Självständigt arbete på avancerad nivå (magisterexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC.The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a top down approach and the model was verified and validated.

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  • 328.
    Gundlegård, David
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Kommunikations- och transportsystem. Linköpings universitet, Tekniska fakulteten.
    Allström, Andreas
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Kommunikations- och transportsystem. Linköpings universitet, Tekniska fakulteten.
    Bergfeldt, Erik
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Kommunikations- och transportsystem. Linköpings universitet, Tekniska fakulteten.
    Ringdahl, Rasmus
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Kommunikations- och transportsystem. Linköpings universitet, Tekniska fakulteten.
    Bayen, Alexandre M.
    University of California, Berkeley, USA.
    Travel Time and Point Speed Fusion Based on a Macroscopic Traffic Model and Non-linear Filtering2015Ingår i: 2015 IEEE 18th International Conference on Intelligent Transportation Systems, IEEE conference proceedings, 2015, s. 2121-2128Konferensbidrag (Refereegranskat)
    Abstract [en]

    The number and heterogeneity of traffic sensors are steadily increasing. A large part of the emerging sensors are measuring point speeds or travel times and in order to make efficient use of this data, it is important to develop methods and frameworks for fusion of point speed and travel time measurements in real-time. The proposed method combines a macroscopic traffic model and a non-linear filter with a new measurement model for fusion of travel time observations in a system that uses the velocity of cells in the network as state vector. The method aims to improve the fusion efficiency, especially when travel time observations are relatively long compared to the spatial resolution of the estimation framework. The method is implemented using the Cell Transmission Model for velocity (CTM-v) and the Ensemble Kalman Filter (EnKF) and evaluated with promising results in a test site in Stockholm, Sweden, using point speed observations from radar and travel time observations from taxis.

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  • 329.
    Gunnars Risberg, Pär
    Linköpings universitet, Institutionen för systemteknik.
    Förbättring av högtalares prestanda genom digital signalbehandling2007Självständigt arbete på grundnivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [sv]

    Högtalare består idag ofta av flera högtalarelement, avsedda för olika frekvensområden. Signalen som driver dessa måste delas upp genom att oönskade frekvenskomponenter filtreras bort ur respektive utgående signal. Normalt görs detta med passiva komponenter i högtalarlådan. I denna rapport beskrivs arbetet med att ta fram ett digitalt system för att ersätta dessa passiva filter. Teoridelen tar metodiskt läsaren till en relevant kravspecifikation för systemet. Systemets fördelar gentemot den konventionella systemutformningen

    diskuteras också. Ingående delystem är hårdvara för digital signalinmatning, digital signalprocessor för bearbetning av ljudet samt analog hårdvara för utmatning av de frekvensuppdelade ljudsignalerna. Stor vikt ligger på mjukvaruapplikationens struktur och implementation. Verifiering av systemets prestanda görs med en för akustikmätningar väl etablerad metod. I resultatdelen presenteras också det digitala systemets förmåga att kompensera högtalarens frekvensgång mot en given målkurva. Slutligen ges konkreta förslag på förbättringar av systemet som kan göras.

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  • 330.
    Guo, Xuewen
    et al.
    East China Normal Univ, Peoples R China.
    Li, Danqin
    East China Normal Univ, Peoples R China.
    Zhang, Yuexing
    Soochow Univ, Peoples R China.
    Jan, Ming
    Shanghai Jiao Tong Univ, Peoples R China.
    Xu, Jinqiu
    Shanghai Jiao Tong Univ, Peoples R China.
    Wang, Zhiquan
    East China Normal Univ, Peoples R China.
    Li, Bo
    East China Normal Univ, Peoples R China.
    Xiong, Shaobing
    East China Normal Univ, Peoples R China.
    Li, Yanqing
    Soochow Univ, Peoples R China.
    Liu, Feng
    Shanghai Jiao Tong Univ, Peoples R China.
    Tang, Jianxin
    Soochow Univ, Peoples R China.
    Duan, Chungang
    East China Normal Univ, Peoples R China; Shanxi Univ, Peoples R China.
    Fahlman, Mats
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Ytors Fysik och Kemi. Linköpings universitet, Tekniska fakulteten.
    Bao, Qinye
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Ytors Fysik och Kemi. Linköpings universitet, Tekniska fakulteten. East China Normal Univ, Peoples R China; Shanxi Univ, Peoples R China; Soochow Univ, Peoples R China.
    Understanding the effect of N2200 on performance of J71: ITIC bulk heterojunction in ternary non-fullerene solar cells2019Ingår i: Organic electronics, ISSN 1566-1199, E-ISSN 1878-5530, Vol. 71, s. 65-71Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    None-fullerene solar cells with ternary architecture have attracted much attention because it is an effective approach for boosting the device power conversion efficiency. Here, the crystalline polymer N2200 as the third component is integrated into J71: ITIC bulk heterojunction. A series of characterizations indicate that N2200 could increase photo-harvesting, balanced hole and electron mobilities, enhanced exciton dissociation, and suppressed charge recombination, which result in the comprehensive improvement of open circuit voltage, short circuit current and fill factor in the device. Moreover, after introduction of N2200, the morphology of the ternary active layer is optimized, and the film crystallinity is improved. This work demonstrates that adding a small quantity of high crystallization acceptor into non-fullerene donor: acceptor mixture is a promising strategy toward developing high-performance organic solar cells.

    Publikationen är tillgänglig i fulltext från 2021-05-08 08:41
  • 331.
    Gustafsson, Andreas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Hir, Danijel
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    High precision frequency synchronization via IP networks2010Självständigt arbete på avancerad nivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    This  report  is  a  part  of  a  master  thesis  project  done  at  Ericsson  Linköping  incooperation with Linköpings Tekniska Högskola (LiTH). This project is divided intwo different parts.  The first part is to create a measurement node that collectsand processes data from network time protocol servers.   It is used to determinethe  quality  of  the  IP  network  at  the  node  and  detect  potential  defects  on  usedtimeservers or nodes on the networks.The second assignment is to analyze the collected data and further improve theexisting synchronization algorithm.  Ip communication is not designed to be timecritical and therefore the NTP protocol needs to be complemented with additionalsignal processing to achieve required accuracy.  Real time requirements limit thecomputational complexity of the signal processing algorithm.

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  • 332.
    Gustafsson, Helena
    Linköpings universitet, Institutionen för systemteknik.
    Implementering av ett parameteriserbart aktivt vågfilter2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [sv]

    Detta examensarbete gick ut på att försöka hitta ett sätt att mäta kompo nentkänslighet hos parameteriserbara aktiva vågfilter. Två olika ansatser har gjorts, men bara ett försök har avslutats.

    Det första försöket behandlar möjligheten att realisera ett vågfilter med hjälp av standardkomponenter i en kretskortslösning. Detta fungerade inte beroende på att nödvändiga komponenter inte finns på marknaden idag. Komponenterna som finns har för stora parasitkapacitanser. Dessa oönskade parasiter var så stora att de skulle kunna förstöra funktionen och det var således inte värt att fortsätta försöket. De komponenter som undersöktes var resistansstegar och digitala potentiometrar. Den största delen av studierna till det första försöket har bestått i att studera datablad från olika kretstillverkare för att hitta lämpliga komponenter.

    Istället startades ett nytt försök som syftade till att undersöka möjligheten att implementera ett aktivt vågfilter i en integrerad krets. I denna rapport presenteras en förstudie till hur en sådan lösning skulle kunna se ut. För att möjliggöra en fortsättning där mitt examensarbete tar slut har arbetet förklarats ingående. Jag har också inkluderat min programkod som bilagor i slutet av rapporten.

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  • 333.
    Gustafsson, Henrik
    Linköpings universitet, Institutionen för systemteknik.
    Behavioral model of an address generation unit2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP.

    The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories.

    This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.

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  • 334.
    Gustafsson, Kristian
    Linköpings universitet, Institutionen för systemteknik.
    Implementation of a Digital Radio Frequency Memory in a Xilinx Virtex-4 FPGA2005Självständigt arbete på grundnivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.

    Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.

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  • 335.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Graph-based code word selection for memoryless low power bus coding2004Ingår i: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 40, nr 24, s. 1531-1532Artikel i tidskrift (Refereegranskat)
  • 336.
    Gustafsson, Oscar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wanhammar, Lars
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Arithmetic2010Ingår i: Handbook of signal processing systems / [ed] Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, Springer , 2010, 1, s. 283-327Kapitel i bok, del av antologi (Refereegranskat)
    Abstract [en]

    Handbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels.

  • 337.
    Gustavsson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Tan, Nianxiong
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    CMOS Data Converters for Communications2000Bok (Övrigt vetenskapligt)
    Abstract [en]

    CMOS Data Converters for Communications distinguishes  itself from other data converter books by emphasizing system-related  aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given  communication system (baseband, passband, and multi-carrier systems).  The authors also review CMOS data converter architectures and discuss  their suitability for communications.

    The rest of the book is  dedicated to high-performance CMOS data converter architecture and  circuit design. Pipelined ADCs, parallel ADCs with an improved passive  sampling technique, and oversampling ADCs are the focus for ADC  architectures, while current-steering DAC modeling and implementation  are the focus for DAC architectures. The principles of the  switched-current and the switched-capacitor techniques are reviewed  and their applications to crucial functional blocks such as  multiplying DACs and integrators are detailed.

    The book outlines the  design of the basic building blocks such as operational amplifiers,  comparators, and reference generators with emphasis on the practical  aspects. To operate analog circuits at a reduced supply voltage,  special circuit techniques are needed. Low-voltage techniques are also  discussed in this book.

    CMOS Data Converters for Communications can be used as a  reference book by analog circuit designers to understand the data  converter requirements for communication applications. It can also be  used by telecommunication system designers to understand the  difficulties of certain performance requirements on data converters.  It is also an excellent resource to prepare analog students for the  new challenges ahead.

  • 338.
    Gustavsson, Per
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap.
    Håkansson, Pär
    Linköpings universitet, Institutionen för teknik och naturvetenskap.
    Utvärdering av en FPGA för rymdbruk2005Självständigt arbete på grundnivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    A new FPGA suitable for space applications has just reached the market. To investigate whether there are any possible flaws or limitations similar to those previously seen on FPGAs, an evaluation has to be done. This master thesis contains the evaluation of this new radhard FPGA with focus on possible design limitations and package related electrical phenomena.Areas evaluated: Ground-/VDD bounce, Cross talk, Rise time sensitivit, Power cycling, Power consumption, Place and route tool, Radiation hardnessThis report contains all steps in the evaluation. From method to measurements, comparisons, theory, results and conclusions. In the evaluation work, special effort has been made to develop designs that really stress the FPGA to find potential problems. All problems found are dealt with in this report.Results: Ground-/VDD bounce measurements showed that devices using a fast slew rate resulted in TTL-level violation. However, by separating sensitive signals and SSOs in different I/O banks it is possible to work around the problem. Cross talk measurements has shown that the phenomena causes problems when using a long rise time input with toggling outputs placed next to the signal. Power cycling did not result in any alarming inrush currents. Regular power up showed an unwanted behaviour with pulses on all I/Os right before power on reset kicked in. When comparing the tool value with measurements regarding power consumption it was clear that it differed as much as 40-50%. The FPGA consumes 40-50% more power than what the power calculator tool estimates.

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  • 339.
    Guzeev, Andrew
    Linköpings universitet, Institutionen för systemteknik.
    Use of equalization and echo canceling on circuit board wires2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    Advances in CMOS technology have resulted in increased clock fre-quencies, even exceeding 3GHz. At the same time, frequencies on most board wires are 125-800MHz. It is especially problematic in modern computer mem-ory buses and high speed telecommunication devices, such as switches and routers operating at 10Gb/s on its ports. It is believed that circuit board buses can be used up to about 20GHz, but there is a problem with Intersymbol Inter-ference (ISI) causing distortion of transmitted symbols by multiple reflections.

    Actually, the circuit board bus behaves like a passive low pass filter with unknown (perhaps changing) transfer characteristic. The problem of ISI was solved some time ago in the telecommunication area. With use of adaptive equalizers it is possible to increase throughput of a long distance communication channel dramatically.

    But the microprocessor bus has certain differences from telecommunica-tion devices such as modems. First of all, the clock frequency on a bus is much higher than in modems. Secondly, a bus has a much more complex structure than a telecommunication channel. At the same time, we can’t use a lot of re-sources for bus maintaining.

    The aim of the thesis work is to investigate the possibility of using adap-tive equalization on a bus, and the construction of a reasonable mathematical model of such an equalizer. Also limits of equalizationare examined and de-pendencies are derived.

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  • 340.
    Hadzimusic, Rasid
    Linköpings universitet, Institutionen för systemteknik.
    Design of Low Voltage Low Power and Highly Efficient DC-DC Converters, Theoretical Guidelines2004Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    In this thesis a predefined design parameters are used to present theoretical guidelines for design of low voltage, and low power DC-DC converter with high power efficiency and low levels of EMI (Electro-Magnetic Interference). This converter is used to alter the DC voltage supplied by the power source. Several DC-DC converters of different types and topologies are described and analyzed. Switched converter of buck topology is found to satisfy the design criteria most adequately and therefore is chosen as the solution for the task of the thesis. Three control schemes are analysed PWM (Pulse-Width Modulation), PFM (Phase-Frequency Modulation), and Sliding control. PWM is found to be most appropriate for implementation with this type of converter. Further, basic operation of the buck converter which includes two modes of operation CCM (Continuous-Conduction Mode) and DCM (Discontinuous-Conduction Mode) is described. Power losses associated with it are analysed as well. Finally several techniques for power conversion improvement are presented.

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  • 341.
    Hadziselimovic, Adin
    Linköpings universitet, Institutionen för systemteknik.
    Ring Simulator2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This report is about a Thesis for Degree of Bachelor of Science at Linköping University. It describes design of equipment which makes it possible to measure signal and noise quality during data transmission via Asymmetric Digital Subscriber Line, ADSL. The measuring instrument is HP 4934A Transmission Impairment Measuring Set. The equipment was supposed to be used for testing of ADSL systems within Solectron Sweden AB. In fact, the equipment stands for virtual Plain Old Telephone Service, POTS. That is why it simulates all three states that may come up. The states are following:"on hook", ringing,"off hook"(speech transmission). There is a control unit in the design. It changes between different circuit connections to get one of the states. You have to use a computer for control of the equipment. The computer commands are sent to equipment via its serial port via RS232 to the control unit. The equipment is driven with 48 Vdc.

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  • 342.
    Hagfalk, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik.
    Eriksson Ianke, Erik
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik.
    Vision Sensor Scheduling for Multiple Target Tracking2010Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    This thesis considers the problem of tracking multiple static or moving targets with one single pan/tilt-camera with a limited field of view. The objective is to minimize both the time needed to pan and tilt the camera's view between the targets and the total position uncertainty of all targets. To solve this problem, several planning methods have been developed and evaluated by Monte Carlo simulations and real world experiments. If the targets are moving and their true positions are unknown, both their current and future positions need to be estimated in order to calculate the best sensor trajectory. When dealing with static and known targets the problem is reduced to a deterministic optimization problem.

    The planners have been tested through experiments using a real camera mounted above a car track using toy cars as targets. An algorithm has been developed to detect the cars and associate the detections with the correct target.

    The Monte Carlo simulations show that, in the case of static targets, there is a huge advantage to arrange the targets into groups to be able to view more than one target at the time. In the case of moving targets with estimated positions it can be concluded that if the objective is to minimize the error in the position estimation the best planning choice is to always move to the target with the highest position uncertainty.

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  • 343.
    Haider, Daniyal
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    On-Chip Phase Measurement Design Study in 65nm CMOS Technology2015Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

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  • 344.
    Hall, Filip
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap.
    Håkansson, Pär
    Linköpings universitet, Institutionen för teknik och naturvetenskap.
    Implementing a receiver in a fast data transfer system: A feasibility study2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB.

    The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to the load, which is sensitive to heat.

    Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed.

    The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.

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  • 345.
    Hall, Marcus
    et al.
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem.
    Forsberg, David
    Linköpings universitet, Institutionen för systemteknik, Fordonssystem.
    Reduced Fuel Consumption of Heavy-Duty Vehicles using Pulse and Glide2019Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    The transport sector always strive towards reduced fuel consumption for heavydutyvehicles. One promising control strategy is to use Pulse and Glide. Themethod works by acceleration to a high speed and then glide in neutral gear to alow speed.Two different control strategies and four different glide options were investigated.The two strategies were either to follow the optimal BSFC-line or using optimalcontrol. For each strategy, different velocity spans between the upper and lowervelocity were tested.The results show that the fuel consumption can be reduced up to 8.1 % comparedto a constant speed driving strategy. The fuel consumption was reduced the mostfor lower velocities and if the difference between the upper and lower velocity forthe Pulse and Glide strategy was kept small. The fuel saving can be explaineddue to increased engine efficiency during the pulse. The results also show thatthe difference between the rule-based and optimization based control strategy issmall. It can be concluded that a near-optimal strategy for a heavy-duty vehicleutilizing Pulse and Glide is to always pulse on the optimal BSFC-line.

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  • 346.
    Halling, Jon
    Linköpings universitet, Institutionen för systemteknik.
    1553-Simulator. In-/uppspelning av databusstrafik med hjälp av FPGA2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    At Saab Aerospace in Linköping, components for measurement systems to the fighter aircraft JAS 39 Gripen are developed. In this activity you sometimes want to record the traffic transmitted on the data busses that connects different sys-tems. This traffic on the data busses is using the military standard MIL-STD-1553.

    This project has aimed to create a system for recording and sending 1553-data. The system is used on an ordinary personal computer, equipped with a recon- figurable I/O card that among others has a programmable logic circuit (FPGA). The recorded data are stored on a hard drive. The system has a graphical user interface, where the user can configure different methods of filtering the data, and other preferences.

    The completed system has currently the capacity to record one channel. This works excellent and the system basically meets all the requirements stated at the start of the project. By using this system instead of the commercial available systems on the market one will get a competitive alternative. If the system where to be developed further, with more channels, it would get even more price worth. Both in case of price per channel, but also in functionality. This is because it is possible to design exactly the functions the user demands. But the current version is already fully functional and competitive compared to commercial systems.

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  • 347.
    Hallström, Claes
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model: Optimization of an Eight-Bit C-xC SAR ADC2013Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor network to performthe conversion. Focus in the master’s thesis was set to understand how the charge is redistributedin the network during the conversion and calibration phase. Redundancy andparasitic capacitors is present in the system and rises the need for extra conversion steps aswell as a calibration algorithm. The calibration algorithm, Bit Weight Estimation, calculatesa weight corresponding to each bit which is used in the last conversion step to perform adigital weighting. The result of extensive calculations in different C-xC capacitor networkswas a model in Python of an N-bit C-xC sar adc. That model was used to create a model ofan eight-bit C-xC sar adc and finding suitable parameters for it through calculations andsimulations. The parameters giving the best inl was chosen. With the best parameters theC-xC sar adc static and dynamic performance was tested and showed an inl of less than1lsb, snr of 47:8 dB and enob of 7:6 bits.

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  • 348.
    Halonen, Niina
    et al.
    Microelectronics and Material Physics Laboratories, University of Oulu, Finland.
    Kilpijärvi, Joni
    Microelectronics and Material Physics Laboratories, University of Oulu, Finland.
    Sobocinski, Maciej
    Microelectronics and Material Physics Laboratories, University of Oulu, Finland.
    Datta-Chaudhuri, Timir
    Laboratory for MicroTechnologies, Department of Mechanical Engineering and the Institute for Systems Research ,University of Maryland, Baltimore, USA.
    Hassinen, Antti
    Division of Cell Biology, Department of Biochemistry, University of Oulu, Finland.
    Prakash, S. B.
    Integrated Biomorphic Information System Laboratory, University of Maryland, Baltimore, USA.
    Möller, Peter
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Tillämpad sensorvetenskap. Linköpings universitet, Tekniska fakulteten.
    Abshire, Pamela
    Integrated Biomorphic Information System Laboratory, University of Maryland, Baltimore, USA.
    Smela, Elisabeth
    Laboratory for MicroTechnologies, Department of Mechanical Engineering and the Institute for Systems Research, University of Maryland, Baltimore, USA.
    Kellokumpu, Sakari
    Division of Cell Biology, Department of Biochemistry, University of Oulu, Finland.
    Lloyd Spetz, Anita
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Tillämpad sensorvetenskap. Linköpings universitet, Tekniska fakulteten. Univ Oulu, Oulu, Finland.
    Low temperature co-fired ceramic package for lab-on-CMOS applied in cell viability monitoring2015Ingår i: Procedia Engineering, ISSN 1877-7058, E-ISSN 1877-7058, Vol. 120, s. 1079-1082Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Lab-on-CMOS chips (LOCMOS) are sophisticated miniaturized analysis tools based on integrated circuit (IC) microchips performing various laboratory functions. We have developed a low temperature co-fired ceramic (LTCC) package for a LOCMOS application regarding cytotoxicity assessment of nanomaterials. The LTCC packaged capacitance sensor chip is designed for long-term cell viability monitoring during nanoparticle exposure. The introduced LTCC package utilizes the flip chip bonding technique, and it is biocompatible as well as able to withstand the environmental conditions required to maintain mammalian cell culture directly on the surface of a complementary metal oxide semiconductor (CMOS) integrated circuit.

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  • 349.
    Hansson, Erik
    Linköpings universitet, Institutionen för systemteknik.
    Detektering samt minskning av Underhållsskuld2008Självständigt arbete på grundnivå (yrkesexamen), 10 poäng / 15 hpStudentuppsats
    Abstract [en]

    Detta exjobb är skapat utifrån ett uppdrag av ABB´s underhållssida på CloettaFazers fabrik i Ljungsbro utanför Linköping. Uppdraget består av att skapa en mall som ska användas för att detektera och minska underhållsskulden på en typisk industrilina. Den skapade underhållsskuldsmallen ska sedan realiseras på en verklig industrilina i CloettaFazers fabrik i Ljungsbro.Exjobbet är uppdelat i fyra delar, där den första delen behandlar bakgrunden, syftet och metoden. Den andra delen behandlar hur själva skapandet av mallen går till, samt hur den ska användas för att detektera och minska underhållsskuld i en typisk industrilina. Den tredje delen behandlar hur mallen fungerar i praktiken, i detta fall realiseras mallen på industrilinan Bridgepack. Den fjärde och avslutande delen behandlar exjobbets resultat och avslutande diskussion.Tanken bakom skapandet av mallen var att skapa en lättförstålig mall som hjälper till att hitta grundorsaken till problemet. Alltså inte bara lösning som löser det direkta felet, utan även att man hittar grundorsaken som hindrar att felet uppstår igen. Idéer och inspiration till detta tillvägagångssätt har mestadels hämtats från filosofin ”The Toyota Way” som Toyota använder sig av i sin verkstadsindustri.Realiseringen av mallen på den aktuella industrilinan Bridgepack har gett blandade resultat. Dels för att i början av exjobbet antogs att många av orsakerna varför inte Bridgepacken fungerade som önskats, berodde på att dom elektriska systemen som styr Bridgepacken började bli slitna och inte lika tillförlitliga som dom en gång varit. Dock så har det visat sig under exjobbets gång att industrilinans brister snarare har berott på mer mekaniska fel än dom elektroniska systemen. Resultaten som exjobbet främst har visat, är att många enklare mekaniska lösningar kommer att påverka effektiviseringen av produktionskörningen avsevärt.

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  • 350.
    Hansson, Martin
    Linköpings universitet, Institutionen för systemteknik.
    Design of microwave low-noise amplifiers in a SiGe BiCMOS process2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    In this thesis, three different types of low-noise amplifiers (LNA’s) have been designed using a 0.25 mm SiGe BiCMOS process. Firstly, a single-stage amplifier has been designed with 11 dB gain and 3.7 dB noise figure at 8 GHz. Secondly, a cascode two-stage LNA with 16 dB gain and 3.8 dB noise figure at 8 GHz is also described. Finally, a cascade two-stage LNA with a wide-band RF performance (a gain larger than unity between 2-17 GHz and a noise figure below 5 dB between 1.7 GHz and 12 GHz) is presented.

    These SiGe BiCMOS LNA’s could for example be used in the microwave receivers modules of advanced phased array antennas, potentially making those more cost- effective and also more compact in size in the future.

    All LNA designs presented in this report have been implemented with circuit layouts and validated through simulations using Cadence RF Spectre.

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