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  • 351.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Lim, Boonshyang
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Parallelization of High-Performance Video Encoding on a Single-Chip Multiprocessor2007In: IEEE International Conference on Signal Processing and Communications,2007, IEEE , 2007Conference paper (Refereed)
    Abstract [en]

    Although single-chip multiprocessor architectures are available nowadays for embedded computing, programming them with efficiency and productivity has become a significant challenge. This paper studies the multi-level parallelization of video encoding algorithms on a state-of-the-art on-chip multiprocessor. The encoding of H.264/AVC video is chosen as the case to be studied because of its performance demanding and branch-rich features. The final benchmarking result proves that the optimized processing flow can achieve more than 100 operations per cycle in performance which allows a single-chip multiprocessor to encode high resolution video (1920 x 1080) in real-time (30 fps).

  • 352.
    Wu, Zhenzhi
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
    Gong, Chen
    Beijing Institute Technology, Peoples R China.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
    Computational Complexity Analysis of FEC Decoding on SDR Platforms2017In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 89, no 2, p. 209-224Article in journal (Refereed)
    Abstract [en]

    The computational complexity evaluation is necessary for software defined Forward Error Correction (FEC) decoders. However, currently there are a limited number of literatures concerning on the FEC complexity evaluation using analytical methods. In this paper, three high efficient coding schemes including Turbo, QC-LDPC and Convolutional code (CC) are investigated. The hardware-friendly decoding pseudo-codes are provided with explicit parallel execution and memory access procedure. For each step of the pseudo-codes, the parallelism and the operations in each processing element are given. Based on it the total amount of operations is derived. The comparison of the decoding complexity among these FEC algorithms is presented, and the percentage of each computation step is illustrated. The requirements for attaining the evaluated results and reference hardware platforms are provided. The benchmarks of state-of-the-art SDR platforms are compared with the proposed evaluations. The analytical FEC complexity results are beneficial for the design and optimization of high throughput software defined FEC decoding platforms.

  • 353.
    Wu, Zhenzhi
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Flexible Multistandard FEC Processor Design With ASIP Methodology2014In: PROCEEDINGS OF THE 2014 IEEE 25TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2014), IEEE , 2014, p. 210-218Conference paper (Refereed)
    Abstract [en]

    Designing decoder for forward error correction (FEC) is more and more challenging because of the requirements on simultaneous supporting of various wireless standards within one IC module. The flexibility, silicon cost and throughput efficiency are all necessary to be traded off. In this paper, by using ASIP methodology, software-hardware co-design is introduced to offer sufficient flexibility of FEC decoding. The decoding procedure can be programmable for decoding QC-LDPC, Turbo and Convolutional Codes. Firstly, the common features from all mentioned algorithms and their corresponding datapaths are analyzed and a unified multi-standard datapath is introduced. Based on it, an application specific instruction-set is proposed and an ASIP (Application Specific Instruction-set Processor) for the FEC algorithms is designed. The firmware FEC codes are developed to adapt to standards. Synthesis results show that the proposed FEC processor is 1.54mm(2) under 65nm CMOS process. It offers QC-LDPC decoding for WiMAX, Turbo decoding for 3GPP-LTE, and 64 states Convolutional code (CC) decoding at the throughput of 193 Mbps, 62 Mbps and 60 Mbps respectively under clock frequency of 200 MHz. The proposed ASIP provides programmable high throughput compared to other tri-mode hardware modules.

  • 354.
    Wu, Zhenzhi
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
    High-Throughput Trellis Processor for Multistandard FEC Decoding2015In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, p. 2757-2767Article in journal (Refereed)
    Abstract [en]

    Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm(2) (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.

  • 355.
    Wu, Zhenzhi
    et al.
    Beijing Institute Technology, Peoples R China.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Memory Sharing Techniques for Multi-standard High-throughput FEC Decoder2014In: 2014 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION (SAMOS XIV), IEEE , 2014, p. 93-98Conference paper (Refereed)
    Abstract [en]

    Nowadays multi-standard wireless baseband, Convolutional Code (CC), Turbo code and LDPC code are widely applied and need to be integrated within one FEC module. Since memory occupies half or even more area of the decoder, memory sharing techniques for area saving purpose is valuable to consider. In this work, several memory merging techniques are proposed. A non-conflict access technique for merged path metric buffer is proposed. The results show that 41% of total memory bits are saved when integrating three different decoding schemes including CC (802.11a/g/n), LDPC (802.11n and 802.16e) and Turbo (3GPP-LTE). Synthesis result with 65nm process shows that the merged memory blocks consume merely 1.06mm(2) of the chip area.

  • 356.
    Xiaoyi, Peng
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    Benchmark of MPEG-2 Video Decoding on ePUMA Multi-core DSP Processor2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Video decoding technologies have been widely used in our daily life. Higherresolutions and more advanced coding technologies may promote the capabilitiesof video decoding. A new multi-core digital signal processing processor, ePUMA,which stands for embedded Parallel DSP platform with Unique Memory Access,is chosen to investigate how it supports video decoding.

    This thesis aims to benchmark the algorithms of video decoding and evaluatethe performance using ePUMA in MPEG-2 standard, which is a common standardwith the purpose of compressing video signals. Based on the slice-parallelismmethodology on eight co-processors of ePUMA, the implementation of the algorithemsconsists of variable length decoding, inverse scan, inverse quantization,two-dimensional inverse discrete cosine transform, motion vector decoding, formprediction and motion compensation. The performance of the kernels is benchmarkedby ePUMA system simulator. The result shows that to decode real-timeFull HD (1920*1080 pixels, 30 frames per second) video, it will require ePUMA torun at 280 MHz for I frames and at 320MHz for P frames.

  • 357.
    Yaochuan, Chen
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Binary Instruction Format Specification for NoGap2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays, hardware designers want to get a powerful and friendly tool to speedup the design flow and design quality. The new development suit NoGap is pro-posed to meet those requirements. NoGap is a design automation tool for ASIP,it helps users to focus on the design stage, free them from module connection andsignal assignment, or integration. Different from the normal ADL tools which limitusers’ design ideas to some template frameworks, NoGap allow designers to im-plement what they want with NoGap Common Language (NoGapCL). However,NoGap is still not perfect, some important functionalities are lacking, but withthe flexible generator component structure, NoGap and NoGapCL can easily beextended.This thesis will firstly investigate the structure of Novel Generator of Acceler-ators and Processors (NoGap) from software prospective view, and then present anew NoGap generator, OpCode Assignment Generator (OpAssignGen), which al-lows users to assign operation code values, exclude operation codes and customizethe operation code size or instruction size.A simple example based on the Microprocessor without Interlocked PipelineStages (MIPS) instructions sets will be mentioned to give users a brief view ofhow to use OpAssignGen. After that, the implementation of the new generatorwill be explained in detail.What’s more, some of NoGap’s flaws will be exposed, but more suggestionsand improvements for NoGap will be given.At last, a successful synthesis result based on the simple MIPS hardware im-plementation will be shown to prove the new generator is well implemented. Moreresults and the final conclusion will be given at the end of the thesis.

  • 358.
    Yu, Lang
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    Evaluating and Implementing JPEG XR Optimized for Video Surveillance2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This report describes both evaluation and implementation of the new coming image compression standard JPEG XR. The intention is to determine if JPEG XR is an appropriate standard for IP based video surveillance purposes. Video surveillance, especially IP based video surveillance, currently has an increasing role in the security market. To be a good standard for surveillance, the video stream generated by the camera is required to be low bit-rate, low latency on the network and at the same time keep a high dynamic display range. The thesis start with a deep insightful study of JPEG XR encoding standard. Since the standard could have different settings,optimized settings are applied to JPEG XR encoder to fit the requirement of network video surveillance. Then, a comparative evaluation of the JPEG XR versusthe JPEG is delivered both in terms of objective and subjective way. Later, part of the JPEG XR encoder is implemented in hardware as an accelerator for further evaluation. SystemVerilog is the coding language. TSMC 40nm process library and Synopsys ASIC tool chain are used for synthesize. The throughput, area, power ofthe encoder are given and analyzed. Finally, the system integration of the JPEGXR hardware encoder to Axis ARTPEC-X SoC platform is discussed.

  • 359.
    Zhou, Ruoxing
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Dynamic Partial Reconfigurable FPGA2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes.

    A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time.

    Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.

  • 360.
    Zhou, Wenbiao
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Karlström, Per
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    NoGapCL: A flexible common language for processor hardware description2010Conference paper (Refereed)
    Abstract [en]

    Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGap (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs, utilizing hardware multiplexed data paths. One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap impose few limits on the architecture and thus design freedom. NoGap does not assume a fixed processor template and is not a data flow synthesizer. To reach this flexibility NoGap makes heavy use of the compositional design principle. This paper describe NoGapCL, a flexible common language for processor hardware description. A RISC processor using NoGapCL has been constructed with NoGap in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178MHz in a Virtex-4 LX80 speedgrade 12.

  • 361.
    Åslund, Jan
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Bregon, A.
    Department of Computer Science, University of Valladolid, Spain.
    Krysander, Mattias
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Frisk, Erik
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Pulido, B.
    Department of Computer Science, University of Valladolid, Spain.
    Biswas, G.
    Dept. of EECS, ISIS, Vanderbilt University, Nashville, United States.
    Structural diagnosability analysis of dynamic models2011In: Proceedings of the 18th IFAC World Congress, 2011: Structural Diagnosability Analysis of Dynamic Models / [ed] Bittanti, Sergio, Cenedese, Angelo, Zampieri, Sandro, Milano, Italy: Elsevier , 2011, Vol. 18, no PART 1, p. 4082-4088Conference paper (Refereed)
    Abstract [en]

    This work is focused on structural approaches to studying diagnosability properties given a system model taking into account, both simultaneously or separately, integral and differential causal interpretations for differential constraints. We develop a model characterization and corresponding algorithms, for studying system diagnosability using a structural decomposition that avoids generating the full set of system ARRs. Simultaneous application of integral and differential causal interpretations for differential constraints results in a mixed causality interpretation for the system. The added power of mixed causality is demonstrated using a case study. Finally, we summarize our work and provide a discussion of the advantages of mixed causality over just derivative or just integral causality. © 2011 IFAC.

  • 362.
    Öhlin, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Real-Time Multi-Dimensional Fast Fourier Transforms on FPGAs2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis presents a way of performing multi dimensional FFT in a continuousflow environment by calculating the FFT of each dimension separately ina pipeline. The result is a three dimensional pipelined FFT implemented on aStratix III FPGA. It can calculate the three dimensional FFT of a data set containing2563 samples with a word size of 32 bits. The biggest challenge and themain part of the work are the data permutations in between the one dimensionalFFT modules, this part of the design make use of an external DDR2 SDRAMas well as on-chip BRAM to store and permute data between the modules. Theevaluations show that the design is hardware efficient and the latency is relativelylow and determined to be 84.2 ms.

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