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  • 501.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2012In: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, p. 369-372Conference paper (Refereed)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 502.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, p. 666-670Article in journal (Refereed)
    Abstract [en]

    This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

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  • 503.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices2011In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland: IEEE Solid-State Circuits Society, 2011, p. 467-470Conference paper (Refereed)
    Abstract [en]

    This paper describes an ultra-low-power SAR ADC in 0.13-um CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-um CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

  • 504.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1585-1593Article in journal (Refereed)
    Abstract [en]

    This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

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  • 505.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications2010In: NORCHIP 2014, Tampere: IEEE , 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.

  • 506.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Power Analysis of Charge-Redistribution SAR ADCs2011In: Swedish System-on-Chip Conference (SSOCC), Varberg, Sweden: IEEE Solid-State Circuits Society, 2011Conference paper (Other academic)
  • 507.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Power Consumption Bounds for SAR ADCs2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 556-559Conference paper (Refereed)
    Abstract [en]

    Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.

  • 508.
    Zhang, Yumiao
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ultra-Low Power Input Driver for High-ResolutionDiscrete-Time Σ∆ Modulator2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis presents the design of an input driver for ultra-low power sigmadelta modulator. High resolution Σ∆ ADCs are becoming more and more usefulin ultra-low power medical applications. Therefore, reducing supply voltage andpower starts a new chanllenges both at architecture as well as circuit performancelevel. Three input drivers are presented in this thesis making use of operationalamplifiers with the class AB buffers as output stage.In the thesis, the building blocks of the input buffer are described in detail.Two different designs are included in the thesis in order to achieve the specificationunder different conditions of the input signal. The specifications are 90 dB Signalto-Noiseand Distortion Ratio (SNDR) and 4 µW of the power consumption. Atwo stage achitectures with different building blocks is investigated. The buildingblocks are a single stage fully differential amplifier as the first stage and a classAB behavior unity gain buffer as the second stage. Design comparison is basedon the simulation results. The reasons for the different designs are mainly causedby design constraints, the input signal voltage level and the stability. Designconstraints are because of the trade-offs among structure of the building block,transistor threshold voltage and low power supply voltage. At the end of thisthesis project, we achieved 90dB SNDR in the first design by using Folded-VoltageFollower (FVF) structure in transistor level and an improved performance designin the second design.

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    Master_Thesis_ZhangYumiao
  • 509.
    Zulkifl, Saad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Frame rate limiter for export restricted cameras2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis describes the design of a low power and low noise CMOS circuit capable of limiting 9 frames per second. This is a part of a larger ongoing project for development and design of a low-cost IR night-vision network camera. This circuit is implemented in 0.35μm process. An RC-oscillator with voltage averaging feedback concept is used as timing reference which is capable of overcoming ± 20% of frequency variations.

    The circuit consumes 85 μW power when enabled and 1.853 μW power when disabled. This circuit design allows 9 frames per second. The variation in frequency due to a temperature range of -40°C to 100°C is within ±2.5% and for voltage range of 3.2V to 3.6V is within ±1%.

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    fulltext
891011 501 - 509 of 509
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