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  • 51.
    Ahlberg, Jesper
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Blomquist, Esbjörn
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Online Identification of Running Resistance and Available Adhesion of Trains2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Two important physical aspects that determine the performance of a running train are the total running resistance that acts on the whole train moving forward, and the available adhesion (utilizable wheel-rail-friction) for propulsion and breaking. Using the measured and available signals, online identification of the current running resistance and available adhesion and also prediction of future values for a distance ahead of the train, is desired. With the aim to enhance the precision of those calculations, this thesis investigates the potential of online identification and prediction utilizing the Extended Kalman Filter.

    The conclusions are that problems with observability and sensitivity arise, which result in a need for sophisticated methods to numerically derive the acceleration from the velocity signal. The smoothing spline approximation is shown to provide the best results for this numerical differentiation. Sensitivity and its need for high accuracy, especially in the acceleration signal, results in a demand of higher sample frequency. A desire for other profound ways of collecting further information, or to enhance the models, arises with possibilities of future work in the field.

  • 52.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    Active Contours in Three Dimensions1996Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    To find a shape in an image, a technique called snakes or active contours can be used. An active contour is a curve that moves towards the sought-for shape in a way controlled by internal forces - such as rigidity and elasticity - and an image force. The image force should attract the contour to certain features, such as edges, in the image. This is done by creating an attractor image, which defines how strongly each point in the image should attract the contour.

    In this thesis the extension to contours (surfaces) in three dimensional images is studied. Methods of representation of the contour and computation of the internal forces are treated.

    Also, a new way of creating the attractor image, using the orientation tensor to detect planar structure in 3D images, is studied. The new method is not generally superior to those already existing, but still has its uses in specific applications.

    During the project, it turned out that the main problem of active contours in 3D images was instability due to strong internal forces overriding the influence of the attractor image. The problem was solved satisfactory by projecting the elasticity force on the contour’s tangent plane, which was approximated efficiently using sphere-fitting.

  • 53.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Image Coding. Linköping University, The Institute of Technology.
    An active model for facial feature tracking2002In: EURASTP journal an applied signal processing, ISSN 1110-8657, E-ISSN 1687-0433, Vol. 2002, no 6, p. 566-571Article in journal (Refereed)
    Abstract [en]

    We present a system for finding and tracking a face and extract global and local animation parameters from a video sequence. The system uses an initial colour processing step for finding a rough estimate of the position, size, and inplane rotation of the face, followed by a refinement step drived by an active model. The latter step refines the previous estimate, and also extracts local animation parameters. The system is able to track the face and some facial features in near real-time, and can compress the result to a bitstream compliant to MPEG-4 face and body animation.

  • 54.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology. Univ.,.
    Model-based coding: extraction, coding, and evaluation of face model parameters2002Doctoral thesis, monograph (Other academic)
    Abstract [en]

    This thesis deals with model-based coding of human faces for low bitrate communication. The basicidea of model-based coding is that the appearance and motion of a human face are analysed. By thisanalysis, compact parameters allowing realistic visualization of a synthetic face are extracted. The parameterscan be transmitted at very low bitrates, potentially allowing video face-to-face communicationover narrow channels like GSM or PSTN. Recently, numerous web-based applications for animatedfaces have emerged as well.Although the idea is two decades old by now, there are still several technical problems to be solved,and some of them are treated in this thesis. With the advent of the MPEG-4 standard for face animationwhich provides a standardized way for storing and transmitting animation parameters, model-basedcoding and face animation have been increasingly popular research topics.The first topic treated here is th ecompression of face model parameters. We propose a new compressionscheme, showing that such parameters can be transmitted with reasonable quality at bitrates lowerthan 1 kbit/s.Then, techniques for analysis of images and image sequences containing a human face are treated. Forstatic face images, a method for the extraction of facial features is proposed. For image sequences, amethod for face tracking using the active appearance model search algorithmis proposed and foundto be useful in practical experiments. Methods for achieving real-time performance have been developed,and the robustness and accuracy are analysed.To set the analysis in the context of possible applications, different ways of video synthesis using theextracted parameters are discussed as well.Finally, we take a look at the synthesized face models. Comparing them to real video sequences, wetry to evaluate how well the synthetic face models can convey emotions. Standard data sets and performancemeasures are suggested.

  • 55.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering. FOI, SE-58111 Linkoping, Sweden.
    Optimizing Object, Atmosphere, and Sensor Parameters in Thermal Hyperspectral Imagery2017In: IEEE Transactions on Geoscience and Remote Sensing, ISSN 0196-2892, E-ISSN 1558-0644, Vol. 55, no 2, p. 658-670Article in journal (Refereed)
    Abstract [en]

    We address the problem of estimating atmosphere parameters (temperature and water vapor content) from data captured by an airborne thermal hyperspectral imager and propose a method based on linear and nonlinear optimization. The method is used for the estimation of the parameters (temperature and emissivity) of the observed object as well as sensor gain under certain restrictions. The method is analyzed with respect to sensitivity to noise and the number of spectral bands. Simulations with synthetic signatures are performed to validate the analysis, showing that the estimation can be performed with as few as 10-20 spectral bands at moderate noise levels. The proposed method is also extended to exploit additional knowledge, for example, measurements of atmospheric parameters and sensor noise. Additionally, we show how to extend the method in order to improve spectral calibration.

  • 56.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Visualization Techniques for Surveillance: Visualizing What Cannot Be Seen and Hiding What Should Not Be Seen2015In: Konsthistorisk Tidskrift, ISSN 0023-3609, E-ISSN 1651-2294, Vol. 84, no 2, p. 123-138Article in journal (Refereed)
    Abstract [en]

    This paper gives an introduction to some of the problems of modern camera surveillance, and how these problems are, or can be, addressed using visualization techniques. The paper is written from an engineering point of view, attempting to communicate visualization techniques invented in recent years to the non-engineer reader. Most of these techniques have the purpose of facilitating for the surveillance operator to recognize or detect relevant events (such as violence), while, in contrast, some have the purpose of hiding information in order to be less privacy-intrusive. Furthermore, there are also cameras and sensors that produce data that have no natural visible form, and methods for visualizing such data are discussed as well. Finally, in a concluding discussion an attempt is made to predict how the discussed methods and techniques will be used in the future. 

  • 57.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering.
    Arsic, Dejan
    Munich University of Technology, Germany.
    Ganchev, Todor
    University of Patras, Greece.
    Linderhed, Anna
    FOI Swedish Defence Research Agency.
    Menezes, Paolo
    University of Coimbra, Portugal.
    Ntalampiras, Stavros
    University of Patras, Greece.
    Olma, Tadeusz
    MARAC S.A., Greece.
    Potamitis, Ilyas
    Technological Educational Institute of Crete, Greece.
    Ros, Julien
    Probayes SAS, France.
    Prometheus: Prediction and interpretation of human behaviour based on probabilistic structures and heterogeneous sensors2008Conference paper (Refereed)
    Abstract [en]

    The on-going EU funded project Prometheus (FP7-214901) aims at establishing a general framework which links fundamental sensing tasks to automated cognition processes enabling interpretation and short-term prediction of individual and collective human behaviours in unrestricted environments as well as complex human interactions. To achieve the aforementioned goals, the Prometheus consortium works on the following core scientific and technological objectives:

    1. sensor modeling and information fusion from multiple, heterogeneous perceptual modalities;

    2. modeling, localization, and tracking of multiple people;

    3. modeling, recognition, and short-term prediction of continuous complex human behavior.

  • 58.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering. Termisk Systemteknik AB, Linköping, Sweden.
    Berg, Amanda
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering. Termisk Systemteknik AB, Linköping, Sweden.
    Evaluating Template Rescaling in Short-Term Single-Object Tracking2015Conference paper (Refereed)
    Abstract [en]

    In recent years, short-term single-object tracking has emerged has a popular research topic, as it constitutes the core of more general tracking systems. Many such tracking methods are based on matching a part of the image with a template that is learnt online and represented by, for example, a correlation filter or a distribution field. In order for such a tracker to be able to not only find the position, but also the scale, of the tracked object in the next frame, some kind of scale estimation step is needed. This step is sometimes separate from the position estimation step, but is nevertheless jointly evaluated in de facto benchmarks. However, for practical as well as scientific reasons, the scale estimation step should be evaluated separately – for example,theremightincertainsituationsbeothermethodsmore suitable for the task. In this paper, we describe an evaluation method for scale estimation in template-based short-term single-object tracking, and evaluate two state-of-the-art tracking methods where estimation of scale and position are separable.

  • 59.
    Ahlberg, Jörgen
    et al.
    Swedish Defence Research Agency (FOI), Linköping, Sweden.
    Dornaika, Fadi
    Linköping University, Department of Electrical Engineering, Image Coding. Linköping University, The Institute of Technology.
    Efficient active appearance model for real-time head and facial feature tracking2003In: Analysis and Modeling of Faces and Gestures, 2003. AMFG 2003. IEEE International Workshop on, IEEE conference proceedings, 2003, p. 173-180Conference paper (Refereed)
    Abstract [en]

    We address the 3D tracking of pose and animation of the human face in monocular image sequences using active appearance models. The classical appearance-based tracking suffers from two disadvantages: (i) the estimated out-of-plane motions are not very accurate, and (ii) the convergence of the optimization process to desired minima is not guaranteed. We aim at designing an efficient active appearance model, which is able to cope with the above disadvantages by retaining the strengths of feature-based and featureless tracking methodologies. For each frame, the adaptation is split into two consecutive stages. In the first stage, the 3D head pose is recovered using robust statistics and a measure of consistency with a statistical model of a face texture. In the second stage, the local motion associated with some facial features is recovered using the concept of the active appearance model search. Tracking experiments and method comparison demonstrate the robustness and out-performance of the developed framework.

  • 60.
    Ahlberg, Jörgen
    et al.
    Swedish Defence Research Agency, Sweden.
    Folkesson, Martin
    Swedish Defence Research Agency, Sweden.
    Grönwall, Christina
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Horney, Tobias
    Swedish Defence Research Agency, Sweden.
    Jungert, Erland
    Swedish Defence Research Agency, Sweden.
    Klasén, Lena
    Swedish Defence Research Agency, Sweden.
    Ulvklo, Morgan
    Swedish Defence Research Agency, Sweden.
    Ground Target Recognition in a Query-Based Multi-Sensor Information System2006Report (Other academic)
    Abstract [en]

    We present a system covering the complete process for automatic ground target recognition, from sensor data to the user interface, i.e., from low level image processing to high level situation analysis. The system is based on a query language and a query processor, and includes target detection, target recognition, data fusion, presentation and situation analysis. This paper focuses on target recognition and its interaction with the query processor. The target recognitionis executed in sensor nodes, each containing a sensor and the corresponding signal/image processing algorithms. New sensors and algorithms are easily added to the system. The processing of sensor data is performed in two steps; attribute estimation and matching. First, several attributes, like orientation and dimensions, are estimated from the (unknown but detected) targets. These estimates are used to select the models of interest in a matching step, where the targetis matched with a number of target models. Several methods and sensor data types are used in both steps, and data is fused after each step. Experiments have been performed using sensor data from laser radar, thermal and visual cameras. Promising results are reported, demonstrating the capabilities of the target recognition algorithms, the advantages of the two-level data fusion and the query-based system.

  • 61.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Image Coding. Linköping University, The Institute of Technology. Div. of Sensor Technology, Swedish Defence Research Agency, Linköping, Sweden.
    Forchheimer, Robert
    Linköping University, Department of Electrical Engineering, Image Coding. Linköping University, The Institute of Technology.
    Face tracking for model-based coding and face animation2003In: International journal of imaging systems and technology (Print), ISSN 0899-9457, E-ISSN 1098-1098, Vol. 13, no 1, p. 8-22Article in journal (Refereed)
    Abstract [en]

    We present a face and facial feature tracking system able to extract animation parameters describing the motion and articulation of a human face in real-time on consumer hardware. The system is based on a statistical model of face appearance and a search algorithm for adapting the model to an image. Speed and robustness is discussed, and the system evaluated in terms of accuracy.

  • 62.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    Li, Haibo
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    Representing and Compressing MPEG-4 Facial Animation Parameters using Facial Action Basis Functions1999In: IEEE Transactions on Circuits and Systems, ISSN 0098-4094, E-ISSN 1558-1276, Vol. 9, no 3, p. 405-410Article in journal (Refereed)
    Abstract [en]

    In model-based, or semantic, coding, parameters describing the nonrigid motion of objects, e.g., the mimics of a face, are of crucial interest. The facial animation parameters (FAPs) specified in MPEG-4 compose a very rich set of such parameters, allowing a wide range of facial motion. However, the FAPs are typically correlated and also constrained in their motion due to the physiology of the human face. We seek here to utilize this spatial correlation to achieve efficient compression. As it does not introduce any interframe delay, the method is suitable for interactive applications, e.g., videophone and interactive video, where low delay is a vital issue.

  • 63.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering. Glana Sensors AB, Sweden.
    Renhorn, Ingmar
    Glana Sensors AB, Sweden.
    Chevalier, Tomas
    Scienvisic AB, Sweden.
    Rydell, Joakim
    FOI, Swedish Defence Research Agency, Sweden.
    Bergström, David
    FOI, Swedish Defence Research Agency, Sweden.
    Three-dimensional hyperspectral imaging technique2017In: ALGORITHMS AND TECHNOLOGIES FOR MULTISPECTRAL, HYPERSPECTRAL, AND ULTRASPECTRAL IMAGERY XXIII / [ed] Miguel Velez-Reyes; David W. Messinger, SPIE - International Society for Optical Engineering, 2017, Vol. 10198, article id 1019805Conference paper (Refereed)
    Abstract [en]

    Hyperspectral remote sensing based on unmanned airborne vehicles is a field increasing in importance. The combined functionality of simultaneous hyperspectral and geometric modeling is less developed. A configuration has been developed that enables the reconstruction of the hyperspectral three-dimensional (3D) environment. The hyperspectral camera is based on a linear variable filter and a high frame rate, high resolution camera enabling point-to-point matching and 3D reconstruction. This allows the information to be combined into a single and complete 3D hyperspectral model. In this paper, we describe the camera and illustrate capabilities and difficulties through real-world experiments.

  • 64.
    Ahlberg, Jörgen
    et al.
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering.
    Åstrom, Anders
    Swedish Natl Forens Ctr NFC, Linkoping, Sweden.
    Forchheimer, Robert
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Simultaneous sensing, readout, and classification on an intensity-ranking image sensor2018In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 46, no 9, p. 1606-1619Article in journal (Refereed)
    Abstract [en]

    We combine the near-sensor image processing concept with address-event representation leading to an intensity-ranking image sensor (IRIS) and show the benefits of using this type of sensor for image classification. The functionality of IRIS is to output pixel coordinates (X and Y values) continuously as each pixel has collected a certain number of photons. Thus, the pixel outputs will be automatically intensity ranked. By keeping track of the timing of these events, it is possible to record the full dynamic range of the image. However, in many cases, this is not necessary-the intensity ranking in itself gives the needed information for the task at hand. This paper describes techniques for classification and proposes a particular variant (groves) that fits the IRIS architecture well as it can work on the intensity rankings only. Simulation results using the CIFAR-10 dataset compare the results of the proposed method with the more conventional ferns technique. It is concluded that the simultaneous sensing and classification obtainable with the IRIS sensor yields both fast (shorter than full exposure time) and processing-efficient classification.

  • 65.
    Ahlberg, Sven
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Evaluation of Different Radio-Based Indoor Positioning Methods2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Today, positioning with GPS and the advantages this entails are almost infinitive, which means that the technology can be utilized in a variety of applications. Unfortunately, there exists a lot of limitations in conjunction with the signals from the GPS can’t reach inside e.g. buildings or underground. This means that an alternative solution that works indoors needs to be developed.

    The report presents the four most common radio-based technologies, Bluetooth,Wi-Fi, UWB and RFID, which can be used to determine a position. These all have different advantages in cost, accuracy and latency, which means that there exist a number of different applications.

    The radio-based methods use the measurement techniques, RSSI, TOA, TDOA, Cell-ID, PD or AOA to gather data. The choice of measurement technique is mainly dependent of which radio-based method being used, since their accuracy depends on the quality of the measurements and the size of the detection area, which means that all measurement techniques have different advantages and disadvantages.

    The measurement data is processed with one of the positioning methods, LS, NLS, ML, Cell-ID, WC or FP, to estimate a position. The choice of positioning method also depends on the quality of the measurements in combination with the size of the detection area.

    To evaluate the different radio-based methods together with measurement techniques and positioning methods, accuracy, latency and cost are being compared. This is used as the basis for the choice of positioning method, since a general solution can get summarized by finding the least expensive approach which can estimate an unknown position with sufficiently high accuracy.

  • 66.
    Ahlin, Karl
    Linköping University, Department of Electrical Engineering.
    Quality of Service i IP-nätverk2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The original promise behind the Internet Protocol was to deliver data from a sender to the receiver using a best-effort approach. This means that the protocol makes no guarantees except that it will try to deliver the data to the destination. If some problem occurs the packet may be discarded by the network without any notice. No guarantees are made regarding the time it takes to deliver the data, the rate at which data will be delivered or if data is delivered in the same order it was sent. The best-effort approach is arguably the reason behind the success of the Internet Protocol and is what makes IP scalable to networks the size of the Internet. However, this approach is also a problem for network operators who want to offer better quality of service to some of their customers. This master thesis will discuss some of the theories behind the implementation of quality of service schemes in an IP network and also provide an example of how to implement it in an existing network.

  • 67.
    Ahlman, Gustav
    Linköping University, Department of Electrical Engineering, Computer Vision.
    Improved Temporal Resolution Using Parallel Imaging in Radial-Cartesian 3D functional MRI2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    MRI (Magnetic Resonance Imaging) is a medical imaging method that uses magnetic fields in order to retrieve images of the human body. This thesis revolves around a novel acquisition method of 3D fMRI (functional Magnetic Resonance Imaging) called PRESTO-CAN that uses a radial pattern in order to sample the (kx,kz)-plane of k-space (the frequency domain), and a Cartesian sample pattern in the ky-direction. The radial sample pattern allows for a denser sampling of the central parts of k-space, which contain the most basic frequency information about the structure of the recorded object. This allows for higher temporal resolution to be achieved compared with other sampling methods since a fewer amount of total samples are needed in order to retrieve enough information about how the object has changed over time. Since fMRI is mainly used for monitoring blood flow in the brain, increased temporal resolution means that we can be able to track fast changes in brain activity more efficiently.The temporal resolution can be further improved by reducing the time needed for scanning, which in turn can be achieved by applying parallel imaging. One such parallel imaging method is SENSE (SENSitivity Encoding). The scan time is reduced by decreasing the sampling density, which causes aliasing in the recorded images. The aliasing is removed by the SENSE method by utilizing the extra information provided by the fact that multiple receiver coils with differing sensitivities are used during the acquisition. By measuring the sensitivities of the respective receiver coils and solving an equation system with the aliased images, it is possible to calculate how they would have looked like without aliasing.In this master thesis, SENSE has been successfully implemented in PRESTO-CAN. By using normalized convolution in order to refine the sensitivity maps of the receiver coils, images with satisfying quality was able to be reconstructed when reducing the k-space sample rate by a factor of 2, and images of relatively good quality also when the sample rate was reduced by a factor of 4. In this way, this thesis has been able to contribute to the improvement of the temporal resolution of the PRESTO-CAN method.

  • 68.
    Ahlman, Gustav
    et al.
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    Magnusson, Maria
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    Dahlqvist Leinhard, Olof
    Linköping University, Center for Medical Image Science and Visualization (CMIV). Linköping University, Department of Medical and Health Sciences, Radiation Physics. Linköping University, Faculty of Health Sciences.
    Lundberg, Peter
    Linköping University, Center for Medical Image Science and Visualization (CMIV). Linköping University, Department of Medical and Health Sciences, Radiation Physics. Linköping University, Department of Medical and Health Sciences, Radiology. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Center for Surgery, Orthopaedics and Cancer Treatment, Department of Radiation Physics. Östergötlands Läns Landsting, Center for Diagnostics, Department of Radiology in Linköping.
    Increased temporal resolution in radial-Cartesian sampling of k-space by implementation of parallel imaging2011Conference paper (Refereed)
  • 69.
    Ahlqvist, Johan
    Linköping University, Department of Electrical Engineering, Communication Systems.
    Evaluation of the Turbo-decoder Coprocessor on a TMS320C64x Digital Signal Processor2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding.

    This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor.

  • 70.
    Ahlström, Linus
    Linköping University, Department of Electrical Engineering.
    Algoritmer för objektdetektering i SAR och IR-bilder2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The first part of the thesis consists of a brief introduction to the general principles of target detection and the sensor-systems used. In the following part there is a theoretical description of the algorithms this thesis focuses on. The detection algorithms described in this paper are called Cell Average, Ordered Statistics, 2parameter and Gammadetector. Two different discriminators called Extended Fractal Features and Quadratic Gamma Discriminator are also described. The algorithms are tested on three different types of data, simulated SAR-pictures, authentic SAR-targets and IR-pictures. The last part account for the results, both those achieved with pictures and those results achieved when doing statistical tests, in this case MonteCarlo- simulations and Reciever Operating Characteristics-curves. The results show that the Gamma- detector and the QGD-algorithm perform best on the tests done in this thesis.

  • 71.
    Ahlström, Per
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Signalprediktering i vitt gaussiskt brus med hjälp av ett adaptivt signalanpassat filter1976Report (Other academic)
    Abstract [sv]

    Ett signalanpassat filter har ett impulssvar som är den exiterandesignalens spegelbild . Ett dylikt filter maximerar vid en viss tidpunkt signalbrusförhållandet på utgången.

    Ett adaptivt transversalfilter styrt av en gradientkännande algoritm, vilken maximerar signalbrusförhållandet på filterutgången, har studerats. Det spegelvända impulssvaret har använts som prediktion av signalen. Denna prediktion har, vid simulering gjord på dator, ej visat sig vara bättre än en klassisk prediktion med en ren summering av brusstörda upplagor av signalen. Inte ens då dylika summerade upplagor av den brusstörda signalenanvänts som insignal till filtret har signalprediktionen via filtrets impulssvar uppvisat ett lägre kvadratiskt medelfel än d en klassiska.

  • 72.
    Ahlström, Tobias
    et al.
    Linköping University, Department of Electrical Engineering.
    Danev, Danyo
    Linköping University, Department of Electrical Engineering.
    Superimposed Codes for CDMA over Fiber Optic Channels2004In: Ninth International Workshop on Algebraic and Combinatorial Coding Theory,2004, 2004, p. 14-19Conference paper (Refereed)
  • 73.
    Ahmad, Shakeel
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Stimuli Generation Techniques for On-Chip Mixed-Signal Test2010Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

    Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

    Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

    A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

    List of papers
    1. ADC on-Chip Dynamic Test by PWM Technique
    Open this publication in new window or tab >>ADC on-Chip Dynamic Test by PWM Technique
    2008 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2008, p. 15-18Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-43029 (URN)10.1109/ICSES.2008.4673345 (DOI)70959 (Local ID)78-83-88309-47-2 (ISBN)70959 (Archive number)70959 (OAI)
    Conference
    International Conference on Signals and Electronic Systems, ICSES '08, 14-17 Sept, Krakow, Poland
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2010-11-17Bibliographically approved
    2. On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
    Open this publication in new window or tab >>On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
    2009 (English)In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, p. 105-108Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

    Place, publisher, year, edition, pages
    IEEE, 2009
    Keywords
    Stimuli generation, on-chip test
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-20668 (URN)10.1109/ECCTD.2009.5274977 (DOI)000276473700027 ()978-1-4244-3896-9 (ISBN)
    Conference
    European Conference on Circuit Theory and Design, ECCTD 2009, 23-27 Aug., Antalya
    Note
    ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEEAvailable from: 2009-10-13 Created: 2009-09-16 Last updated: 2010-11-17Bibliographically approved
    3. Two-tone PLL for on-chip IP3 test
    Open this publication in new window or tab >>Two-tone PLL for on-chip IP3 test
    2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, p. 3549-3552Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61666 (URN)10.1109/ISCAS.2010.5537812 (DOI)978-1-4244-5308-5 (ISBN)
    Conference
    Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
    4. Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
    Open this publication in new window or tab >>Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
    2010 (English)In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, p. 393-396Conference paper, Published paper (Refereed)
    Abstract [en]

    This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-61668 (URN)978-1-4244-5307-8 (ISBN)
    Conference
    International Conference on Signals and Electronic Systems (ICSES), 7-10 Sept, Gliwice, Poland
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2015-09-14Bibliographically approved
    5. Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
    Open this publication in new window or tab >>Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
    (English)Manuscript (preprint) (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61669 (URN)
    Conference
    IEEE Transactions on Circuits and Systems–II
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
    6. One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
    Open this publication in new window or tab >>One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
    2010 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic) Submitted
    Place, publisher, year, edition, pages
    Springer, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61687 (URN)
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2017-12-12Bibliographically approved
  • 74.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-tone PLL for on-chip IP3 test2010In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, p. 3549-3552Conference paper (Refereed)
    Abstract [en]

    This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

  • 75.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-Tone PLL for on-Chip IP3 Test2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 76.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ADC on-Chip Dynamic Test by PWM Technique2008In: International Conference on Signals and Electronic Systems, IEEE , 2008, p. 15-18Conference paper (Refereed)
    Abstract [en]

    This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

  • 77.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator2010In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, p. 393-396Conference paper (Refereed)
    Abstract [en]

    This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

  • 78.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Univ Management and Technol, Pakistan.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test2019In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 35, no 1, p. 77-85Article in journal (Refereed)
    Abstract [en]

    In this paper a built-in-self-test (BiST) aimed at the third and second intercept point (IP3/IP2) characterization of RF receiver is discussed with a focus on a stimulus generator. The generator is designed based on a specialized phase-lock loop (PLL) architecture with two voltage controlled oscillators (VCOs) operating in GHz frequency range. The objective of PLL is to keep the VCOs frequency spacing under control. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the design of VCOs and analog adder. The PLL reference spurs, critical for the IP3 measurement, are avoided by means of a frequency doubling technique. The circuit is designed in 65nm CMOS. A highly linear analog adder with OIP3amp;gt;+15dBm and ring VCOs with phase noise amp;lt; -104 dBc/Hz at 1MHz offset are used to generate the RF stimulus of total power greater than -22dBm. In simulations a performance sufficient for IP3/IP2 test of a typical RF CMOS receiver is demonstrated.

  • 79.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of Two-Tone RFGenerator for On-Chip IP3/IP2 TestManuscript (preprint) (Other academic)
  • 80.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-Chip Spectral Test for High-Speed ADCs by ΣΔ Technique2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 661-664Conference paper (Refereed)
    Abstract [en]

    Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.

  • 81.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique2009In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, p. 105-108Conference paper (Refereed)
    Abstract [en]

    This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

  • 82.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test2010In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic)
  • 83.
    Ahmadi, Shervin Parvini
    et al.
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, Faculty of Science & Engineering.
    Hansson, Anders
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, Faculty of Science & Engineering.
    Parallel Exploitation for Tree-Structured Coupled Quadratic Programming in Julia2018In: Proceedings of the 22nd International Conference on System Theory, Control and Computing, IEEE, 2018, p. 597-602Conference paper (Refereed)
    Abstract [en]

    The main idea in this paper is to implement a distributed primal-dual interior-point algorithm for loosely coupled Quadratic Programming problems. We implement this in Julia and show how can we exploit parallelism in order to increase the computational speed. We investigate the performance of the algorithm on a Model Predictive Control problem.

  • 84.
    Ahmed Aamir, Syed
    et al.
    University of Bielefeld, Germany .
    Angelov, Pavel
    AnaCatum Design AB, Linkoping, Sweden .
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS2014In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 22, no 4, p. 888-898Article in journal (Refereed)
    Abstract [en]

    This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

  • 85.
    Ahmed Aamir, Syed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob J
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers2013In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, p. 381-384Conference paper (Refereed)
    Abstract [en]

    This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

  • 86.
    Ahmed, Atheeq
    Linköping University, Department of Electrical Engineering, Communication Systems.
    Human Detection Using Ultra Wideband Radar and Continuous Wave Radar2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A radar works by radiating electromagnetic energy and detecting the reflected signal returned from the target. The nature of the reflected signal provides information about the target’s distance or speed. In this thesis, we will be using a UWB radar and a CW radar to help detect the presence and rough location of trapped survivors by detecting their motions. Range is estimated in the UWB radar using clutter removal with SVD and for the dual frequency CW Radar using STFT and median filtering. The effect of the algorithm parameters on their performance was analyzed. The performance of the implemented algorithms with regards to small motion detection, distance estimation and penetration capability was analyzed. Both systems are certainly capable of human detection and tracking.

  • 87.
    Ahmed, Mohsin Niaz
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    LTE Uplink Modeling and Channel Estimation2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis investigates the uplink transmition from User Equipment (UE) to base station in LET (Long Term Evolution) and channel estimation using pilot symbols with parameter defined in 3GPP (3rd Generation Partnership Project) specifications. The purpose of the thesis was to implement a simulator which can generate uplink signal as it is generated by UE. The Third Generation (3G) mobile system was given the name LTE. This thesis focus on the uplink of LTE where single carrier frequency division multiple access (SC-FDMA) is utilized as a multiple access technique. The advantage over the orthogonal frequency division multiple access (OFDMA), which is used in downlink is to get better peak power characteristics. Because in uplink communication better peak power characteristic is necessary for better power efficiency in mobile terminals. To access the performance of uplink transmition realistic channel model for wireless communication system is essential. Channel models used are proposed by International Telecommunication Union (ITU) and the correct knowledge of these models is important for testing, optimization and performance improvements of signal processing algorithms. The channel estimation techniques used are Least Square (LS) and Least Minimum Mean Square Error (LMMSE) for different channel models. Performance of these algorithms has been measured in term of Bit Error Rate (BER) and Signal to Noise Ratio (SNR).

  • 88.
    Ahmed, Tanvir
    Linköping University, Department of Electrical Engineering, Electronics System.
    High Level Model of IEEE 802.15.3c Standard and Implementation of a Suitable FFT on ASIC2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A high level model of HSIPHY mode of IEEE 802.15.3c standard has been constructedin Matlab to optimize the wordlength to achieve a specific bit error rate (BER) depending on the application, and later an FFT has been implemented for different wordlengths depending on the applications. The hardware cost and power is proportional to wordlength. However, the main objective of this thesis has been to implement a low power, low area cost FFT for this standard. For that the whole system has been modeled in Matlab and the signal to noise ratio (SNR) and wordlength of the system have been studied to achieve an acceptable BER. Later an FFT has been implemented on 65nm ASIC for a wordlength of 8, 12 and 16 bits. For the implementation, a Radix-8 algorithm with eight parallel samples has been adopted. That reduce the area and the power consumption significantly compared to other algorithms and architectures. Moreover, a simple control has been used for this implementation. Voltage scaling has been done to reduce thepower. The EDA synthesis result shows that for 16bit wordlength, the FFT has 2.64 GS/s throughput, it takes 1.439 mm2 area on the chip and consume 61.51mW power.

  • 89.
    Ahmed, Tanvir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Garrido, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 512-point 8-parallel pipelined feedforward FFT for WPAN2011In: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), IEEE , 2011, p. 981-984Conference paper (Refereed)
    Abstract [en]

    This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm2.

  • 90.
    Ahmed, Zubair
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design of Autonomous Low Power Sensor for Soil Moisture Measurement.2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Drought is the most severe disaster compared to other disasters in human civilization and their impacts are serious which can cause hungur, thrist, food shortages, loss of livestock directly effects the human life. The main objective of this project is to develop an early warning system (EWS) [3] for drought indices by using wireless sensor networks (WSNs) which is the only way forward for an on-site monitoring and validation of locally defined drought indices [3].The designed wireless sensor network (WSN) consisting of a sensor unit, a master unit and a sensor power management unit (PMU). The sensor unit measures the moisture of the soil and transmitt the measured data through ZigBee module to the master unit. A real time clock (RTC) is also used in the sensor unit which records the information of second, minute, hour, day, month of day and year about when or what time the measurement taken. The master unit consisting of a SD-card and Bluetooth module. SD-card is used to store measured data from other sensor units and it is possible to take out the reading of measured data from the master unit by accessing the SD-card via Bluetooth inside the master unit to a PC or a smartphone mobile.To manage the power in the sensor unit and to make sensor alive for several years, the power management unit (PMU) manages the power level between two energy storage buffers (i.e., a supercapacitor and a Li+ ion battery) for a sensor node.

  • 91.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Programmable and Tunable Circuits for Flexible RF Front Ends2008Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Most of today’s microwave circuits are designed for specific function and specialneed. There is a growing trend to have flexible and reconfigurable circuits. Circuitsthat can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured toachieve the desired performance seems to be challenging. However, with recentadvances in many areas of technology these demands can now be met.

    Two concepts have been investigated in this thesis. The initial part presents thefeasibility of a flexible and programmable circuit (PROMFA) that can be utilized formultifunctional systems operating at microwave frequencies. Design details andPROMFA implementation is presented. This concept is based on an array of genericcells, which consists of a matrix of analog building blocks that can be dynamicallyreconfigured. Either each matrix element can be programmed independently or severalelements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters oroscillators. Realization of a flexible RF circuit based on generic cells is a new concept.In order to validate the idea, a test chip has been fabricated in a 0.2μm GaAs process, ED02AH from OMMICTM. Simulated and measured results are presented along withsome key applications like implementation of a widely tunable band pass filter and anactive corporate feed network.

    The later part of the thesis covers the design and implementation of tunable andwideband highly linear LNAs that can be very useful for multistandard terminals suchas software defined radio (SDR). One of the key components in the design of a flexibleradio is low noise amplifier (LNA). Considering a multimode and multiband radiofront end, the LNA must provide adequate performance within a large frequency band.Optimization of LNA performance for a single frequency band is not suitable for thisapplication. There are two possible solutions for multiband and multimode radio frontends (a) Narrowband tunable LNAs (b) Wideband highly linear LNAs. A dual bandtunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuningtechnique has also been proposed for the optimization of this LNA. This thesis alsopresents the design of a novel highly linear current mode LNA that can be used forwideband RF front ends for multistandard applications. Technology process for thiscircuit is 90nm CMOS.

    List of papers
    1. Applications of Programmable Microwave Function Array (PROMFA)
    Open this publication in new window or tab >>Applications of Programmable Microwave Function Array (PROMFA)
    2007 (English)In: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain, IEEE , 2007, p. 164 -167Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.

    Place, publisher, year, edition, pages
    IEEE, 2007
    Keywords
    Microwave circuits, phase shifters, programmable circuits, active corporate feed network, four-port circuit, generic cells, phase shift capability, programmable microwave function array, tunable recursive filter
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14859 (URN)10.1109/ECCTD.2007.4529562 (DOI)978-1-4244-1341-6 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    2. Dual Band Tunable LNA for Flexible RF Front End
    Open this publication in new window or tab >>Dual Band Tunable LNA for Flexible RF Front End
    2007 (English)In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, p. 19-22Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

    Place, publisher, year, edition, pages
    IEEE Explore, 2007
    Keywords
    Circuit tuning, flexible electronics, gallium arsenide, low noise amplifiers, radiofrequency amplifiers, varactors, wireless LAN
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14860 (URN)10.1109/IBCAST.2007.4379900 (DOI)978-969-8741-04-4 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    3. A Self-Tuning Technique for Optimization of Dual Band LNA
    Open this publication in new window or tab >>A Self-Tuning Technique for Optimization of Dual Band LNA
    2008 (English)In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 178-181Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14862 (URN)978-2-87487-008-8 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2009-05-29Bibliographically approved
    4. Highly Linear Wideband Low Power Current Mode LNA
    Open this publication in new window or tab >>Highly Linear Wideband Low Power Current Mode LNA
    2008 (English)In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, p. 73-76Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14863 (URN)10.1109/ICSES.2008.4673361 (DOI)978-83-88309-47-2 (ISBN)978-83-88309-52-6 (ISBN)
    Conference
    International Conference on Signals and Electronic Systems (ICSES’08), September 14-17, 2008, Krakow, Poland
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2014-05-15Bibliographically approved
  • 92.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reconfigurable and Broadband Circuits for Flexible RF Front Ends2009Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Most of today’s microwave circuits are designed for specific function and special need. There is a growing trend to have flexible and reconfigurable circuits. Circuits that can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured to achieve the desired performance seems to be challenging. However, with recent advances in many areas of technology these demands can now be met.

    Two concepts have been investigated in this thesis. The initial part presents the feasibility of a flexible and programmable circuit (PROMFA) that can be utilized for multifunctional systems operating at microwave frequencies. Design details and PROMFA implementation is presented. This concept is based on an array of generic cells, which consists of a matrix of analog building blocks that can be dynamically reconfigured. Either each matrix element can be programmed independently or several elements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters or oscillators. Realization of a flexible RF circuit based on generic cells is a new concept. In order to validate the idea, two test chips have been fabricated. The first chip implementation was carried out in a 0.2μm GaAs process, ED02AH from OMMICTM. The second chip was implemented in a standard 90nm CMOS process. Simulated and measured results are presented along with some key applications such as low noise amplifier, tunable band pass filter and a tunable oscillator.

    The later part of the thesis covers the design and implementation of broadband RF front-ends that can be utilized for multistandard terminals such as software defined radio (SDR). The concept of low gain, highly linear frontends has been presented. For proof of concept two test chips have been implemented in 90nm CMOS technology process. Simulated and measurement results are presented. These RF front-end implementations utilize wideband designs with active and passive mixer configurations.

    We have also investigated narrowband tunable LNAs. A dual band tunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuning technique has been proposed for the optimization of this LNA.

    List of papers
    1. Applications of Programmable Microwave Function Array (PROMFA)
    Open this publication in new window or tab >>Applications of Programmable Microwave Function Array (PROMFA)
    2007 (English)In: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain, IEEE , 2007, p. 164 -167Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.

    Place, publisher, year, edition, pages
    IEEE, 2007
    Keywords
    Microwave circuits, phase shifters, programmable circuits, active corporate feed network, four-port circuit, generic cells, phase shift capability, programmable microwave function array, tunable recursive filter
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14859 (URN)10.1109/ECCTD.2007.4529562 (DOI)978-1-4244-1341-6 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    2. A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells
    Open this publication in new window or tab >>A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells
    Show others...
    2009 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic) Submitted
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

    Keywords
    CMOS, flexible circuit, generic PROMFA cells, reconfigurable circuit, tunable oscillator, tunable band pass filter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18508 (URN)
    Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2017-12-13Bibliographically approved
    3. Dual Band Tunable LNA for Flexible RF Front End
    Open this publication in new window or tab >>Dual Band Tunable LNA for Flexible RF Front End
    2007 (English)In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, p. 19-22Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

    Place, publisher, year, edition, pages
    IEEE Explore, 2007
    Keywords
    Circuit tuning, flexible electronics, gallium arsenide, low noise amplifiers, radiofrequency amplifiers, varactors, wireless LAN
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14860 (URN)10.1109/IBCAST.2007.4379900 (DOI)978-969-8741-04-4 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    4. A Self-Tuning Technique for Optimization of Dual Band LNA
    Open this publication in new window or tab >>A Self-Tuning Technique for Optimization of Dual Band LNA
    2008 (English)In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 178-181Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14862 (URN)978-2-87487-008-8 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2009-05-29Bibliographically approved
    5. Highly Linear Wideband Low Power Current Mode LNA
    Open this publication in new window or tab >>Highly Linear Wideband Low Power Current Mode LNA
    2008 (English)In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, p. 73-76Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14863 (URN)10.1109/ICSES.2008.4673361 (DOI)978-83-88309-47-2 (ISBN)978-83-88309-52-6 (ISBN)
    Conference
    International Conference on Signals and Electronic Systems (ICSES’08), September 14-17, 2008, Krakow, Poland
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2014-05-15Bibliographically approved
    6. A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
    Open this publication in new window or tab >>A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
    Show others...
    2009 (English)Manuscript (Other academic)
    Abstract [en]

    The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18196 (URN)
    Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-01-14Bibliographically approved
    7. A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
    Open this publication in new window or tab >>A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
    Show others...
    2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, p. 79-90Article in journal (Refereed) Published
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

    Place, publisher, year, edition, pages
    SpringerLink, 2012
    Keywords
    Blocker suppression, common gate (CG), highly linear, low power, multi-standard, software defined radio, wideband front-end
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18511 (URN)10.1007/s10470-011-9667-9 (DOI)000298604100007 ()
    Note
    The original status of this article was: Manuscript.Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2017-12-13Bibliographically approved
  • 93.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Self-Tuning Technique for Optimization of Dual Band LNA2008In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 178-181Conference paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

  • 94.
    Ahsan, Naveed
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A tunable LNA for flexible RF front-end.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 95.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dual Band Tunable LNA for Flexible RF Front End2007In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, p. 19-22Conference paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

  • 96.
    Ahsan, Naveed
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Samuelsson, Carl
    FOI, Linköping.
    Boman, Tomas
    FOI, Linköping.
    A widely tunable filter using generic PROMFA cells.2007In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper (Refereed)
  • 97.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Boman, Tomas
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Applications of Programmable Microwave Function Array (PROMFA)2007In: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain, IEEE , 2007, p. 164 -167Conference paper (Refereed)
    Abstract [en]

    This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.

  • 98.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 99.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Highly Linear Wideband Low Power Current Mode LNA2008In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, p. 73-76Conference paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

  • 100.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, p. 79-90Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

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