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  • 51.
    Larsson, Christer
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A tool for manual scheduling of DSP algorithms implemented in Java1999In: Proc. National Conf. on Radio Science and Communication, RVK'99, 1999, p. I-367-I-369Conference paper (Other academic)
    Abstract [en]

    A program for manual scheduling of digital signal processing algorithms is presented. The program works with a cyclic scheduling formulation that yield maximally fast implementations. The operations can be moved across a number of sample intervals by drag-and-drop-operations. By implementing the program in Java it can be used on all platforms supporting Java.

  • 52. Li, Weidong
    et al.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    An FFT processor based on 16-point module2001In: Proc. NORCHIP'01, 2001, p. 125-130Conference paper (Refereed)
    Abstract [en]

    The number of multiplications has been a key merit for FFT algorithms. It has important impact on the total power consumption. In this paper, we present a 16-point FFT module, which reduc-es the multiplicative complexity by using real constant multiplications. A pipeline FFT proces-sor has been implemented with the 16-point module and simulation result shows that it is an attractive candidate to reduce the power consumption.

  • 53.
    Melander, Johan
    et al.
    n/a.
    Widhe, Torbjörn
    n/a.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    An FFT processor based on the SIC architecture with asynchronous PE1996In: Proc. IEEE 1996 Midwest Symp. on Circuits and Systems, MWSCAS'96, 1996, p. III-1313-III-1316Conference paper (Refereed)
    Abstract [en]

    A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.

  • 54.
    Melander, Johan
    et al.
    n/a.
    Widhe, Torbjörn
    n/a.
    Sandberg, Peter
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of a bit-serial FFT processor with a hierarchical control structure1995In: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95, 1995, p. I-423-I-426Conference paper (Refereed)
    Abstract [en]

    A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high  performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a  hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented  as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.

  • 55.
    Nilsson, Peter
    et al.
    Dept. of Applied Electronics, University of Lund.
    Torkelsson, Mats
    Dept. of Applied Electronics, University of Lund.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock1994In: Mobile Communications Advanced Systems and Components / [ed] Christoph G. Günther, Berlin ; New York: Springer-Vlg, cop. , 1994, p. 510-521Chapter in book (Other academic)
    Abstract [en]

    A chip for digital intermediate frequency filtering is introduced. The filter is intended move most of the analog intermediate frequency filtering to the digital domain in systems like the American mobile radio system (IS-54). It is a wave digital lattice filter realized with bit-serial arithmetic. Furthermore, a technique for local clocks on chip is presented. The method is based on a ring oscillator and a cycle counter which is controlled from outside the chip. A 0.8 micron technology custom test chip has been fabricated and tested.

  • 56.
    Nilsson, Peter
    et al.
    n/a.
    Torkelsson, Mats
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A bit-serial realization of a lattice wave digital intermediate frequency filter1993In: Proc. Sixth Annual IEEE Int. ASIC Conf. and Exhibit, ASIC'93, 1993, p. 197-200Conference paper (Refereed)
    Abstract [en]

    A custom DSP chip for mobile radio systems like the American IS-54 system is presented. The application is a digital intermediate frequency filter which is intended to replace expensive analog filters. It is a lattice wave digital filter with fixed coefficient bit-serial arithmetic. A technique which is useful for area efficient layouts in high throughput real time signal processing is discussed.

  • 57.
    Nilsson, Peter
    et al.
    n/a.
    Torkelsson, Mats
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A high performance bit-serial lattice wave digital intermediate frequency filter chip1993In: Proc. European Conf. on Circuit Theory and Design, ECCTD'93, 1993Conference paper (Refereed)
  • 58.
    Nilsson, Peter
    et al.
    n/a.
    Torkelsson, Mats
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A lattice wave digital intermediate frequency filter chip1993In: Proc. National Conf. on Radio Science, RVK'93, 1993, p. 197-200Conference paper (Other academic)
  • 59.
    Nilsson, Peter
    et al.
    Dept. Applied Electronics, University of Lund.
    Torkelsson, Mats
    Dept. Applied Electronics, University of Lund.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    CMOS on-chip clock for digital signal processors1993In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 15, no 8, p. 669-670Article in journal (Refereed)
    Abstract [en]

    An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.

  • 60.
    Ohlsson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A study on pipeline-interleaved digital filters for low power2001In: Proc. NORCHIP'01, 2001, p. 93-98Conference paper (Refereed)
    Abstract [en]

    Pipeline-interleaving is an implementation method yielding a reduced area. This paper discusses the power consumption for such implementations, compared to a direct implementation. An examplefilter has been implemented, both as a direct structure and a pipeline-interleaved structure, and the results show a 38% and 23% increase in power consumption for correlated and uncorrelated input data respectively using a pipeline-interleaved structure. Possible explanations of the results are discussed for the example filter.

  • 61.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Digital IF filter for mobile radio1995In: Proc. Nordic Radio Symposium, NRS'95, 1995, p. 271-276Conference paper (Other academic)
    Abstract [en]

    A multirate IF filter for mobile radio has been implemented in silicon. The filter consists of a decimation stage followed by a bandpass filter. Both parts use a lattice wave digital structure. The design and implementation are described beginning with the filter specification and proceed through algorithmic design, operations scheduling, and resource allocation and assignment. Every step tries to minimize the amount of resources in the final implementation, thereby reducing power consumption. Finally the architecture is selected and the system is described using synthesizable VHDL in order to arrive at a chip layout using standard-cell technology. This design technique is used to reduce the design work.

  • 62.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and implementation of an interpolator using wave digital filters1993In: Proc. National Conf. on Radio Science, RVK'93, 1993, p. 205-208Conference paper (Other academic)
    Abstract [en]

    The design and implementation of an interpolator using wave digital filters is presented. The interpolator increases the sample frequency with a factor of 4, from 800 kHz to 3.2 MHz. The design approach yields implementations with low power consumption and small chip area. The excellent stability and sensitivity properties of wave digital filters are retained.

  • 63.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Nordhamn, Erik
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A fast bit-serial lattice wave digital filter1992In: Proc. NUTEK Workshop on Digital Communications, 1992, p. 88-92Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss the implementation of maximally fast fixed-function digital filters. We demonstrate by means of an example that digital filters with sampling frequencies of more than hundred MHz can efficiently be implemented by using bit-serial PEs. The proposed approach lead to maximally fast filters that require little chip area and have low power consumption. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying equivalence transformations to the signal-flow graph.

  • 64.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Scheduling of data-independent recursive algorithms1995In: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95, 1995, p. II-855-II-858Conference paper (Refereed)
    Abstract [en]

    A new scheduling formulation for data independent recursive algorithms is proposed. This formulation is intuitive and finds a static rate optimal schedules. Processing elements may be non-preemptive and non-homogenous. Comparison with some other common scheduling methods to increase throughput is made.

  • 65.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Arithmetic transformations for fast bit-serial VLSI implementations of recursive algorithms1996In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, p. 391-394Conference paper (Refereed)
    Abstract [en]

    A method to increase the throughput of static recursive algorithms is presented. The signal-flow graph is transformed by first minimizing the number of summation points in the computational loops. A second transformation to rewrite the fixed coefficient multiplications as a sum of weighted signals is then followed by a reordering of the summations. It is how a sum of products can be implemented in this way. Sharing of sub-expressions are also discussed. A bit-serial implementation of a third order bireciprocal lattice WDF is used to illustrate the transformations and sharing of sub-expressions.

  • 66.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of static DSP algorithms using multiplexed PEs1996In: Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'96, 1996, p. 824-827Conference paper (Refereed)
    Abstract [en]

    An efficient and flexible ASIC implementation method suited for static DSP algorithms is presented. It is aimed at low power implementations with moderate speed requirements. The method allows for the processing elements to be multiplexed in order to reduce the amount of resources required. A method to find a minimal number of resources and a corresponding architecture from the cyclic scheduling formulation is described. An implementation of a wave digital bandpass filter is used as an example. The low power consumption and high resource utilization is obtained by using the cyclic scheduling formulation that leads to a maximally fast implementation. The excess speed can be converted to low power consumption by reducing the power supply voltage.

  • 67. Rudberg, Mikael
    et al.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Niklas
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    A Scrambler and a Method of Scrambling Data Words2001Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    The invention relates generally to D/A converters and more specifically to a method of scrambling or randomization of thermometer coded input data in order to reduce the influence of matching errors in D/A converters.

  • 68.
    Rudberg, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Glitch minimization and dynamic element matching in D/A converters2000In: Proc. 7th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'00, IEEE , 2000, p. 899-902 vol.2Conference paper (Refereed)
    Abstract [en]

    In this paper we present a novel method for combining thermometer coding and dynamic element matching (DEM) in a digital-to-analog converter (DAC). The proposed method combines DEM with a minimization of glitch power. The glitch power may in a DEM solution make a significant contribution to the total noise power. The switch based solution provides a structural solution where it is possible to implement parts of the method, which reduce the area required for implementation.

  • 69.
    Rudberg, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System.
    Scrambler and a method of scrambling data words, (US pat. 2002027519)2002Patent (Other (popular science, discussion, etc.))
  • 70.
    Sadeghi, Vahideh Sadat
    et al.
    Integrated Circuit Research Lab, Babol University of Tehnology, Babol, Iran.
    Saeed, Sohail Imran
    Department of Electrical Engineering, Linköping University, Linköping, Sweden.
    Calnan, Shane
    Department of Electrical & Electronic Engineering University College Cork, Ireland.
    Kennedy, Michael Peter
    Department of Electrical & Electronic Engineering University College Cork, Ireland.
    Naimi, Hossein Miar
    Integrated Circuit Research Lab, Babol University of Tehnology, Babol, Iran.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Simulation and experimental investigation of a nonlinear mechanism for spur generation in a fractional-N frequency synthesizer2012Conference paper (Refereed)
    Abstract [en]

    The performance of fractional-N frequency synthesizers in wireless communications applications is degraded by the presence of spurious tones. While the Digital Delta-Sigma Modulator (DDSM) can be directly responsible for the production of such tones, a range of deterministic and stochastic techniques have been invented to eliminate the principal causes associated with the architecture of the DDSM. A second source of spurs, when the spectrum of the DDSM iteself is spur-free, is (analogue) nonlinearities in the synthesizer. Recent work has predicted that specific nonlinearities will produce tones at well-defined frequencies; this paper presents simulation and experimental verification of the prediction.

  • 71.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A dynamic element matching technique for flash analog-to-digital converters2004In: Proc. 8th Nordic Signal Processing Symp., NORSIG'04, 2004, p. 137-140Conference paper (Refereed)
    Abstract [en]

    A flash analog-to-digital converter is proposed that employs a new dynamic element matching architecture. The architecture uses a new strategy of incorporating switches in the voltage reference generator that allows lower hardware complexity and higher conversion speed than comparable converters. The converter has been modeled and simulated on a behavioral level in Matlab. The results indicate good linearity properties that together with the expected speed performance should make it suitable in intended communications applications.

  • 72.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications2005In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05, 2005, p. I/127-I/130Conference paper (Refereed)
    Abstract [en]

    The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

  • 73.
    Säll, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    6-bit flash ADC with dynamic element matching2006In: Proc. IEEE 24th Norchip Conf., NORCHIP'06, 2006, , p. 159-162p. 159-162Conference paper (Refereed)
    Abstract [en]

    Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter. The converter is sent for manufacturing in a 130 nm partially depleted silicon-on-insulator CMOS technology. It was simulated at transistor level in Cadence using the foundry provided BSIM3SOI Eldo models. These simulations yield a maximum sampling frequency of at least 350 MHz. The simulations also indicate a performance improvement in terms of spurious free dynamic range when using dynamic element matching.

  • 74.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A multiplexer based decoder for flash analog-to-digital converters2004In: Proc. IEEE TENCON 2004, 2004, p. 250-253Conference paper (Refereed)
    Abstract [en]

    A decoder for flash analog-to-digital converters with short critical path, regular structure, and small area is presented. The decoder is based on 2:1 multiplexers connected as a tree. Each level of the tree divides the input thermometer scale in two and calculates one of the bits in the binary output. In comparison with the Wallace tree decoder and the folded decoder the length of the critical path is approximately reduced to one third and one half, respectively. The amount of hardware is also reduced, which is likely to translate to a power saving, compared with the Wallace tree decoder and the folded decoder.

  • 75.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Comparison of two thermometer-to-binary decoders for high-performance flash ADCs2005In: Proc. IEEE 23rd NORCHIP Conf., NORCHIP'05, 2005, p. 253-256Conference paper (Refereed)
    Abstract [en]

    The performance of flash analog-to-digital converters is affected significantly by the choice of thermometer-tobinary decoder topology. In this work two different promising decoder topologies, multiplexer-based and onescounter, are evaluated. Two converters with different decoders, but otherwise similar, are therefore designed. Two test chips are also sent for manufacturing in a 130 nm silicon-on-insulator CMOS technology. The converter performance is evaluated by simulations using foundry provided models. The results show that both decoders can be used in high-speed converters, but the ones-counter decoder is more robust and yield a higher converter efficiency.

  • 76.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Design and evaluation of a comparator in CMOS SOI2005In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper (Other academic)
    Abstract [en]

    The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-onchip in SOI. A comparator has therefore been designed and manufactured in a 0.13 um partially depleted SOI CMOS technology. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz, or above. An introduction to the silicon-on-insulator (SOI) technology is also given and some of the major advantages and disadvantages of using SOI are presented.

  • 77.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Design of a comparator in CMOS SOI2004In: Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, p. 229-232Conference paper (Refereed)
    Abstract [en]

    This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 μm partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz.

  • 78.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Mixed signal design in SOI CMOS technology2005In: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Conference paper (Other academic)
    Abstract [en]

    The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-on-chip in silicon-on-insulator (SOI). A 6-bit flash analog-to-digital converter (ADC) has therefore been designed and manufactured in a 130 nm partially depleted SOI CMOS technology. The ADC is designed for a sampling frequency of 1.5 GHz or above. An introduction to the SOI technology is also given and some of the major advantages and disadvantages of using SOI are presented.

  • 79.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Silicon-on-insulator CMOS technology for system-on-chip2004In: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Conference paper (Other academic)
    Abstract [en]

    This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. Some unwanted effects is introduced when using SOI, compared with bulk, of which the kink effect, history effect and self heating are the most important. Methods to compensate for these effects are presented. At the end a comparison between bulk and SOI devices is done, from which we conclude that the SOI technologies appears to be more suited for the future sub nanometer and low supply voltage technologies, than bulk technologies. The power consumption is also expected to decrease if SOI is used instead of bulk devices.

  • 80.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Thermometer-to-binary decoders for flash analog-to-digital converters2007In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 240-243Conference paper (Refereed)
    Abstract [en]

    Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.

  • 81.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering.
    A study of digital decoders in flash analog-to-digital converters2004In: Proc. IEEE Int. Symp. Circuits Syst., ISCAS'04, 2004, p. I-129-I-132Conference paper (Refereed)
  • 82.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Andersson, Niklas U.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Synthesis of time-to-digital convertersManuscript (preprint) (Other academic)
    Abstract [en]

    We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.

  • 83.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A novel technique to reduce the supply sensitivity of CMOS ring oscillators2014Manuscript (preprint) (Other academic)
    Abstract [en]

    A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

  • 84.
    Touqir Pasha, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    A modified switching scheme for multiplexer based thermometer-to-binary encoders2014In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

  • 85. Touqir Pasha, Muhammad
    et al.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Frequency control schemes for single ended ring oscillators2011In: 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden, IEEE , 2011, p. 361-364Conference paper (Refereed)
    Abstract [en]

    An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.

  • 86.
    Unnikrishnan, Vishnu
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Time-Mode Analog-to-Digital Conversion Using Standard Cells2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 12, p. 3348-3357Article in journal (Refereed)
    Abstract [en]

    Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

  • 87.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-transistor CMOS full adder with full voltage-swing nodes1999In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'99, 1999, p. 713-722Conference paper (Refereed)
    Abstract [en]

    We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 μm process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder

  • 88.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A new six-transistor CMOS XOR circuit with complementary output1999In: Proc. IEEE 1999 Midwest Symp. on Circuits and Systems, MWSCAS'99, 1999, p. II-796-II-799Conference paper (Refereed)
    Abstract [en]

    A new CMOS XOR circuit based on pass transistors is proposed. It uses only six transistors to produce both an XOR and the complementary XNOR function. The circuit has full voltage-swing and negligible static power dissipation. A drawback is that the transistors need to be ratioed due to a feedback structure. Simulation results for the new circuit compared to simulation results for a reference XOR circuit indicated that the energy consumption was similar for the circuits. However, the propagation delay was 50% longer for the new circuit, due to the feedback structure. The main advantage of the new circuit was the reduction in device count from eight to six transistors.

  • 89.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A robust differential scan flip-flop1999In: Proc. 1999 IEEE Int. Symp. on Circuits and Systems, ISCAS'99, 1999, p. I-334-I-337Conference paper (Refereed)
    Abstract [en]

    A flip-flop is proposed that is robust against smooth clock edges. This robustness simplifies the design of the clock net in large integrated circuits and lowers the power consumed in the clock driver compared to flip-flops needing sharper clock edges. The proposed flip-flop is realized using 20 MOSFETs and uses a single phase clock. It includes a multiplexer circuit at the input that is useful in a scan test. The flip-flop is semi-static in the sense that the master latch is static while the slave latch is dynamic. This allows the clock to be in the low state for an indefinitely long period, while the period of the high state is limited due to charge leakage. Therefore another circuit is also proposed that limits the pulse width of the clock. The use of this circuit enables design of a scan chain that can be clocked with an arbitrarily low frequency.

  • 90.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A static CMOS master-slave flip-flop experiment2000In: Proc. 7th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'00, IEEE , 2000, p. 870-873 vol.2Conference paper (Refereed)
    Abstract [en]

    A variant of a classical master-slave flip-flop based on transmission gates is derived where the transmission gates are replaced by static CMOS gates. The transmission gate flip-flop and the variant are evaluated along with one flip-flop based on C2MOS latches and another based on SR latches. All flip-flops are edge-triggered. The propagation delay, set-up time, and hold time are estimated using a 0.35 μm process. The author also investigates how the power dissipation at the maximal clock frequency varies when the supply voltage is scaled, both when the device geometry is kept constant and when it is scaled to yield good noise margins. In comparison, the variant on master-slave flip-flop has short propagation delay, but is only average in terms of throughput and power consumption. The flip-flop realized with C2 MOS latches seems to be a better candidate for a general-purpose implementation when voltage scaling is an option

  • 91.
    Vesterbacka, Mark
    Linköping University.
    DEM in Pipeline ADCs2010Other (Other academic)
    Abstract [en]

    A DEM technique for ADCs is presented. The technique scrambles the hardware used for producing the reference levels of an ADC or DAC. At the core is a circular resistor net with random connection to the reference supply. A conceptual design of a pipeline ADC stage is given, where the ADC and DAC share the DEM circuitry.

  • 92.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Linear-coded D/A converters with small relative error due to glitches2001In: Proc. IEEE 2001 Midwest Symp. on Circuits and Systems, MWSCAS'01, 2001, p. I-280-I-283Conference paper (Refereed)
    Abstract [en]

    Two encoding schemes aimed at improving the glitch performance of flash D/A converters are proposed. The schemes use an encoding with linearly increasing source weights. Estimates based on a first-order model of the relative error due to glitches show an improvement with several orders of magnitude over existing D/A converters.

  • 93.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Realization of serial/parallel multipliers with fixed coefficients1993In: Proc. National Conf. on Radio Science, RVK'93, 1993, p. 209-212Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss trade-offs in the realization of serial/parallel multipliers with fixed coefficients. The coefficients are represented as two-complement binary numbers or in canonic sign digit code.

  • 94.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Substrate Noise Reduction in Mixed-Signal ICs: BWRC seminar Sept. 25, 20092009Other (Other academic)
    Abstract [en]

    Technological advancements allow more and more functionality to be put on a single silicon chip. We do now have advanced computers on-chip complete with many means of communication over radio and cable, connecting equipment and people. The system integration yields many favorable properties like low cost, size and energy consumption. However, there is an increasing challenge to design the electronics systems due to high complexity and an aggravated environment for the analog circuits in terms of substrate noise and operating voltage. We will address the noise issue, which generally shows up as a side effect of the digital computations. Methods for reducing the noise are discussed, including a new frequency domain approach.

  • 95.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Ola
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Niklas
    n/a.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Using different weights in DACs2002In: Proc. 4th IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and their Applications, ADDA'02, 2002Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss some properties of different codes with their respective sets of weights to be used in digital-to-analog converters (DACs). The thermometer (unratioed) code is widely used instead of a binary code in the most significant bits of a segmented DAC to reduce errors due to weight and timing mismatch. The binary and thermometer codes are two extremes, where the first offers a small digital hardware cost and the latter a large cost. We have investigated some of the properties of these codes and codes with properties in-between; such as linear, polynomial, and segmented codes. Some new ideas and results on using different sets of weights and how to generate them are presented. We present simulation results for some low-order polynomial codes.

  • 96.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of narrow-band lattice wave digital filters1998In: Proc. 1998 IEEE Nordic Signal Processing Symp., NORSIG'98, 1998, p. 153-156Conference paper (Refereed)
    Abstract [en]

    Recently, a filter structure for narrow-band filtering based on lattice wave digital filters was introduced. The structure has increased parallelism over the corresponding direct realization. In this paper, hardware implementation of the filter structure is discussed. The suggested approach uses bit-serial processing elements that are scheduled so that a maximally fast implementation is achieved. An example is given where our implementation approach increases the sample frequency by a factor of 4 compared to a direct realization.

  • 97.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Madsen, Jan
    n/a.
    Selected Papers from NORCHIP '062008In: IET Computers & Digital Techniques, ISSN 1751-8601, E-ISSN 1751-861X, Vol. 2, no 4, p. 251-325Article in journal (Other academic)
  • 98.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of fast bit-serial lattice wave digital filters1994In: Proc. 1994 IEEE Int. Symp. on Circuits and Systems, ISCAS'94, 1994, p. II-113-II-116Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss the design and implementation of fixed-function wave digital lattice filters. We demonstrate by means of an example that a sampling frequency of more than 130 MHz can be achieved by using bit-serial arithmetic. The proposed approach leads to very fast filters with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. (1981) often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of filters.

  • 99.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sandberg, Peter
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Implementation of fast DSP algorithms using bit-serial arithmetic1994In: National Conf. on Electronic Design Automation, EDA-meeting'94, 1994Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. The proposed approach leads to very fast recursive algorithms with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of DSP algorithms.

  • 100.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Palmkvist, Kent
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A CAD tool for synthesis of maximally fast lattice wave digital filters1999In: Proc. National Conf. on Radio Science and Communication, RVK'99, 1999, p. 456-460Conference paper (Other academic)
    Abstract [en]

    A synthesis tool has been developed that implements the scheduling and the hardware mapping of maximally fast, bit-serial lattice wave digital filters. Such implementa­tions are of interest for use in high-speed applications or in low-power applications after supply voltage scaling. The tool generates a synthesizable VHDL hardware netlist from a set of coefficients describing the filter. The VHDL netlist is further mapped to an ASIC using tools from Mentor Graphics. Currently the tool is capable of synthesizing two lattice wave digital filter structures as well as optimizing the structure for cases like the birecip­rocal form of the filter.

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