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  • 51.
    Karlström, Per
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 42006Inngår i: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, s. 31-34Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

  • 52.
    Karlström, Per
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    NoGAP: A Micro Architecture Construction Framework2009Inngår i: Embedded Computer Systems: Architectures, Modeling, and Simulation: 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings / [ed] Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong, Berlin: Springer Berlin/Heidelberg, 2009, 1, s. 171-180Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a vide variety of fields. However the design of an ASIP is today a substantial design effort. This paper discusses NoGAP (Novel Generator for ASIP) a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of NoGAP compared to other ADL tools is that it does not impose limits on the architecture and thus design freedom. To reach this flexibility NoGAP makes heavy use of the compositional design principle and is therefore divided into three parts Mage, Mase, and Castle. This paper presents the central concepts of NoGAP to show that it is possible to reach this advertised flexibility and still be able to generate HDL code and tools such as simulators and assemblers.

  • 53.
    Karlström, Per
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Zhou, Wenbiao
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Automatic Assembler Generator for NoGAP2010Inngår i: Ph.D. Research in Microelectronics and Electronics, 2010Konferansepaper (Fagfellevurdert)
  • 54.
    Karlström, Per
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Zhou, Wenbiao
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Automatic Port and Bus Sizing in NoGAP2010Inngår i: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2010, s. 258-264Konferansepaper (Fagfellevurdert)
    Abstract [en]

    ASIP processors and programmable accelerators are replacing monolithic ASICs in more and more areas. However the design and implementation of a new ASIP processor or programmable accelerator requires a substantial design effort. There are a number of existing tools that promise to ease this design effort, but using these tools usually means that the designer get locked into the tools a priori assumtions and it is therefore hard to develop truly novel ASIPs or accelerators. NoGAP is a tool that delivers design support while not locking the designer into any predefined template architecture. An important aspect of NoGAPs design process is the ability to design the data path of each instruction individually. Therefore the size of input/output ports can sometimes not be known while designing the individual functional units. For this reason we have introduced the concept of dynamic port sizes, which is an extension of the parameter/generic concept in Verilog/VHDL. A problem arises if the data path graph contains loops, either due to intra or inter instruction dependencies. This paper will present the algorithm used to solve this looping problem.

  • 55.
    Karlström, Per
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Zhou, Wenbiao
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Operation Classification for Control Path Synthetization with NoGAP2010Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGAP (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of NoGAP compared to other ADL tools is that it does not impose limits on the architecture and thus design freedom. NoGAP does not assume a fixed processor template and is not another data flow synthesizer. To reach this flexibility NoGAP makes heavy use of the compositional design principle and is therefore divided into three parts Mage, Mase, and Castle. This paper discusses the techniques used in NoGAP for control path synthetization. A RISC processor has been constructed with NoGAP in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178MHz in a Virtex-4 LX80 speedgrade 12.

  • 56.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Application specific instruction set DSP processors2010Inngår i: Handbook of signal processing systems / [ed] Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, New York: Springer, 2010, s. 415-447Kapittel i bok, del av antologi (Fagfellevurdert)
  • 57.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Embedded DSP Processor Design: Application Specific Instruction Set Processors2008Bok (Annet (populærvitenskap, debatt, mm))
    Abstract [en]

       

  • 58.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Sohl, Joar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Petersson, Magnus
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Zhou, Wenbiao
    Beijing Institute of Technologies, China.
    ePUMA embedded parallel DSP processor with Unique Memory Access2011Inngår i: Information, Communications and Signal Processing (ICICS), 2011, IEEE , 2011, s. 1-5Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Computing unto 100GOPS without cooling is essential for high-end embedded systems and much required by markets. A novel master-slave multi-SIMD architecture and its kernel (template) based parallel programming flow is thus introduced as a parallel signal processing platform, ePUMA, embedded Parallel DSP processor with Unique Memory Access. It is an on chip multi-DSP-processor (CMP) targeting to predictable signal processing for communications and multimedia. The essential technologies are to separate the processing of control stream from parallel computing, and to separate parallel data access from parallel arithmetic computing kernels. By separations, the computation and data access can be orthogonal both in hardware and in programs. Orthogonal operations can therefore be executed in parallel and the run time cost of data access can be minimized. Benchmark shows that the computing performance therefore reaches about 80% of the hardware limit. Less than 40% of the hardware limit can be reached by normal processors. The unique SIMD memory subsystem architecture offers programmable conflict free parallel data accesses. Programming flow and tools are also developed to support coding on the unique hardware architecture. A prototype on FPGA shows especially high performance over silicon cost.

  • 59.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nilsson, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Eilert, Johan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Bridging Dream and Reality: Programmable Baseband Processors for Software-Defined Radio2009Inngår i: IEEE COMMUNICATIONS MAGAZINE, ISSN 0163-6804, Vol. 47, nr 9, s. 134-140Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A programmable radio baseband signal processor is one of the essential enablers of software-defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

  • 60.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Ronny
    Ericsson Microelectronics.
    Norling, Fredrik
    Ericsson Microelectronics.
    Full digital driving voice and audio load on an IC2002Inngår i: International Conference of Communications, Circuits and Systems,2002, 2002Konferansepaper (Fagfellevurdert)
  • 61.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Nordqvist, Ulf
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Configuration-based architecture for high speed and general-purpose protocol processing1999Inngår i: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, s. 540-547Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

  • 62.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Olausson, Mikael
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    The ADSP-21535 Blackfin and speech coding2003Inngår i: Swedish System-on-Chip Conference SSoCC,2003, 2003Konferansepaper (Annet vitenskapelig)
  • 63.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Sohl, Joar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Parallel Programming and its architectures Based on data access separated algorithm Kernels2010Inngår i: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, E-ISSN 1947-3184, Vol. 1, nr 1, s. 65-85Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing. Copyright © 2010, IGI Global.

  • 64.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Hardware Architecture for a Multi Mode Block Interleaver2004Inngår i: International Conference on Circuits and Systems for Communications, ICCSC,2004, 2004Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We are interested in developing a programmable baseband processor for software defined radio and are trying to find configurable hardware blocks that can be used in multiple radio standards, including for example wireless LAN and 3G standards. This paper suggests an architecture for a multi mode block interleaver that is suitable e.g. for the IEEE 802.11a and 802.11g standards. Our implementation is based on a special matrix memory to which data is written as rows but read out as columns. To enable a comparison, an interleaver for theWireless LAN standard 802.11a has been implemented both using our suggested architecture and using a traditional interleaver implementation based on a bit memory. Our implementation reaches a significantly higher performance and a lower power consumption with no extra area. The price to pay is a small loss of generality.

  • 65.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Low-Power Baseband Processors for Communications2004Inngår i: Low-Power Electronics Design / [ed] Christian Piguet, CRC Press , 2004, 1, s. -912Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management. The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now.

  • 66.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Implemenation of Programmable Baseband Processors2004Inngår i: CCIC,2004, 2004Konferansepaper (Fagfellevurdert)
  • 67.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Söderquist, Ingemar
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Fully flexible baseband DSP processors for future SDR/JTRS2005Inngår i: Western European Armaments Organization WEAO,2005, 2005Konferansepaper (Annet vitenskapelig)
  • 68.
    Liu, Dake
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Wang, Zhihua
    Tsinghua Univ, Elect Engn, Beijing, Peoples R China.
    Luo, Li
    BJTU, Beijing, Peoples R China.
    Editorial Material: SPECIAL ISSUE ON COMMUNICATION IC in CHINA COMMUNICATIONS, vol 12, issue 5, pp III-VI2015Inngår i: China Communications, ISSN 1673-5447, Vol. 12, nr 5, s. III-VIArtikkel i tidsskrift (Annet vitenskapelig)
    Abstract [en]

    n/a

  • 69.
    Liu, Dake
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Seger, Olle
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Sathe, Sumant
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Svensson, Erik
    SoC BUS: The solution of high communication bandwidth on chip and short TTM2002Inngår i: Real Time and Embedded Computing Conference,2002, 2002Konferansepaper (Fagfellevurdert)
  • 70.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Area efficient fully programmable baseband processors2007Inngår i: SAMOSVII Workshop; SAMOS, Greece, July 16-19, 2007Konferansepaper (Fagfellevurdert)
  • 71.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Multi-standard support in SIMT programmable baseband processors2006Inngår i: SSoCC Swedish System-on-chip Conference,2006, 2006Konferansepaper (Annet vitenskapelig)
  • 72.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Processor friendly peak-to-average reduction in multi-carrier systems2004Inngår i: Swedish system-on-Chip Conference, SSoCC 04,2004, 2004Konferansepaper (Annet vitenskapelig)
  • 73.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    A fully programmable Rake-receiver architecture for multi-standard baseband processors2005Inngår i: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, s. 292-297Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

  • 74.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    A Programmable SIMD-based Multi-standard Rake Receiver Architecture2005Inngår i: European Signal Processing Conference, EUSIPCO, Antalya, Turkey, 2005Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability with its associated flexibility will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and MRC-based channel equalization for several CDMA-based wireless transmission systems in software. Our processor is based on a DSP core with SIMD-computing clusters. We have mapped Rake receiver kernel-functions supporting several 3G standards to this micro-architecture and benchmarking shows that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA FDD/TDD-modes and HSDPA at clock rate not exceeding 76 MHz during soft handover conditions.

  • 75.
    Nilsson, Anders
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Tell, Eric
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Acceleration in multi-standard baseband processors2005Inngår i: Radiovetenskap och Kommunikation,2005, 2005Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an architecture for fully programmable baseband processing, based on a programmable DSP processor and a number of configurable accelerators which communicate via a configurable network. Acceleration of common cycleconsuming DSP jobs is necessary in order to manage wide-band modulation schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband processor supporting a number of common Wireless LAN and 3G standards. Benchmarking show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 76.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    An 11 mm(2), 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12 mu m CMOS2009Inngår i: IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA: Vol 44, number 1, IEEE , 2009, Vol. 44, nr 1, s. 90-97Konferansepaper (Fagfellevurdert)
    Abstract [en]

    With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm(2) in a 0.12 mu m CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.

  • 77.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    An accelerator structure for programmable multi-standard baseband processors2004Inngår i: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, s. 644-649Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 78.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Simultaneous multistandard support in programmable baseband processors2006Inngår i: Proceedings of IEEE PRIME 2006, Otranto, Italy, 2006Konferansepaper (Fagfellevurdert)
  • 79.
    Nilsson, Anders
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Tell, Eric
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wiklund, Daniel
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Design methodology for memory-efficient multi-standard baseband processors2005Inngår i: Asia Pacific Communication Conference, Perth, Australia, 2005, s. 28-32Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.

  • 80.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Henriksson, Tomas
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Configurable CRC Generator2002Inngår i: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, s. 192-Konferansepaper (Fagfellevurdert)
  • 81.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Henriksson, Tomas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    CRC generation for protocol processing2000Inngår i: Proceedings of NORCHIP 2000, 2000, s. 288-293Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

    A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

  • 82.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Comparative Study of Protocol Processors2002Inngår i: Conference on Computer Science and Systems Engineering,2002, 2002, s. 107-Konferansepaper (Fagfellevurdert)
  • 83.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Control path in a protocol processor2003Inngår i: Midwest symposium on circuits and systems MWCAS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 84.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Packet Classification and Termination in a Protocol Processor2003Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

  • 85.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Packet classification and termination in a protocol processor2003Inngår i: Network processor design - Issues and practices, vol 2 / [ed] Mark A. Franklin, Patrick Crowley , Haldun Hadimioglu, Peter Z. Onufryk, Elsevier , 2003, 1, s. 159-180Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. ·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

  • 86.
    Nordqvist, Ulf
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Power optimized packet buffering in a protocol processor2003Inngår i: International conference on electronic circuits and systems, ICECS,2003, 2003Konferansepaper (Fagfellevurdert)
  • 87.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Edman, Anders
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Bit memory instructions for a general CPU2004Inngår i: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, s. 215-218Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

  • 88.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Ehliar, Andreas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Eilert, Johan
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Reduced floating point for MPEG1/2 layer III decoding2004Inngår i: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, s. V-209-12 vol.5-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

  • 89.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Instruction and hardware acceleration for MP-MLQ in G.723.12002Inngår i: IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02)., 2002, s. 235-239Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.

  • 90.
    Olausson, Mikael
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.7292001Inngår i: Proceedings of the 1st IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2001, s. 34-39Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper makes accelerations on instruction level based on the three speech coding algorithms G.723.1, 6.3 kbit/s and 5.3 kbit/s and G.729 8 kbit/s with hardware implementation. All these three algorithms are proposed by the H.323 standard together with G.711 64 kbit/s and G.728 16 kbit/s. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions [I], [2]. Three hardware structures are proposed to increase the performance.

  • 91.
    Ragnemalm, Ingemar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Adapting the ePUMA Architecture for Hand-held Video Games2012Inngår i: International Journal of Computer Information Systems and Industrial Management Applications, ISSN 2150-7988, Vol. 4, s. 153-160Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The ePUMA architecture is a novel parallel archi- tecture being developed as a platform for low-power computing, typically for embedded or hand-held devices. It was originally designed for radio baseband processors for hand-held devices and for radio base stations. It has also been adapted for executing high definition video CODECs. In this paper, we investigate the possibilities and limitations of the platform for real-time graphics, with focus on hand-held gaming.

  • 92.
    Ragnemalm, Ingemar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Towards using the ePUMA architecture for hand-held video games2010Inngår i: COMPUTER GRAPHICS,  VISUALIZATION, COMPUTER VISION  AND IMAGE PROCESSING 2010, 2010, s. 380--384Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The ePUMA architecture is a novel parallel architecture being developed as a platform for low-power computing,

    typically for embedded or hand-held devices. It was originally designed for radio baseband processors for hand-held

    devices and for radio base stations. It has also been adapted for executing high definition video CODECs. In this paper,

    we investigate the possibilities and limitations of the platform for real-time graphics, with focus on hand-held gaming.

  • 93. Sathe, Sumant
    et al.
    Wiklund, Daniel
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Design of a switching node (router) for on-chip networks2003Inngår i: Int Conference on ASIS ASICON,2003, 2003Konferansepaper (Fagfellevurdert)
  • 94.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Conflict-free data access for multi-bank memory architectures using padding2013Inngår i: High Performance Computing (HiPC), 2013, IEEE , 2013, s. 425-432Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For high performance computation memory access is a major issue. Whether it is a supercomputer, a GPGPU device, or an Application Specific Instruction set Processor (ASIP) for Digital Signal Processing (DSP) parallel execution is a necessity. A high rate of computation puts pressure on the memory access, and it is often non-trivial to maximize the data rate to the execution units. Many algorithms that from a computational point of view can be implemented efficiently on parallel architectures fail to achieve significant speed-ups. The reason is very often that the speed-up possible with the available execution units are poorly utilized due to inefficient data access. This paper shows a method for improving the access time for sequences of data that are completely static at the cost of extra memory. This is done by resolving memory conflicts by using padding. The method can be automatically applied and it is shown to significantly reduce the data access time for sorting and FFTs. The execution time for the FFT is improved with up to a factor of 3.4 and for sorting by a factor of up to 8.

  • 95.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Karlsson, Andréas
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Automatic Permutation for Arbitrary Static Access Patterns2012Inngår i: Parallel and Distributed Processing with Applications (ISPA), 2012, IEEE , 2012, s. 215-222Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A significant portion of the execution time on current SIMD and VLIW processors is spent on data access rather than instructions that perform actual computations. The ePUMA architecture provides features that allow arbitrary data elements to be accessed in parallel as long as the elements reside in different memory banks. Using permutation to move data elements that are accessed in parallel, the overhead from memory access can be greatly reduced; and, in many cases completely removed. This paper presents a practical method for automatic permutation based on Integer Linear Programming (ILP). No assumptions are made about the structure of the access patterns other than their static nature. Methods for speeding up the solution time for periodic access patterns and reusing existing solutions are also presented. Benchmarks for e.g. FFTs show speedups of up to 3.4 when using permutation compared to regular implementations.

  • 96.
    Sohl, Joar
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Wang, Jian
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture2009Inngår i: ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS, Springer Berlin/Heidelberg, 2009, s. 408-419Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper introduces a novel master-multi-SIMD on-chip multi-core architecture for embedded signal processing. The parallel architecture and its memory subsystem are described in this paper. We evaluate the large size matrix multiplication performance on this parallel architecture and compare it with a SIMD-extended data parallel architecture. We also examine how well the new architecture scales for different numbers of SIMD co-processors. The experimental results show that the ePUMA architecture's memory subsystem can effectively hide the data access overhead. With its 8-way SIMD data path and multi-SIMD parallel execution, the ePUMA architecture improves the performance of matrix multiplication with a speedup of 45x from the conventional SIMD extension.

  • 97.
    Svensson, Christer
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Presenting efficient hardware solutions for SDR terminals.2006Inngår i: Software Defined Radio 2006,2006, 2006Konferansepaper (Fagfellevurdert)
  • 98.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Suitable Channel Equalization Scheme for IEEE 802.11b2003Inngår i: Swedish System-on-Chip Conference,2003, 2003Konferansepaper (Annet vitenskapelig)
  • 99.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Low Area and Low Power Programmable Baseband Processor Architecture2005Inngår i: International workshop on SoC for real-time applications,2005, 2005Konferansepaper (Fagfellevurdert)
  • 100.
    Tell, Eric
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Nilsson, Anders
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    Liu, Dake
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Datorteknik.
    A Programmable DSP core for Baseband Processing2005Inngår i: IEEE Northeast Workshop on Circuits and Systems NEWCAS,2005, 2005Konferansepaper (Fagfellevurdert)
123 51 - 100 of 137
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