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  • 51.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    A parameterized cell-based design approach for digital-to-analog converters2004Ingår i: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, s. 225-228Konferensbidrag (Refereegranskat)
    Abstract [en]

    Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.

  • 52.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik.
    A testbed for different codes in digital-to-analog converters2004Ingår i: Proc. Swedish System-on-Chip Conf. 2004, SSoCC'04, 2004Konferensbidrag (Övrigt vetenskapligt)
  • 53.
    Andersson, Ola
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    A yield-enhancement strategy for binary-weighted DACs2005Ingår i: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05, 2005, , s. 55-58s. 55-58Konferensbidrag (Refereegranskat)
    Abstract [en]

    One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.

  • 54.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Dynamic element matching in decomposed digital-to-analog converters2004Ingår i: Proc. IEEE NORCHIP'04, Denmark: TechnoData A/S , 2004, , s. 187-190s. 187-190Konferensbidrag (Refereegranskat)
    Abstract [en]

    A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.

  • 55. Andersson, Ola
    et al.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters2005Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, Vol. 52, nr 11, s. 2265-2275Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.

  • 56.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Partial decomposition of digital-to-analog converters2004Ingår i: Proc. 12th IEEE Mediterranean Electrotechnical Conf., MELECON'04, 2004, s. 193-196Konferensbidrag (Refereegranskat)
    Abstract [en]

    The decomposed DAC architecture was recently proposed as an alternative to the traditional segmented architecture. In this work, we present a modified version of the decomposed architecture with reduced hardware complexity denoted the partially decomposed architecture. Behavioral-level simulations indicate that the partially decomposed architecture is a good alternative for signals with Gaussian distribution, whereas the original decomposed or segmented architectures are preferred for sinusoidal signals.

  • 57.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Characterization of a CMOS current-steering DAC using state-space models2000Ingår i: Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, IEEE , 2000, Vol. 2, s. 668-671 vol.2Konferensbidrag (Refereegranskat)
    Abstract [en]

    Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters

  • 58.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Digital-to-analog converter having error correction2002Patent (Övrig (populärvetenskap, debatt, mm))
    Abstract [en]

    The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n−1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

  • 59.
    Andersson, Ola
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs1999Ingår i: Proceedings of the 17th Norchip Conference, 1999Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.

  • 60.
    Andersson, Olof
    et al.
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Komplexa material och system. Linköpings universitet, Tekniska fakulteten.
    Maas, Joris
    Holst Ctr TNO, Netherlands.
    Gelinck, Gerwin
    Holst Ctr TNO, Netherlands; Eindhoven Univ Technol, Netherlands.
    Kemerink, Martijn
    Linköpings universitet, Institutionen för fysik, kemi och biologi, Biomolekylär och Organisk Elektronik. Linköpings universitet, Tekniska fakulteten.
    Scalable Electronic Ratchet with Over 10% Rectification Efficiency2020Ingår i: ADVANCED SCIENCE, ISSN 2198-3844, artikel-id 1902428Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Electronic ratchets use a periodic potential with broken inversion symmetry to rectify undirected (electromagnetic, EM) forces and can in principle be a complement to conventional diode-based designs. Unfortunately, ratchet devices reported to date have low or undetermined power conversion efficiencies, hampering applicability. Combining experiments and numerical modeling, field-effect transistor-based ratchets are investigated in which the driving signal is coupled into the accumulation layer via interdigitated finger electrodes that are capacitively coupled to the field effect transistor channel region. The output current-voltage curves of these ratchets can have a fill factor amp;gt;amp;gt; 0.25 which is highly favorable for the power output. Experimentally, a maximum power conversion efficiency well over 10% at 5 MHz, which is the highest reported value for an electronic ratchet, is determined. Device simulations indicate this number can be increased further by increasing the device asymmetry. A scaling analysis shows that the frequency range of optimal performance can be scaled to the THz regime, and possibly beyond, while adhering to technologically realistic parameters. Concomitantly, the power output density increases from approximate to 4 W m(-2) to approximate to 1 MW m(-2). Hence, this type of ratchet device can rectify high-frequency EM fields at reasonable efficiencies, potentially paving the way for actual use as energy harvester.

  • 61.
    Andersson, Oscar
    Linköpings universitet, Institutionen för ekonomisk och industriell utveckling.
    Energikombinat i Halmstads fjärrvärmesystem2007Självständigt arbete på avancerad nivå (magisterexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [sv]

    Klimatförändringar börjar allt mer få en viktig roll i allas vardag och för energibranschen har arbetet med att minska miljöpåverkan bara börjat. Branschen har sedan en tid tillbaka premierat fjärrvärme som bra miljöval för uppvärmningskälla för bostäder och lokaler. Faktum kvarstår dock att beroende på hur fjärrvärmesystemet ser ut så påverkar näten miljön olika. I denna rapport behandlas det lokala energibolaget Halmstads Energi och Miljös fjärrvärmesystem genom en optimering av systemkostnaden. Utifrån optimeringen studeras sedan skuggpriser, drift och miljöpåverkan för systemet. Studien behandlar även de stora fördelarna med att energibolaget samarbetar med en eventuellt kommande energikrävande industrier, i detta fall en etanolfabrik. I och med samarbetet bildas ett energikombinat där fjärrvärme, el och etanol tillverkas.

    För analysen används ett energisystemperspektiv som får större geografiska gränser än bara Halmstad. Undersökningen av systemet görs med hjälp av datorprogrammet MODEST som är ett energioptimeringsprogram som utvecklats på Linköpings Tekniska högskola. Modellen av Halmstads fjärrvärmenät baseras och valideras mot driftsäsongen 2005 och har visat sig stämma med verkligheten bra.

    Resultatet visar att Halmstad Energi och Miljö planerade effekthöjningar används fullt ut men att det nätet kommer få stora effekttoppar inom en snar framtid. Energikombinatet som analyseras visar sig både ha ekonomiska som miljöfördelar för både energibolaget och en etanolfabrik. Spillvärmen som kan utvinnas kan även den minska användningen av topplastanläggningarna i fjärrvärmenätet.

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  • 62.
    Andersson, Per-Oskar
    Linköpings universitet, Institutionen för systemteknik.
    Rhapsody on small processor platforms2008Självständigt arbete på avancerad nivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [sv]

    Rhapsody är ett verktyg för modelldriven utveckling och design av inbyggda system och realtidssystem. Syftet med detta examensarbete är att undersöka om Rhapsody kan användas för att utveckla mjukvara till små processorplattformar som Atmel’s AVR. Då Rhapsody normalt används till plattformar med ett operativsystem behöver vissa modifieringar göras för att möjliggöra utveckling mot plattformar utan operativsystem. Dessa modifieringar, deras för och nackdelar samt påverkan på utvecklingsprocessen undersöks medan AVR-mjukvara porteras till Rhapsody. Mjukvaran som porteras är en del av styrsystemet till en av CC Systems produkter: CC Pilot XL II, en robust fordonsdator.

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  • 63.
    Andersson, Peter
    Linköpings universitet, Institutionen för systemteknik.
    Design of a channel board used in an electronic warfare target simulator2006Självständigt arbete på avancerad nivå (magisterexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    A channel board was designed for a DRFM circuit. The DRFM is implemented in a Virtex-4 FPGA from Xilinx. In the future a similar channel board is intended to be used for target echo generation in ELSI which is an electronic warfare simulator at Saab Bofors Dynamics in Linköping.

    Besides the DRFM circuit the channel board consists of analog-to-digital converters, digital-to-analog converters, Ethernet plug-in board with a microcontroller, voltage regulators, FPGA configuration memory, voltage amplifiers, current amplifiers, oscillator, buffers/drivers and bus transceivers. The sample rate is 200 MHz and LVDS signalling standard is used between the DRFM circuit and the converters.

    The channel board has a JTAG interface which enables in-system programming of the FPGA. This implies that the DRFM can easily be redesigned. An external computer can manage the channel board via Ethernet. Software was developed for the microcontroller on the channel board and for the external computer. The function of the channel board is heavily dependent on the DRFM circuit.

    The channel board design resulted in the assembly of a prototype circuit board. Measurements were performed in a lab and the channel board was approved to be integrated in ELSI for further tests.

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  • 64.
    Andersson, Peter
    Linköpings universitet, Institutionen för systemteknik.
    Implementering av digitalt vågfilter av Richardstyp i FPGA2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [sv]

    Ett digitalt vågfilter av Richardstyp har implementerats i en FPGA på ett utvecklingskort. Sampel kan skickas till filtret och mottas från filtret via serieporten på en dator. Metoden som användes är att en modell av filtret konstruerades i Simulink. Filtret har modifierats med avseende på skalning, brus och stabilitet. VHDL-koden till filtret genererades i Simulink genom att bygga modellen av Xilinx Blockset. Ytterligare VHDL-kod konstruerades för att kunna skicka sampel mellan filter och minnet på utvecklingskortet. För kommunikation mellan minnet på utvecklingskortet och dator utnyttjades färdiga lösningar.

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  • 65.
    Andersson, Peter
    Linköpings universitet, Institutionen för systemteknik.
    Överföring av digital video via FireWire2002Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    Transmission of digital signals is today more frequently used than transmission of analog signals. One reason for this is that a digital signal is less sensitive to noise than an analog, another reason is that almost all signals today are handled in a digital format. This thesis describes the development of a system that receives digital video signals through FireWire. The standard for FireWire, which is a high performance serial bus, is under development. Today the standard of the bus supports transmission of data with a speed of up to 400 Mbit/s. In the future FireWire is supposed to transmit data with a speed of up to 3,2 Gbit/s. The thesis gives an introduction to the technique for FireWire and how it is implemented. It also includes a short description of digital video signals in DVCAM format.

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  • 66.
    Andersson, Pontus
    Linköpings universitet, Institutionen för teknik och naturvetenskap.
    Visuell processreglering2007Självständigt arbete på grundnivå (kandidatexamen), 10 poäng / 15 hpStudentuppsats
    Abstract [sv]

    Examensarbetet handlar om att ta fram en processmodell för nivåreglering och det innehåller flera utmaningar. Vätskesystemets dynamik och balans måste beaktas likväl som lämpliga reglermetoder samt modellens utseende. I den här rapporten behandlas hela händelseförloppet från initialskedet till en färdig produkt redo att visas för en publik. Läsaren får möjlighet att närmare granska de komponenter som modellen är uppbyggd av, ta del av programmeringsarbetet och de omfattande test av modellen som utförts. Flera teknikområden belyses men fokus riktas särskilt på ABB:s styrsystem AC800M/800xA, fältbussteknik och reglerstrategier. PID-regulatorn har under arbetet spelat en stor roll och reglerstrategier som innefattar bl.a. framkoppling och kaskadkoppling analyseras och diskuteras. För att bedöma skillnader i val av reglermetod används grafer från praktiska försök. Rapportens upplägg med flertalet illustrationer och den genomgripande tekniska dokumentationen hjälper läsaren att förstå modellens funktion och uppbyggnad.

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  • 67.
    Andersson, Robby
    Linköpings universitet, Institutionen för systemteknik.
    FPGA design of a controller for a CAN controller.2003Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This diploma work describes how an FPGA is designed to control a CAN controller. It describes the different tools used when working with Actel’s design tools and the sequence of work applied. It gives a short overview of a multiplexer, the CAN bus, an analog/digital-converter and some more information on the actual FPGA. It also brings up the design process of the FPGA, planning, coding, simulating, testing and finally programming the FPGA. The different parts implemented in the FPGA are a shift-register and two state- machines that are connected with each other. They work together to control the SJA1000 CAN controller made by Philips. They also receive data from the analog/digital-converter that they forward onwards to the CAN controller that forward the data on the CAN bus.

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  • 68. Beställ onlineKöp publikationen >>
    Andersson, Stefan
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Multiband LNA Design and RF-Sampling Front-Ends for Flexible Wireless Receivers2006Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC.

    One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands.

    Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.

    Delarbeten
    1. A Tuned, Inductorless, Recursive Filter LNA in CMOS
    Öppna denna publikation i ny flik eller fönster >>A Tuned, Inductorless, Recursive Filter LNA in CMOS
    2002 (Engelska)Ingår i: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), Florens, Italy, September, 2002, s. 351-354Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    An active recursive filter approach is proposed for the implementation of an inductorless, tuned LNA in CMOS. Such an LNA was designed and fabricated ina 0.8 μm CMOS process. In simulation, the feasibility of this type of LNA was demonstrated, and reasonably good performance was obtained. The fabricated device shows a center frequency tuning range from 250 MHz to 975 MHz. Gain and Q value are tunable in a wide range. The LNA exhibits an input referred 1 dB compression point of -31 dB m and a noise figure of approximately 3 dB measured at 900 MHz center frequency.

    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14084 (URN)
    Konferens
    28th European Solid-State Circuit Conference (ESSCIRC). Firenze, Italy, September 24-26, 2002.
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2013-10-31
    2. An Active Recursive RF Filter in 0.35 μm BiCMOS
    Öppna denna publikation i ny flik eller fönster >>An Active Recursive RF Filter in 0.35 μm BiCMOS
    2005 (Engelska)Ingår i: Journal of Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, Vol. 44, nr 3, s. 213-218Artikel i tidskrift (Refereegranskat) Published
    Abstract [en]

    An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is −26 and −34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.

    Nyckelord
    active filter, tuneable recursive filter for multicarrier systems, inductorless RF filter, tuneable gain and Q
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14085 (URN)10.1007/s10470-005-3002-2 (DOI)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2013-10-31
    3. A 750 MHz to 3 GHz Tunable Narrowband Low-Noise Amplifier
    Öppna denna publikation i ny flik eller fönster >>A 750 MHz to 3 GHz Tunable Narrowband Low-Noise Amplifier
    2005 (Engelska)Ingår i: Proceedings of the Norchip 2005 Conference, Oulu, Finland, 2005, s. 8-11Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    An active recursive filter approach is proposed for the implementation of an inductorless, tunable LNA in CMOS. A test circuit was designed and manufactured in a 0.18 μm CMOS technology. The feasibility of this type of LNA was demonstrated in both simulations and measurements and reasonably good performance was obtained. The measurements show a center frequency tuning range from 0.75-3 GHz and a minimum noise figure of 4.8 dB. Gain and Q value are also tunable in a wide range. Measured IIP-3 and 1-dB compression point is -24 dBm and -29.5 dBm respectively, measured at the center frequency 1.7 GHz and with 21 dB gain.

    Nyckelord
    CMOS integrated circuits, UHF amplifiers, active filters, circuit tuning, integrated circuit design, low noise amplifiers, recursive filters, CMOS technology, active recursive filter, inductorless low-noise amplifier, tunable narrowband low-noise amplifier
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14086 (URN)10.1109/NORCHP.2005.1596976 (DOI)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16
    4. Wideband LNA for a Multistandard Wireless Receiver in 0.18 μm CMOS
    Öppna denna publikation i ny flik eller fönster >>Wideband LNA for a Multistandard Wireless Receiver in 0.18 μm CMOS
    2003 (Engelska)Ingår i: Proceedings of the 29th European Solid-State Circuits Conference, 2003. ESSCIRC '03, 2003, s. 655-658Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    A differential wideband LNA for a multistandard receiver has been designed and implemented in 0.18μm CMOS. The circuit topology is a two-stage amplifier with active feedback. The input stage is a common-source stage with a common-drain stage in the feedback loop for impedance matching. Bandwidth enhancement with inductive shunt-peaking is used for maximizing the bandwidth. Measurements on the fabricated device show a power gain of 13.1 dB and a 3-dB bandwidth of nearly 7 GHz together with an IIP3 and a 1-dB compression point of -4.7 dBm and -15.2 dBm respectively. The measured noise figures are 3.3 dB at 1 GHz and 5.5 dB at 6 GHz. Reported LNAs with similar performance are usually implemented with bipolar transistors or MESFETs.

    Nyckelord
    CMOS integrated circuits, integrated circuit design, radio receivers, wideband amplifiers
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14087 (URN)10.1109/ESSCIRC.2003.1257220 (DOI)0-7803-7995-0 (ISBN)
    Konferens
    29th European Solid-State Circuits Conference, 2003. Estoril, Portugal, September 16-18.
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2013-10-31
    5. Wideband LNA for aMultistandard RF-Sampling Front-End in 0.13 μm CMOS
    Öppna denna publikation i ny flik eller fönster >>Wideband LNA for aMultistandard RF-Sampling Front-End in 0.13 μm CMOS
    (Engelska)Manuskript (Övrigt vetenskapligt)
    Abstract [en]

    The pad pitch of modern RF ICs is in order of few tens of micrometers. Connecting the large number of high speed I/Os to outside world with good signal fidelity and low cost is extremely challenging. To cope with this requirement, we need reflection-free transmission lines from on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow to wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that impedance variation is less then 3Ω for 50Ω microstrip when the width changes from 165μm to 940μm and substrate thickness changes from 100μm to 500μm. The Sparameter measurement on same microstrip shows S11 better then -9dB for the frequency range 1-6GHz

    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14088 (URN)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2018-10-08
    6. Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies
    Öppna denna publikation i ny flik eller fönster >>Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies
    2004 (Engelska)Ingår i: Proceedings of the Norchip 2004 Conference, Oslo, Norway, November, 2004, s. 123-126Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    In this paper, measurements of drain thermal noise for three NMOS devices with different channel lengths was carried out. The three NMOS devices were all implemented in a 0.18 μm CMOS technology, with channel lengths 0.18. 0.36, and 0.72 μm, respectively. The result was then compared with simulated data using the BSIM3- model and parameters provided by the vendor Large discrepancies between measurements and simulations were observed. This work was done in order to understand how to utilize transistor length as a design parameter to achieve optimal noise gures for wideband LNAs in deep submicron technologies.

    Nyckelord
    CMOS, wideband LNAs
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14089 (URN)10.1109/NORCHP.2004.1423838 (DOI)0-7803-8510-1 (ISBN)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2013-10-31
    7. SC Filter for RF Down Conversion with Wideband Image Rejection
    Öppna denna publikation i ny flik eller fönster >>SC Filter for RF Down Conversion with Wideband Image Rejection
    2006 (Engelska)Ingår i: Proceedings of the ISCAS 2006 conference, Kos, Greece, 2006, s. 3542-3545Konferensbidrag, Publicerat paper (Refereegranskat)
    Nyckelord
    SF filter, RF downconversion, RF sampling
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14090 (URN)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2009-04-24
    8. SC Filter for RF Sampling and Downconversion with Wideband Image Rejection
    Öppna denna publikation i ny flik eller fönster >>SC Filter for RF Sampling and Downconversion with Wideband Image Rejection
    2006 (Engelska)Ingår i: Journal of Analog Integrated Circuits and Signal Processing by Springer, special issue: MIXDES, ISSN 0925-1030, Vol. 49, nr 2, s. 115-122Artikel i tidskrift (Refereegranskat) Published
    Abstract [en]

    In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.

    Nyckelord
    RF sampling, Decimation filter, SC filter, Wideband image rejection
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14091 (URN)10.1007/s10470-006-7833-2 (DOI)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16
    9. Noise Analysis and Noise Estimation of an RF-Sampling Front-End using an SC Decimation Filter
    Öppna denna publikation i ny flik eller fönster >>Noise Analysis and Noise Estimation of an RF-Sampling Front-End using an SC Decimation Filter
    2006 (Engelska)Ingår i: Proceedings of the MIXDES 2006 Conference, Gdynia, Poland, 2006, s. 343-348Konferensbidrag, Publicerat paper (Refereegranskat)
    Nyckelord
    RF sampling, decimation, thermal- and 1/f-noise, SC filter
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14092 (URN)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2009-04-24
    10. Multiband Direct RF-Sampling Receiver Front-End for WLAN in 0.13 μm CMOS
    Öppna denna publikation i ny flik eller fönster >>Multiband Direct RF-Sampling Receiver Front-End for WLAN in 0.13 μm CMOS
    (Engelska)Manuskript (Övrigt vetenskapligt)
    Abstract [en]

    In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.

    Identifikatorer
    urn:nbn:se:liu:diva-14093 (URN)10.1109/ECCTD.2007.4529563 (DOI)
    Tillgänglig från: 2006-10-16 Skapad: 2006-10-16 Senast uppdaterad: 2014-08-19
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    FULLTEXT01
  • 69.
    Andersson, Tobias
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Wahlsten, Johan
    Linköpings universitet, Institutionen för systemteknik.
    Delta-Sigma Modulation Applied to Switching RF Power Amplifiers2007Självständigt arbete på grundnivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [en]

    Background:

    The task of this thesis is to investigate the possibility of using non-linear high efficiency switching power amplifiers with spectrally efficient varying envelope modulation schemes and, if possible, further investigate such a solution on a high level.

    The thesis focuses on the theory necessary to understand the technical issues related to power amplifiers and the procedures behind simulating and measuring the characteristics of different power amplifier configurations. The thesis also covers basic theory behind Delta-Sigma-modulators. The theory is needed to draw conclusions about the feasibility of using a Delta-Sigma-modulator as input to a switching amplifier.

    Results:

    Using a Delta-Sigma-modulated input to a switching amplifier inherently degrades the performance, mainly because of poor coding efficiency and high switching activity. However, by merely using a switching amplifier as a mixer it is shown to be possible to transmit a non-constant envelope signal, with digital logic. The resulting circuit is, however, not an amplifier and it should not be seen as the final result. As already mentioned: the result lies in the investigation of a using Delta-Sigma-modulator as input to a switching amplifier.

    Conclusion:

    From this investigation we believe that the widely known technique: pulse width modulation (PWM), together with a tuned switching amplifier and some linearization technique, for example pre-distortion, is a better way to go. Much effort should be put in understanding the fundamental limits and possibilities of an efficient tuned switching power amplifier.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 70.
    Andrén, Filip
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik.
    Optimization of Random Access in 3G Long Term Evolution2009Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    Before a mobile can commence services it needs to have access to a base station. The access method is often referred to as random access (RA). One way to measure the performance of the RA procedure is the access delay (AD) of the mobiles, where AD is the time from which a mobile wants to start a RA attempt until it has received access.

    There are different approaches to optimize the RA procedure. Manual optimization is possible but costly. Automated optimization is preferable because of the lower costs and the possibility to change configuration fast in the base station when the operational conditions change. This thesis focuses on automated optimization of the RA procedure with regard to AD.

    A controllability and observability study of AD is first presented in this thesis. The controllability study shows that AD can be controlled by a number of RA parameters, whereas the observability study show that AD cannot always be correctly observed. The next part of this thesis presents a controller synthesis, where three different controllers are presented to control a specified percentile of AD. It is shown, through experiments, that the controllers derived can be used to optimize the RA procedure with regard to AD.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 71.
    Angelov, Pavel
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Design of an Input Multiplexer for Video Applications2011Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    In modern home entertainment video systems the digital interconnection between the different components is becoming increasingly common. However, analog signal sources are still in widespread use and must be supported by new devices. In order to keep costs down, the digital and the analog receiver chains are implemented on a single die to form a system-on-chip (SoC). For such integrated circuits, it is beneficial to reduce the number of power supply domains to a minimum and preferably use the core voltage to power the analog circuits.

    An eight-to-one input multiplexer, targeted for video digitizer applications, is presented. Together with the multiplexer, a simple current-mode DC restoration circuit is provided. The goal has been to design the circuits for a standard, single-well, 65 nm CMOS process, entirely using low-voltage core transistors and a single 1.1 V supply domain, while allowing the input signal voltages to extend beyond the supply rails.

    To fulfill the requirements, a bootstrap technique has been proposed for the implementation of the multiplexer switches. Bootstrapping a CMOS switch allows high linearity, as well as wide bandwidth and dynamic range, to be achieved with a very low supply voltage. The simulated performance is: 3 dB bandwidth of 536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of 65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistor is stressed by high voltages, therefore, the circuit reliability is guaranteed. The DC restoration circuit utilizes the main video ADC, for measuring the DC level, and is capable of setting it with an accuracy of 60 μV within the range of 100 mV to 500 mV.

    Ladda ner fulltext (pdf)
    FULLTEXT03
  • 72.
    Angelov, Pavel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Nielsen Lönn, Martin
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting2019Rapport (Övrigt vetenskapligt)
    Abstract [en]

    This report presents the analysis of a novel capacitance-based multilevel bias flip rectifier used to increase the output power from a piezoelectric vibration energy harvesting system. The ideal voltage flipping efficiency is calculated based on the number of levels used followed by an analysis of the power losses caused by the bottom-plate parasitic capacitance of the flying capacitor used to distribute the charge between the levels. Then the time to complete the bias flip is examined and the difference between using either a diode or energy investment is investigated. This analysis is intended to be used for aiding in the design of such a system.

    Ladda ner fulltext (pdf)
    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting
  • 73.
    Angelov, Pavel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Nielsen Lönn, Martin
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Ring-oscillator-based timing generator for ultralow-power applications2017Ingår i: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 74.
    Antelius, Henrik
    Linköpings universitet, Institutionen för systemteknik.
    Retargeting a C Compiler for a DSP Processor2004Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    The purpose of this thesis is to retarget a C compiler for a DSP processor.

    Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors.

    This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.

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    FULLTEXT01
  • 75.
    Anton, Gagner
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Hebib, Nino
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    FPGA Software Development for Control Purposes of High-Frequency Switching Power Converters2016Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    FPGA stands for Field Programmable Gate Array and it is a technology that has been on the rise the last decades. With a decrease in size of the logic elements commercially available products have started to have more built-in functionality in one package and by being reprogrammable makes the system a powerful competitor among its neighbors. FPGA technology in comparison with Digital Signal Processing technology is generally interesting because of the parallelism of the programming that can be made. This allows for more operations in less time. In this thesis a system is developed to control power converters with control signals in high frequency. A previous project is used as a base and a toolchain of new components are implemented to create a new, more generic system. The previous system is evaluated and a new protocol for communication is developed. The toolchain with the necessary control blocks is implemented in Quartus II that includes a timer block, a pulse width modulation block, a PID controller block and a FIR-filter block. The system is used to control a power converter and the result is evaluated.

    Ladda ner fulltext (pdf)
    FPGA Software Development for Control Purposes of High-Frequency Switching Power Converters
  • 76.
    Arbring, Joel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Informationskodning.
    Hedström, Patrik
    Linköpings universitet, Institutionen för systemteknik, Informationskodning.
    On Data Compression for TDOA Localization2010Självständigt arbete på avancerad nivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    This master thesis investigates different approaches to data compression on common types of signals in the context of localization by estimating time difference of arrival (TDOA). The thesis includes evaluation of the compression schemes using recorded data, collected as part of the thesis work. This evaluation shows that compression is possible while preserving localization accuracy.

    The recorded data is backed up with more extensive simulations using a free space propagation model without attenuation. The signals investigated are flat spectrum signals, signals using phase-shift keying and single side band speech signals. Signals with low bandwidth are given precedence over high bandwidth signals, since they require more data in order to get an accurate localization estimate.

    The compression methods used are transform based schemes. The transforms utilized are the Karhunen-Loéve transform and the discrete Fourier transform. Different approaches for quantization of the transform components are examined, one of them being zonal sampling.

    Localization is performed in the Fourier domain by calculating the steered response power from the cross-spectral density matrix. The simulations are performed in Matlab using three recording nodes in a symmetrical geometry.

    The performance of localization accuracy is compared with the Cramér-Rao bound for flat spectrum signals using the standard deviation of the localization error from the compressed signals.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 77.
    Arshad, Sana
    et al.
    NED University of Engn and Technology, Pakistan.
    Ramzan, Rashad.
    United Arab Emirates University, U Arab Emirates.
    Zafar, Faiza
    NED University of Engn and Technology, Pakistan.
    Wahab, Qamar-Ul
    Linköpings universitet, Institutionen för fysik, kemi och biologi. Linköpings universitet, Tekniska fakulteten. NED Univ Engn and Technol, Dept Elect Engn, Pakistan.
    Highly Linear Inductively Degenerated 0.13 mu m CMOS LNA using FDC Technique2014Ingår i: 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), IEEE , 2014, s. 225-228Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, a highly linear, inductively degenerated, common source narrowband LNA is presented. An extremely simple feed-forward distortion circuit (FDC) which consists of an appropriately sized ac-coupled diode connected NMOS is proposed. This circuit generates distortion components at output, when added at the input node as a feed forward element (M-6). These distortion components partially cancel the 3rd order nonlinearity of the cascode pair (M-2 and M-3), thus improving the overall linearity of LNA. The prototype is manufactured in standard 0.13 mu m CMOS process from IBM. Simulation and partial measurement results show the S11 and S22 to be -19.27dB and -7.14dB respectively at 2.45GHz. The simulation results of the LNA demonstrate a power gain of 18.5dB, NF of 4.38dB, input referred 1dBCP of -11.76dBm and IIP3 of +0.7dBm consuming 27.7mA from 1.0V power supply. The proposed LNA achieves the best input referred IIP3 reported in recent literature using 0.13 mu m CMOS in 2.4GHz frequency band.

  • 78.
    Arvidsson, Amanda
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Generic Control of Permanent Magnet Synchronous Motors2014Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    -

    Ladda ner fulltext (pdf)
    fulltext
  • 79. Beställ onlineKöp publikationen >>
    Arwidson, Jonas
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Thermal Fatigue Life Prediction of Solder Joints in Avionics by Surrogate Modeling: A Contribution to Physics of Failure in Reliability Prediction2013Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    Manufacturers of aerospace, defense, and high performance (ADHP) equipment are currently facing multiple challenges related to the reliability of electronic systems. The continuing reduction in size of electronic components combined with increasing clock frequencies and greater functionality, results in increased power density. As an effect, controlling the temperature of electronic components is central in electronic product development in order to maintain and potentially improve the reliability of the equipment. Simultaneously, the transition to lead-free electronic equipment will most probably propagate also to the ADHP industry. Compared to well-proven tin-lead solder, the knowledge about field operation reliability of lead-free solders is still limited, as well as the availability of damage evaluation models validated for field temperature conditions. Hence, the need to fill in several knowledge gaps related to reliability and reliability prediction of lead-free solder alloys is emphasized. Having perceived increasing problems experienced in the reliability of fielded equipment, the ADHP industry has suggested inclusion of physics-of-failure (PoF) in reliability prediction of electronics as one potential measure to improve the reliability of the electronic systems.

    This thesis aims to contribute to the development of reliable ADHP systems, with the main focus on electronic equipment for the aerospace industry. In order to accomplish this, the thesis provides design guidelines for power distribution on a double-sided printed circuit board assembly (PBA) as a measure to improve the thermal performance without increasing the weight of the system, and a novel, computationally efficient method for PoF-based evaluation of damage accumulation in solder joints in harsh, non-cyclic field operation temperature environments.

    Thermal fatigue failure mechanisms and state‑of‑the‑art thermal design and design tools are presented, with focus on the requirements that may arise from avionic use, such as low weight, high reliability, and ability to sustain functional during high vibration levels and high g-forces. Paper I, II, and III describes an in-depth investigation that has been performed utilizing advanced thermal modeling of power distribution on a double-sided PBA as a measure to improve the thermal performance of electronic modules.

    Paper IV contributes to increasing the accuracy of thermal fatigue life prediction in solder joints, by employing existing analytical models for predicting thermal fatigue life, but enhancing the prediction result by incorporating advanced thermal analysis in the procedure.

    Papers V and VI suggest and elaborate on a computational method that utilizes surrogate stress and strain modeling of a solder joint, to quickly evaluate the damage accumulated in a critical solder joint from non-cyclic, non-simplified field operation temperature profiles, with accuracy comparable to finite element modeling. The method has been tested on a ball grid array package with SnAgCu solder joints. This package is included in an extensive set of accelerated tests that helps to qualify certain packages and solder alloys for avionic use. The tests include -20°C to +80°C and -55°C to +125°C thermal cycling of a statistically sound population of a number of selected packages, assembled with SnAgCu, Sn100C, and SnPbAg solder alloys. Statistical analysis of the results confirms that the SnAgCu-alloy may outperform SnPbAg solder at moderate thermal loads on the solder joints.

    In Papers VII and VIII, the timeframe is extended to a future, in which validated life prediction models will be available, and the suggested method is expected to increase the accuracy of embedded prognostics of remaining useful thermal fatigue life of a critical solder joint.

    The key contribution of the thesis is the added value of the proposed computational method utilized in the design phase for electronic equipment. Due to its ability for time-efficient operation on uncompressed temperature data, the method gives contribution to the accuracy, and thereby also to the credibility, of reliability prediction of electronic packages in the design phase. This especially relates to applications where thermal fatigue is a dominant contributor to the damage of solder joints.

    Delarbeten
    1. CFD Analysis of an Avionic Module for Evaluating Power Distribution as a Thermal Management Measure for a Double-sided PCB
    Öppna denna publikation i ny flik eller fönster >>CFD Analysis of an Avionic Module for Evaluating Power Distribution as a Thermal Management Measure for a Double-sided PCB
    2007 (Engelska)Ingår i: Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2007, IEEE , 2007, s. 233-243Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Thermal design aspects of an avionic module including fully populated PCBs housed in a sealed enclosure have been studied by means of computational fluid dynamics. Effect of power distribution between the sides of a double-sided PCB on the case temperature of surface-mounted components has been investigated within a proposed simulation strategy. Simulation-based guidelines have been developed for thermal design of avionic modules, regarding preferable power configuration on a double-sided PCB, representing an alternative approach to thermal management, as compared to introducing additional cooling devices.

    Ort, förlag, år, upplaga, sidor
    IEEE, 2007
    Serie
    Semiconductor Thermal Measurement and Management Symposium, ISSN 1065-2221 ; 2007
    Nyckelord
    Avionics, thermal management, double-sided PCB, CFD, non-dominated designs
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91902 (URN)10.1109/STHERM.2007.352429 (DOI)1-4244-09589-4 (print) (ISBN)1-4244-09589-4 (online) (ISBN)
    Konferens
    23rd Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM 2007), March 18-22, San Jose, CA. USA
    Anmärkning

    At the time for thesis presentation publication was in status: Manuscript

    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2016-12-22Bibliografiskt granskad
    2. An experimental setup for validating a CFD model of a double-sided PCB in a sealed enclosure at various power configurations
    Öppna denna publikation i ny flik eller fönster >>An experimental setup for validating a CFD model of a double-sided PCB in a sealed enclosure at various power configurations
    2005 (Engelska)Ingår i: Proceedings of EuroSime 2005, Berlin: EuroSime , 2005, s. 127-133Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    A flexible experimental setup enabling power control of a fully populated double-sided PCB has been realized, and is described in detail. A CFD model of a double-sided PCB housed in a sealed enclosure has been validated in a 19°C environment by means of temperature and flow measurement. The difference between simulated and measured component temperatures has been within 10%. Potential errors both in the model and in the experiments have been discussed and their impact on temperatures has been numerically evaluated.

    Ort, förlag, år, upplaga, sidor
    Berlin: EuroSime, 2005
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-28747 (URN)10.1109/ESIME.2005.1502787 (DOI)13922 (Lokalt ID)0-7803-9062-8 (ISBN)0-7803-9063-6 (ISBN)13922 (Arkivnummer)13922 (OAI)
    Konferens
    The 6th IEEE EuroSimE conference, April 18-20, Berlin, Germany
    Tillgänglig från: 2009-10-09 Skapad: 2009-10-09 Senast uppdaterad: 2013-11-12Bibliografiskt granskad
    3. Investigating the effect of power distribution on cooling a double-sided PCB: Numerical simulation and experiment
    Öppna denna publikation i ny flik eller fönster >>Investigating the effect of power distribution on cooling a double-sided PCB: Numerical simulation and experiment
    2005 (Engelska)Ingår i: Proceedings of ASME Summer Heat Transfer Conference 2005, San Fransisco: ASME , 2005, s. 649-657Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    An experimental procedure for investigating the effect of power distribution on the cooling of a double-sided PCB is implemented. A number of computational fluid dynamics (CFD) models are validated by laboratory experiments performed in 19.5°C temperature environment. Case temperatures of surface-mounted components fully populating the PCB sides are measured and monitored in simulations. Different combinations of power distribution with other cooling methods, such as a heatsink tooled on a sealed or open enclosure, at natural or forced convection, are studied. Thermally efficient uniform and non-uniform power configurations are determined on a double sided PCB. It is concluded that managing power distribution on a double-sided PCB can be considered as a measure to improve the thermal performance of electronic modules.

    Ort, förlag, år, upplaga, sidor
    San Fransisco: ASME, 2005
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-28748 (URN)10.1115/HT2005-72549 (DOI)13923 (Lokalt ID)0-7918-4734-9 (ISBN)0-7918-3762-9 (ISBN)13923 (Arkivnummer)13923 (OAI)
    Konferens
    ASME 2005 Summer Heat Transfer Conference collocated, with the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems, Heat Transfer: Volume 4, San Francisco, California, USA, July 17–22, 2005
    Tillgänglig från: 2009-10-09 Skapad: 2009-10-09 Senast uppdaterad: 2013-11-12Bibliografiskt granskad
    4. On thermomechanical durability analysis combined with computational fluid dynamics thermal analysis
    Öppna denna publikation i ny flik eller fönster >>On thermomechanical durability analysis combined with computational fluid dynamics thermal analysis
    Visa övriga...
    2007 (Engelska)Ingår i: Proceedings of IMECE2007: ASME International Mechanical Engineering Congress and Exposition, American Society of Mechanical Engineers , 2007, s. 233-240Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Results are presented on durability analysis of an electronic module subjected to thermal and power cycles, and vibration. A hierarchical analysis process for analyzing the durability of the module is described. The initial step is a transient thermal analysis of the unit in which the module is located. The three operating modes of the unit are modeled and analyzed using a commercially available computational fluid dynamics (CFD) tool. The tool generates a time history of the temperature at all points within the unit and module.

    The second step comprises exporting temperatures from the transient temperature analysis to a durability prediction tool. The temperatures calculated by the global analysis are mapped to the printed wiring assembly (PWA) mounted within the box, yielding the temperature distribution of the PWA as functions of time. The durability tool utilizes a modified Coffin Manson formula together with the transient temperature profile to estimate the durability of each lead and solder joint included in the module. Thermomechanical fatigue level of leads and solder joints within the unit are reported as a cumulative damage index (CDI). The CDI is the ratio of the number of cycles required for the test item to endure under a life time to the number of cycles the item is predicted to sustain before failure.

    Durability analysis of solder joint due to vibration is performed separately. The environment is specified according to the location where the unit is mounted. CDI due to vibration is added to form an overall CDI based on Miner’s rule.

    Ort, förlag, år, upplaga, sidor
    American Society of Mechanical Engineers, 2007
    Nyckelord
    Durability analysis, thermal cycling, vibration, transient power dissipation
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91897 (URN)0791842991 (ISBN)
    Konferens
    ASME International Mechanical Engineering Congress and Exposition (IMECE 2007), November 11–15, 2007, Seattle, Washington, USA
    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2013-12-03Bibliografiskt granskad
    5. A computational method for evaluating the damage in a solder joint of an electronic package subjected to thermal loads
    Öppna denna publikation i ny flik eller fönster >>A computational method for evaluating the damage in a solder joint of an electronic package subjected to thermal loads
    (Engelska)Manuskript (preprint) (Övrigt vetenskapligt)
    Abstract [en]

    Purpose – The purpose of this paper is to introduce a novel computational method to evaluate damage accumulation in a solder joint of an electronic package, when exposed to operating temperature environment. A procedure to implement the method is suggested, and a discussion of the method and its possible applications is provided in the paper.

    Originality/value – The method enables increased accuracy in thermal fatigue life prediction of solder joints. Combined with other failure mechanisms, it may contribute to the accuracy of reliability assessment of electronic packages.

    Design/methodology/approach – Methodologically, interpolated response surfaces based on specially designed finite element simulation runs, are employed to compute a damage metric at regular time intervals of an operating temperature profile. The developed method has been evaluated on a finite-element model of a lead-free PBGA256 package, and accumulated creep strain energy density has been chosen as damage metric.

    Findings – The method has proven to be two orders of magnitude more computationally efficient compared to finite element simulation. A general agreement within 3% has been found between the results predicted with the new method, and finite element simulations when tested on a number of temperature profiles from an avionic application. The solder joint temperature ranges between +25°C and +75°C.

    Practical implications – The method can be implemented as part of reliability assessment of electronic packages in the design phase.

    Nyckelord
    Computational method, electronic package, finite element analysis, thermal fatigue, operating temperature environment, lead-free solder
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91898 (URN)
    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2013-05-08Bibliografiskt granskad
    6. Investigation on thermal fatigue of SnAgCu, Sn100C, and SnPbAg solder joints in varying temperature environments
    Öppna denna publikation i ny flik eller fönster >>Investigation on thermal fatigue of SnAgCu, Sn100C, and SnPbAg solder joints in varying temperature environments
    Visa övriga...
    (Engelska)Manuskript (preprint) (Övrigt vetenskapligt)
    Abstract [en]

    Thermal cycling tests have been performed for a range of electronic components intended for avionic applications, assembled with SAC305, SN100C and SnPbAg solder alloys. Two temperature profiles have been used, the first ranging between -20°C to +80°C (TC1), and the second between -55°C and +125°C (TC2). High level of detail is provided for the solder alloy composition and the component package dimensions, and statistical analysis, partially supported by FE modeling, is reported. The test results confirm the feasibility of SAC305 as a replacement for SnPbAg under relatively benign thermomechanical loads. Furthermore, the test results serve as a starting point for estimation of damage accumulation in a critical solder joint in field conditions, with increased accuracy by avoiding data reduction. A computationally efficient method that was earlier introduced by the authors and tested on relatively mild temperature environments has been significantly improved to become applicable on extended temperature range, and it has been applied to a PBGA256 component with SAC305 solder in TC1 conditions. The method, which utilizes interpolated response surfaces generated by finite element modeling, extends the range of techniques that can be employed in the design phase to predict thermal fatigue of solder joints under field temperature conditions.

    Nyckelord
    Thermal cycling tests, lead-free solder, reliability prediction, surrogate modeling
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91899 (URN)
    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2013-05-08Bibliografiskt granskad
    7. Prognostics of Thermal Fatigue Failure of Solder Joints in Avionic Equipment
    Öppna denna publikation i ny flik eller fönster >>Prognostics of Thermal Fatigue Failure of Solder Joints in Avionic Equipment
    2012 (Engelska)Ingår i: IEEE Aerospace and Electronic Systems Magazine, ISSN 0885-8985, E-ISSN 1557-959X, Vol. 27, nr 4, s. 16-24Artikel i tidskrift (Refereegranskat) Published
    Abstract [en]

    A practical method has been suggested for solder joint thermal fatigue prognostics, which enables real-time fatigue calculations based on uncompressed temperature data embedded in a host system that performs safety-critical operations. The accuracy of the prognosticated remaining useful life depends on the level of details captured in the model, and the level of confidence from validation efforts.

    Ort, förlag, år, upplaga, sidor
    IEEE, 2012
    Nyckelord
    Thermal fatigue prognostics, physics-of-failure, electronics, avionics, solder joints.
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91900 (URN)10.1109/MAES.2012.6203714 (DOI)
    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2017-12-06Bibliografiskt granskad
    8. An approach to life consumption monitoring of solder joints in operating temperature environment
    Öppna denna publikation i ny flik eller fönster >>An approach to life consumption monitoring of solder joints in operating temperature environment
    2012 (Engelska)Ingår i: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2012, IEEE , 2012, s. 1-8Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    This paper elaborates the 3T-approach to life consumption monitoring of solder joints in operating temperature environment without requiring simplification of operating loads.

    An overview of the 3T-approach is provided including assumptions made for a proposed realization in an avionic application. Associated implementation routines are highlighted and exemplified for a lead-free PBGA256 package with creep strain energy density (SEDcr) as damage metric.

    Factors that affect the prediction accuracy are investigated. A data resolution has been determined that delivers response surfaces that provide results comparable to 3-D finite-element (FE) simulations, while bearing two orders of magnitude higher computational efficiency.

    A stress-free temperature modification routine is proposed and proves to further mitigate accuracy problems.

    Ort, förlag, år, upplaga, sidor
    IEEE, 2012
    Nyckelord
    Life consumption monitoring, solder joints, avionics, thermal fatigue
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-91901 (URN)10.1109/ESimE.2012.6191699 (DOI)978-1-4673-1512-8 (ISBN)
    Konferens
    13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2012), April 16-18, Cascais, Portugal
    Tillgänglig från: 2013-05-04 Skapad: 2013-05-04 Senast uppdaterad: 2013-05-20Bibliografiskt granskad
    Ladda ner fulltext (pdf)
    Thermal Fatigue Life Prediction of Solder Joints in Avionics by Surrogate Modeling: A Contribution to Physics of Failure in Reliability Prediction
    Ladda ner (pdf)
    omslag
  • 80.
    Arya, Ishan
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System.
    Sundaram, Viswanaath
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System.
    A System Study Of Ultrasonic Transceivers For Haptic Applications2018Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    We are investigating the use of ultrasound in Haptic applications. Initially abrief background of ultrasonic transducers and its characteristics were presented.Then a theoretical research was documented to understand the concepts that govern haptics. This section also discusses the algorithm adopted by various researches to implement haptics in the professional world. Then investigations were made to understand the behavior of ultrasonic transducers and conduct soft-ware simulations to obtain various results. At first simulations were conducted on Field II software. This simulations involved the creation of elements in trans-ducers, transducer’s spatial impulse responses, transducer’s impulse responsein time and frequency domain, effect of adding apodization to the transducers,pulse echo response of the transducers, beam profile variation along the focallength of the transducers. Then a Matlab based GUI was used to study the relationship between number of elements in transducers, the frequency of the input signal and duty cycle variation of the input wave. A concept of phase shift, which explains the time delay generation was also coded in Matlab.

    Ladda ner fulltext (pdf)
    fulltext
  • 81.
    Asghar, Malik Summair
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    A “Divide-by-Odd Number” Injection-Locked Frequency Divider.2013Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

    Ladda ner fulltext (pdf)
    ex-jobb_4653
  • 82.
    Asghar, Rizwan
    et al.
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    Liu, Dake
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
    2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation2009Ingår i: Proceedings of World Academy of Science, Engineering and Technology (ISSN: 2070-3740), 2009, s. 25-29Konferensbidrag (Refereegranskat)
    Abstract [en]

    The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly.  A fully re-configurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.

  • 83.
    Ask, Per
    et al.
    Linköpings universitet, Institutionen för medicinsk teknik, Fysiologisk mätteknik. Linköpings universitet, Tekniska högskolan.
    Öberg, Åke
    Linköpings universitet, Institutionen för medicinsk teknik. Linköpings universitet, Tekniska högskolan.
    Pressure integrating transducer for oesophageal manometry.1979Ingår i: Medical and Biological Engineering and Computing, ISSN 0140-0118, E-ISSN 1741-0444, Vol. 17, nr 3, s. 360-364Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A transducer has been designed that gives an integrated measure of the radial pressure profile at a specific level in the oesophagus. The oesophageal pressure is picked up by a semicylinder elastically connected to a transducer housing by means of a slotted semicylinder. The displacement of the semicylinder is sensed by a semiconductor transducer element. The transducer has a linear relation between static pressure and output voltage, flat frequency characteristic and low temperature drift.

  • 84.
    Ask, Per
    et al.
    Linköpings universitet, Institutionen för medicinsk teknik, Fysiologisk mätteknik. Linköpings universitet, Tekniska högskolan.
    Öberg, Åke
    Linköpings universitet, Institutionen för medicinsk teknik. Linköpings universitet, Tekniska högskolan.
    Tibbling, Lita
    Frequency content of esophageal peristaltic pressure.1979Ingår i: American Journal of Physiology, ISSN 0002-9513, E-ISSN 2163-5773, Vol. 236, nr 3, s. E296-300Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Fourier analysis of esophageal peristaltic pressure waves was performed by computer fast Fourier transform. The highest power spectral density was obtained in the frequency range below 1 Hz. The Fourier analysis showed spectral components up to about 12 Hz in the upper esophageal sphincter (UES). The significance of different frequency components was investigated by low-pass filtering at different cut-off frequencies. A reduction in the amplitude of UES contractions was obtained at a cut-off frequency of 4 Hz, whereas the cut-off frequency of 8 Hz did not show any distortion. For perfused manometry systems, only a low-compliance perfusion pump will have sufficient bandwidth for accurate recording of esophageal peristaltic pressures.

  • 85.
    Aslam, Junaid
    Linköpings universitet, Institutionen för systemteknik.
    Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking2005Självständigt arbete på grundnivå (yrkesexamen)Studentuppsats
    Abstract [en]

    This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 86.
    ASLAM, UMAIR
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    H.264 CODEC Blocks Implementation on FPGA2014Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    H.264/AVC (Advance Video Coding) standard developed by ITU-T Video Coding Experts Group(VCEG) and ISO/IEC JTC1 Moving Picture Experts Group (MPEG), is one of the most powerful andcommonly used format for video compression. It is mostly used in internet streaming sources i.e.from media servers to end users.

    This Master thesis aims at designing a CODEC targeting the Baseline profile on FPGA.Uncompressed raw data is fed into the encoder in units of macroblocks of 16×16 pixels. At thedecoder side the compressed bit stream is taken and the original frame is restored. Emphasis isput on the implementation of CODEC at RTL level and investigate the effect of certain parameterssuch as Quantisation Parameter (QP) on overall compression of the frame rather than investigatingmultiple solutions of a specified block of CODEC.

    Ladda ner fulltext (pdf)
    fulltext
  • 87.
    Athari, Emad
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Lerenius, Petter
    Linköpings universitet, Institutionen för systemteknik.
    Design and implementation of an SDR receiver for the VHF band2007Självständigt arbete på grundnivå (yrkesexamen), 20 poäng / 30 hpStudentuppsats
    Abstract [sv]

    Syftet med det här examensarbetet är att utreda möjligheten att bygga en mjukvarustyrd radiomottagare (SDR) för VHF-bandet. Målet är att göra detta genom att använda så få komponenter som möjligt, och därigenom minska storleken och produktionskostnaden.

    En SDR lösning ger att samplingen kommer att ske så nära antennen som möjligt. Den stora bandbredd som behövs för en sådan produkt uppnås genom att använda SP Devices algoritm för att ''tidsinterleava'' höghastighets ADC:er. Två hårdvaruprototyper och två versioner av mjukvaran har designats och implementerats.

    Analyserna har visat bra resultat, och möjligheterna att bygga en komersiell mjukvarudefinierade radiomottagare för VHF-bandet ses som goda.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 88.
    Azizi, Kaveh
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    FPGA Implementation of a Multimode Transmultiplexer2010Självständigt arbete på avancerad nivå (masterexamen), 30 poäng / 45 hpStudentuppsats (Examensarbete)
    Abstract [en]

    As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA.

    This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA.

    The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 89.
    Azmat, Rehan
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers2012Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance.

    The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture.

    The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

    Ladda ner fulltext (pdf)
    fulltext
  • 90.
    Baaklini, Fredrik
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska fakulteten.
    Bohman, Nicklas
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska fakulteten.
    Design of a high-precision energy meter according to the Measuring Instruments Directive2018Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    This thesis investigates how an energy meter should be constructed in order to apply to the Measurement Instrument Directive. The measuring instrument directive is a statutory industry standard. All meters used for billing purposes must abide by this standard. Multiple systems were investigated in order to find the optimal system according to the agreed upon demands. Each system is presented individually and need to be able to withstand 230V and 35A. The system which fulfills the demands the best is implemented. The choosen system is based around the M90E32AS and Atmega328pb IC:s from Microchip. The sensors used are current transformers and voltage dividers. The M90E32AS samples data from the sensors and forwards it to the Atmega328pb where they can be read by a computer. Communication is conducted via SPI (Serial Peripheral Interface). Isolation is needed to provide protection to low voltage components and other equipment. Because of this the transformers and optocouplers are used. The end result is a functioning energy meter. It measures voltage and current in a satisfying way with a very small margin om error. According to the test made regarding energymetering the measurement error is just above 1%. This is a bigger error than what was wanted but the tests are not very precise and the error is probably smaller in reality.

    Ladda ner fulltext (pdf)
    Design of a high-precision energy meter according to the Measuring Instruments Directive
  • 91.
    Babar, Haji Akbar
    et al.
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Khattak, Atif
    Linköpings universitet, Institutionen för teknik och naturvetenskap, Fysik och elektroteknik. Linköpings universitet, Tekniska högskolan.
    Design of Dual Band Patch Antenna Array2012Självständigt arbete på avancerad nivå (masterexamen), 20 poäng / 30 hpStudentuppsats (Examensarbete)
    Abstract [en]

    Low profile antennas are very useful in applications such as missile, aircraft, cellular applications and satellites, because in these types of applications, some commonly important constraints are cost, size, weight, performance and easy installation. Microstrip patch antenna fits quite comfortably in this category.

    This thesis work aimed to design the dual band microstrip patch antenna arrays operating at frequencies of 3.5 GHz and 5.0 GHz. Two schemes were used to design the antenna array which is the antenna array with same patch size and antenna array with alternating patch size. Different array configuration with 2, 4, 8 and 16 elements were designed and simulated in Agilent Inc EDA tool ADS using Roger RO4350B substrate with a height of 1.524 mm, and transmission-line model was used for the analysis. Array configuration with 2, 4 and 8 elements were fabricated, and results were measured with the help of the network analyzer in the Lab. Distinct antenna parameters were studied such as VSWR, impedance bandwidth, gain, directivity, antenna radiation efficiency, axial ratio and radiation pattern to evaluate the performance of antennas. Focusing on impedance bandwidth it can be claimed that the microstrip patch antenna arrays have better performance as compared to the single microstrip patch antenna designed.

    Ladda ner fulltext (pdf)
    fulltext
  • 92. Beställ onlineKöp publikationen >>
    Backenius, Erik
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    On Reduction of Substrate Noise in Mixed-Signal Circuits2005Licentiatavhandling, monografi (Övrigt vetenskapligt)
    Abstract [en]

    Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.

    In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.

    In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.

    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 93. Beställ onlineKöp publikationen >>
    Backenius, Erik
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Reduction of Substrate Noise in Mixed-Signal Circuits2007Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate.

    Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.

    The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three.

    Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI.

    An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended.

    A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations.

    Delarbeten
    1. A strategy for reducing clock noise in mixed-signal circuits
    Öppna denna publikation i ny flik eller fönster >>A strategy for reducing clock noise in mixed-signal circuits
    2002 (Engelska)Ingår i: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, s. 29-32Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

    Nyckelord
    FIR filters, RC circuits, active filters, clocks, flip-flops, integrated circuit noise, mixed analog-digital integrated circuits
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14442 (URN)0-7803-7523-8 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    2. Design of circuits for a robust clocking scheme
    Öppna denna publikation i ny flik eller fönster >>Design of circuits for a robust clocking scheme
    2004 (Engelska)Ingår i: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, s. 185-188Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

    Nyckelord
    buffer circuits, circuit noise, circuit simulation, clocks, digital integrated circuits, flip-flops, integrated circuit modelling, low-power electronics
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14443 (URN)10.1109/MELCON.2004.1346804 (DOI)0-7803-8271-4 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-05
    3. Evaluation of a clocking strategy with relaxed constraints on clock edges
    Öppna denna publikation i ny flik eller fönster >>Evaluation of a clocking strategy with relaxed constraints on clock edges
    2004 (Engelska)Ingår i: Proc. TENCON'04, 2004, Vol. 4, s. 411-414Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

    Nyckelord
    CMOS logic circuits, FIR filters, clocks, delays, flip-flops
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14444 (URN)10.1109/TENCON.2004.1414957 (DOI)0-7803-8560-8 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-05
    4. Reduction of simultaneous switching noise in digital circuits
    Öppna denna publikation i ny flik eller fönster >>Reduction of simultaneous switching noise in digital circuits
    2006 (Engelska)Ingår i: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, s. 187-190Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

    Nyckelord
    CMOS integrated circuits, buffer circuits, clocks, flip-flops, integrated circuit noise, integrated circuit testing
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14445 (URN)10.1109/NORCHP.2006.329207 (DOI)1-4244-0772-9 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    5. Effect of simultaneous switching noise on an analog filter
    Öppna denna publikation i ny flik eller fönster >>Effect of simultaneous switching noise on an analog filter
    2006 (Engelska)Ingår i: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, s. 898-901Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

    Nyckelord
    clocks, digital filters, integrated circuit noise, mixed analog-digital integrated circuits
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14446 (URN)10.1109/ICECS.2006.379934 (DOI)1-4244-0395-2 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    6. Introduction to substrate noise in SOI CMOS integrated circuits
    Öppna denna publikation i ny flik eller fönster >>Introduction to substrate noise in SOI CMOS integrated circuits
    2005 (Engelska)Ingår i: Proc. National Conf. on Radio Science, RVK'05, 2005Konferensbidrag, Publicerat paper (Övrigt vetenskapligt)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14447 (URN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    7. Programmable reference generator for on-chip measurement
    Öppna denna publikation i ny flik eller fönster >>Programmable reference generator for on-chip measurement
    2006 (Engelska)Ingår i: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, s. 89-92Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

    Nyckelord
    comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    8. Reduction of simultaneous switching noise in analog signal band
    Öppna denna publikation i ny flik eller fönster >>Reduction of simultaneous switching noise in analog signal band
    2007 (Engelska)Ingår i: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, s. 148-151Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

    Nyckelord
    CMOS integrated circuits, adders, flip-flops, frequency-domain analysis, mixed analog-digital integrated circuits, analog signal band, digital clock frequency, frequency components, frequency domain, higher transistor count, pipelined adders, precharged differential cascode switch logic, static CMOS logic, switching noise reduction, transistor level
    Nationell ämneskategori
    Annan elektroteknik och elektronik
    Identifikatorer
    urn:nbn:se:liu:diva-14449 (URN)10.1109/ECCTD.2007.4529558 (DOI)978-1-4244-1341-6 (ISBN)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2009-10-14
    9. Bidirectional Conversion to Minimum Signed-Digit Representation
    Öppna denna publikation i ny flik eller fönster >>Bidirectional Conversion to Minimum Signed-Digit Representation
    2006 (Engelska)Ingår i: Circuits and Systems, 2006. ISCAS 2006., 2006Konferensbidrag, Publicerat paper (Övrigt vetenskapligt)
    Abstract [en]

    In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

    Nyckelord
    Boolean functions, digital arithmetic, bidirectional conversion, signed-digit representation
    Nationell ämneskategori
    Teknik och teknologier
    Identifikatorer
    urn:nbn:se:liu:diva-14450 (URN)10.1109/ISCAS.2006.1693109 (DOI)
    Tillgänglig från: 2007-05-22 Skapad: 2007-05-22 Senast uppdaterad: 2015-03-11
    Ladda ner fulltext (pdf)
    FULLTEXT01
  • 94.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Säll, Erik
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Andersson, Ola
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Programmable reference generator for on-chip measurement2006Ingår i: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, s. 89-92Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

  • 95.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    A digital circuit with relaxed clocking2004Ingår i: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjustable rise and fall times, and an FIR filter that uses the special D flip-flop in the registers. According to measurements, the digital circuit works well when the rise and fall times of the clock is varied from 0.5 ns to 10 ns. This makes the propagation delay in the critical path to vary between 13.0 ns and 13.7 ns, and the energy dissipation to vary between 1.5 pJ and 1.7 pJ, for an input signal with a transition activity of 0.4.

  • 96.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Characteristics of a differential D flip-flop2003Ingår i: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003, Vol. 4Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    A D flip-flop circuit that works well with long rise and fall times of the clock is characterized. This property is important when we would like to, e.g., relax the constraints on the clock distribution network or reduce the amount of noise generated in a mixed-signal circuit. Since the use of the D flip-flop allows small clock driver circuits, the amount of simultaneous switching noise can be reduced. There is also a potential for power savings with the use of smaller drivers, assuming that the short-circuit current in the flip-flops can be kept low. Moreover, the high frequency content of the clock is reduced, causing the noise that is injected into the substrate to be more easy to suppress. This is important in a mixed-signal circuit where analog circuits are present on the same substrate. The effects of long rise and fall times on the differential D flip-flop used in this work are mainly longer propagation times.

  • 97.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Design of circuits for a robust clocking scheme2004Ingår i: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, s. 185-188Konferensbidrag (Refereegranskat)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

  • 98.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Evaluation of a clocking strategy with relaxed constraints on clock edges2004Ingår i: Proc. TENCON'04, 2004, Vol. 4, s. 411-414Konferensbidrag (Refereegranskat)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

  • 99.
    Backenius, Erik
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Introduction to substrate noise in SOI CMOS integrated circuits2005Ingår i: Proc. National Conf. on Radio Science, RVK'05, 2005Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

  • 100.
    Backenius, Erik
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Vesterbacka, Mark
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Pin assignment for low simultaneous switching noise2005Ingår i: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    Simultaneous switching noise (SSN) can degrade the performance of digital circuits. In mixed-signal circuits, the performance of analog circuits are degraded by the SSN that is spread from digital circuits through the substrate to the analog circuits. The most critical parameter when considering SSN is the parasitic inductance in the power supply path from off-chip to on-chip. In this paper, basic theories of inductance of current paths are given for parallel interconnects throughout examples. The results from these examples show that the placement of interconnects plays a big role for the effective inductance. Power supply interconnects should be placed with small distances in between, and so that currents in adjacent interconnects are in opposite directions. With this strategy, a low inductance in the power supply current path can be achieved. The importance of choosing a good package for the silicon die is also briefly discussed.

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