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  • 1.
    Gannedahl, Rikard
    et al.
    Department of Electrical and Information Technology, Lund University, Lund, Sweden.
    Asli, Javad Bagheri
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten. Department of Electrical and Information Technology, Lund University, Lund, Sweden.
    Sjöland, Henrik
    Department of Electrical and Information Technology, Lund University, Lund, Sweden.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity2023Ingår i: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Konferensbidrag (Refereegranskat)
    Abstract [en]

    Sub-THz frequencies are tomorrow’s hot research area in mobile communication. However, in this range of frequencies the systems are complex, and it is hard to explore various system architectures and correlate the system-level solutions with circuit-level performances and requirements. This paper presents a scalable testbench in MATLAB/Simulink for sub-THz hybrid beamforming receivers. The testbench models analog and mixed signal blocks with high fidelity, enabling system level simulations with circuit-level imperfections. A receiver with multiple 4-element subarrays is simulated in the testbench, and the impact of phase noise, beam squint, phase shifter inaccuracies, ADC resolution, and more are investigated. Additionally, a Mueller-Müller symbol synchronizer is implemented to achieve symbol-rate sampling. 

  • 2.
    Asli, Javad Bagheri
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Saberkari, Alireza
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A Parallel-Path Amplifier for Fast Output Settling2023Ingår i: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Konferensbidrag (Refereegranskat)
    Abstract [en]

    Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.

  • 3.
    Sundstrom, Timmy
    et al.
    Saab AB, Sweden.
    Asli, Javad Bagheri
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS2020Ingår i: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings, IEEE , 2020Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

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