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  • 1.
    Nielsen Lönn, Martin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Angelov, Pavel
    Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Self-powered micro-watt level piezoelectric energy harvesting system with wide input voltage range2019Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, nr 3, s. 441-451Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18m CMOS process and the chip measures 3mm(2). Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11V while maintaining an output voltage of 1.8V at an output power of 16.2W. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4.

  • 2.
    Hultman, Martin
    et al.
    Linköpings universitet, Institutionen för medicinsk teknik, Avdelningen för medicinsk teknik. Linköpings universitet, Tekniska fakulteten.
    Fredriksson, Ingemar
    Linköpings universitet, Institutionen för medicinsk teknik, Avdelningen för medicinsk teknik. Linköpings universitet, Tekniska fakulteten. Perimed AB, Järfälla-Stockholm, Sweden.
    Larsson, Marcus
    Linköpings universitet, Institutionen för medicinsk teknik, Avdelningen för medicinsk teknik. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Strömberg, Tomas
    Linköpings universitet, Institutionen för medicinsk teknik, Avdelningen för medicinsk teknik. Linköpings universitet, Tekniska fakulteten.
    A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup2018Ingår i: Journal of Biophotonics, ISSN 1864-063X, E-ISSN 1864-0648, Vol. 11, nr 2, artikel-id e201700069Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A multiple exposure laser speckle contrast imaging (MELSCI) setup for visualizing blood perfusion was developed using a field programmable gate array (FPGA), connected to a 1000 frames per second (fps) 1-megapixel camera sensor. Multiple exposure time images at 1, 2, 4, 8, 16, 32 and 64 milliseconds were calculated by cumulative summation of 64 consecutive snapshot images. The local contrast was calculated for all exposure times using regions of 4 × 4 pixels. Averaging of multiple contrast images from the 64-millisecond acquisition was done to improve the signal-to-noise ratio. The results show that with an effective implementation of the algorithm on an FPGA, contrast images at all exposure times can be calculated in only 28 milliseconds. The algorithm was applied to data recorded during a 5 minutes finger occlusion. Expected contrast changes were found during occlusion and the following hyperemia in the occluded finger, while unprovoked fingers showed constant contrast during the experiment. The developed setup is capable of massive data processing on an FPGA that enables processing of MELSCI data in 15.6 fps (1000/64 milliseconds). It also leads to improved frame rates, enhanced image quality and enables the calculation of improved microcirculatory perfusion estimates compared to single exposure time systems.

  • 3.
    Rusu, C.
    et al.
    RISE Acreo, Sweden.
    Bader, S.
    Mid Sweden Univ, Sweden.
    Oelmann, B.
    Mid Sweden Univ, Sweden.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Enoksson, P.
    Chalmers Univ Technol, Sweden.
    Braun, T.
    Fraunhofer IZM, Germany.
    Tiedke, S.
    AixACCT Syst GmbH, Germany.
    Dal Molin, R.
    Cairdac, France.
    Ferin, G.
    Vermon SA, France.
    Torvinen, P.
    Spinverse Innovat Management Oy, Finland.
    Liljeholm, J.
    Silex Microsyst AB, Sweden.
    Challenges for Miniaturised Energy Harvesting Sensor Systems2018Ingår i: 2018 10TH INTERNATIONAL CONFERENCE ON ADVANCED INFOCOMM TECHNOLOGY (ICAIT), IEEE , 2018, s. 214-217Konferensbidrag (Refereegranskat)
    Abstract [en]

    Harvesting ambient energy, as an alternative power source, tackles the increasing demand for future energy-efficient autonomous sensor systems, especially for applications requiring miniaturisation and distributed sensing such Wireless Sensors Network and Internet-of-Things. A functional energy harvesting system requires addressing simultaneously all the components of the system: the harvester device, the energy storage and the powering management circuits. These components are described through examples of miniaturized kinetic-based harvesting systems for low-power applications with focus on energy harvester, piezoelectric and electromagnetic, respectively.

  • 4.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, nr 1, s. 43-53Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

  • 5.
    Duong, Quoc-Tai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Bhide, Ameya
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Design and analysis of high-speed split-segmented switched-capacitor DACs2017Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, nr 2, s. 199-217Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

  • 6.
    Angelov, Pavel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Nielsen Lönn, Martin
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Ring-oscillator-based timing generator for ultralow-power applications2017Ingår i: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 7.
    Nielsen Lönn, Martin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Angelov, Pavel
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting2017Ingår i: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents three self-oscillating multilevel time-interleaved switched-capacitor DC/DC converters implemented and taped-out in 0:18-mu m CMOS targeting microwatt power levels. Two of the converters are step-up with ratios of 1:2, 1:3, and 1:4, and one is a step-down with ratios of 2:1, 3:1, and 4:1. They all regulate the output voltage towards a targeted reference removing the need for a separate regulator. Aimed for use in vibration energy harvesting systems, the converters have a wide combined input voltage range of 450 mV to 20 V. The low voltage step-up converter operates from an input voltage of 475 mV and has a peak measured power efficiency of 82.2 % with an area of 0.62 mm(2). The medium voltage step-up converter operates from an input voltage of 700 mV and has a peak power efficiency of 74.5 % and an area of 0.53 mm(2). Lastly, the step-down converter works with input voltages up to 20 V and achieves a peak power efficiency of 68.7 % with an area of 0.55 mm(2).

  • 8.
    Harikumar, Prakash
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, nr 8, s. 743-747Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 9.
    Zhang, Dai
    et al.
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, nr 3, s. 244-248Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 10.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Nielsen Lönn, Martin
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS2016Ingår i: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

  • 11.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Capacitive Charge Pump Gain-stage with Source Follower Buffers for Pipelined SAR ADCs2016Ingår i: 2016 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), IEEE , 2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 mu m CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 mu W at a sampling frequency of 10 kHz.

  • 12.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten.
    Harikumar, Prakash
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, nr 1, s. 87-98Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

  • 13.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump2016Ingår i: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, s. 187-190Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

  • 14.
    Unnikrishnan, Vishnu
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    VCO-based ADCs for IoT applications2016Ingår i: 2016 International Symposium on Integrated Circuits (ISIC), IEEE Press, 2016, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    Internet of things (IoT) benefits from fast and low cost development of technology portable re-configurable hardware. Low power consumption is desired for applications operating from harvested or limited energy. Subthreshold operation of VCO-based ADCs is investigated in this work in order to meet these challenges. A ring VCO built using NAND gates is used for reliable operation in the subthreshold region. The impact of supply scaling and PVT variations on the VCO characteristics as well as on the converter performance is studied using transistor level simulations. Some solutions are suggested towards energy efficient operation over a wide range of PVT conditions.

  • 15.
    Bhide, Ameya
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015Ingår i: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, nr 10, s. 2306-2310Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 16.
    Harikumar, Prakash
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications2015Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, s. 13-16Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

  • 17.
    Harikumar, Prakash
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias2015Ingår i: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

  • 18.
    Nielsen Lönn, Martin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Harikumar, Prakash
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems2015Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, s. 308-311Konferensbidrag (Refereegranskat)
    Abstract [en]

    MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

  • 19.
    Bhide, Ameya
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Ojani, Amin
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, nr 7, s. 646-650Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

  • 20.
    Yeknami, Ali Fazli
    et al.
    School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters.2015Ingår i: VLSI-SoC: At the Crossroads of Emerging Trends: 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised Selected Papers / [ed] Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala and Ricardo Reis, Springer-Verlag New York, 2015, s. 94-118Kapitel i bok, del av antologi (Refereegranskat)
    Abstract [en]

    A low-voltage low-power fourth-order active-passive ΔΣ modulator with one active stage is presented. The input-feedforward architecture is adopted, which improves the voltage swing prior to the quantizer. This enables a simpler comparator design and cascade of three passive filters. The passive integrator, as an alternate option to its power-hungry active counterpart, and the non-idealities associated with it are investigated. The active integrator used at the input stage provides most of the loop gain, which suppresses the thermal noise from the succeeding stages and minimizes the non-idealities in the comparator, such as noise and offset. The active integrator employs a two-stage amplifier with load compensation, whose DC-gain is boosted by a partially body-driven technique. The modulator, operated from a 0.7 V supply and clocked with 256 kHz sampling frequency, achieves 84 dB SNR and 80.3 dB SNDR over a 500 Hz signal bandwidth, while it dissipates only 400 nW power.

  • 21.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers2015Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, nr 1, s. 273-282Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

  • 22.
    Chen, Kairang
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Duong, Quoc-Tai
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Power Analysis for Two-Stage High Resolution Pipeline SAR ADC2015Ingår i: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, s. 496-499Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

  • 23.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Low-Power Direct IQ Upconversion Technique Based on Duty-Cycled Multi-Phase Sub-Harmonic Passive Mixers for UWB Transmitters2014Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO frequency, i.e., a sub-harmonic frequency of the carrier. As a result, several benefits can be gained. Requiring a sub-harmonic LO (SHLO) relaxes the requirements on the frequency synthesizer circuitry. Moreover, the need for digital power-hungry or analog inductor-based high frequency LO buffers is alleviated. In addition, since rail-to-rail LO signals can be provided easier and with less power consumption at lower frequencies, we can employ passive mixers in the mixer array to improve the power consumption and linearity of the overall transmitter. Multi-phase LO clocks required by the proposed scheme are provided using a delay-locked loops (DLL). The proposed architecture is utilized in design of a WiMedia-UWB direct-conversion TX in a standard 65-nm CMOS technology. The MC simulation results indicate LO leakage of –68 dBc and sideband rejection of –39 dBc. The overall system draw 6.8 mA from a 1.2 V supply.

  • 24.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Self-Calibration Technique for Fast-Switching Frequency-Hopped UWB Synthesis2014Ingår i: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014,, IEEE , 2014, s. 154-159Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during a start-up phase. During the normal operation when the hopping command arrives, the stored voltages are applied to the loop in an open-loop regime to perform fast channel switching of sub-9.5 ns which is required by WiMedia-UWB standard. Certain architectural and circuit methods are utilized in order to minimize the error in the sampled voltages caused by channel charge injection and clock feedthrough of the sampling switches. Since the proposed fast-switching scheme does not require a wide loop bandwidth, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples resulting in sideband spurs is eliminated. Moreover, the VCDL can be biased in the low-gain region of its transfer function to reduce its noise transfer to the synthesizer output. The proposed architecture is implemented in a 65-nm standard CMOS process and the simulation results indicate a worst-case band switching time of less than 5.5 ns.

  • 25.
    Zhang, Dai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs2014Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, nr 9, s. 666-670Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

  • 26.
    Duong, Quoc-Tai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Dabrowski, Jerzy
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Design and Analysis of High Speed Capacitive Pipeline DACs2014Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, nr 3, s. 359-374Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

  • 27.
    Nielsen Lönn, Martin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska högskolan.
    Design considerations for interface circuits to low-voltage piezoelectric energy harvesters2014Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm2 and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.

  • 28.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Qazi, Fahad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS2014Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, nr 2, s. 358-370Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

  • 29.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers2014Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, nr 11, s. 3075-3084Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

  • 30.
    Bhide, Ameya
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska högskolan.
    Timing challenges in high-speed interleaved ΔΣ DACs2014Ingår i: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, s. 46-49Konferensbidrag (Refereegranskat)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

  • 31.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices2013Ingår i: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, s. 2010-2013Konferensbidrag (Refereegranskat)
    Abstract [en]

    A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

  • 32.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage2013Konferensbidrag (Refereegranskat)
    Abstract [en]

    A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

  • 33.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, nr 1, s. 69-78Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 34.
    Raza Khan, Hashim
    et al.
    NED University of Engn and Technology, Pakistan .
    Fritzin, Jonas
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    ul Wahab, Qamar
    NED University of Engn and Technology, Pakistan .
    A parallel circuit differential class-E power amplifier using series capacitance2013Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 75, nr 1, s. 31-40Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

  • 35.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A quadrature UWB frequency synthesizer with dynamic settling-time calibration2013Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE , 2013, s. 2480-2483Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.

  • 36.
    Svärd, Daniel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Jansson, Christer
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 mu m CMOS2013Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, nr 1, s. 29-44Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper describes a readout integrated circuit architecture for an infrared focal plane array intended for infrared network-attached video cameras in surveillance applications. The focal plane array consists of 352 x 288 uncooled thin-film microbolometer detectors with a pitch of 25 mu m, enabling ambient temperature operation. The circuit features a low-noise readout path, detector resistance mismatch correction and a non-linear ramped current pulse scheme for the electrical biasing of the detectors in order to relax the dynamic range requirement of amplifiers and the ADC in the readout channel, imposed by detector process variation and self-heating during readout. The design is implemented in a 0.35-mu m standard CMOS process and two versions of a smaller 32 x 32-pixel test chip have been fabricated and measured for evaluation. The latest test chip achieves a dynamic range of 97 dB and an input-referred RMS noise voltage of 6.4 mu V yielding an estimated NETD value of 26 mK with f/1 optics. At a frame rate of 60 FPS the chip dissipates 170 mW of power from a 3.4 V supply.

  • 37.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System2013Ingår i: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2013, s. 1918-1921Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

  • 38.
    Bhide, Ameya
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Esmailzadeh Najari, Omid
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, nr 7, s. 387-391Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

  • 39.
    Bhide, Ameya
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators2013Ingår i: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

  • 40.
    Duong, Quoc-Tai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska fakulteten.
    Dabrowski, Jerzy
    Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem. Linköpings universitet, Tekniska fakulteten.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska fakulteten.
    Highly linear open-loop output driver design for high speed capacitive DACs2013Ingår i: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

  • 41.
    Jung, Ylva
    et al.
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska fakulteten.
    Fritzin, Jonas
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Enqvist, Martin
    Linköpings universitet, Institutionen för systemteknik, Reglerteknik. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS2013Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, nr 7, s. 1915-1928Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

  • 42.
    Fazli Yeknami, Ali
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012Ingår i: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, s. 336-339Konferensbidrag (Refereegranskat)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 43.
    Yeknami, Ali Fazli
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 2.1 uW 76 dB SNDR DT-ΔΣ Modulator for Medical Implant Devices2012Ingår i: NORCHIP 2012, IEEE , 2012, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 µW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit.

  • 44.
    Zhang, Dai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2012Ingår i: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, s. 369-372Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 45.
    Zhang, Dai
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Bhide, Ameya
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices2012Ingår i: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, nr 7, s. 1585-1593Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

  • 46.
    Fritzin, Jonas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation2012Ingår i: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Lida Ray Technologies Inc., , 2012, s. 45-48Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

  • 47.
    Fritzin, Jonas
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation2012Konferensbidrag (Refereegranskat)
  • 48.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB2012Ingår i: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), IEEE , 2012, s. 2027-2030Konferensbidrag (Refereegranskat)
    Abstract [en]

    A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

  • 49.
    Ojani, Amin
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Mesgarzadeh, Behzad
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Process Variation Tolerant DLL-Based UWB Frequency Synthesizer2012Ingår i: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE , 2012, s. 558-561Konferensbidrag (Refereegranskat)
    Abstract [en]

    A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.

  • 50.
    Svärd, Daniel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Jansson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A Readout Circuit for an Uncooled IR Camera With Mismatch and Self-Heating Compensation2012Ingår i: NORCHIP 2012, IEEE , 2012, s. 1-4Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper presents a readout integrated circuit for an infrared focal plane array intended to be used in infrared network attached video cameras in surveillance applications. The focal plane array consists of 352×288 uncooled microbolometer detectors with a pitch of 25 µm. The circuit features mismatch correction and a non-linear ramped current pulse scheme for biasing of the detectors, in order to relax the dynamic range requirement of preamplifiers and ADC imposed by detector process variation and self-heating during readout. The integrated circuit is designed in a 0.35 µm standard CMOS process and a smaller 32×32 size test chip has been fabricated for verification. The test chip shows RMS input referred noise of 17 µV at 60 frames/second and dissipates 170 mW of power.

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