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  • 1.
    Hassan Raza Naqvi, Syed
    Linköping University, Department of Electrical Engineering.
    1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology2007Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

    Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

  • 2.
    Hofvendahl, Maria
    Linköping University, Department of Electrical Engineering.
    2.4 GHz Power Amplifier with Cartesian Feedback for WLAN2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This final year project describes the linearisation method Cartesian feedback and the design of such a feedback with a 2.4GHz power amplifier.

    To investigate the functionality of the Cartesian feedback ideal blocks with no current consumption were made and then gradually analog circuits were introduced into the feedback. The Cartesian feedback design consists of a subtracter, a modulator and a preamplifier in the top path and a demodulator and a filter in the feedback path. The blocks that are discussed in this report are the subtracter and the modulator unit. The circuits are designed in a 0.35µm SiGe BiCMOS technology.

    The result of the Cartesian feedback showed an increase in 1dB compression point by 6.2dBm and the IMD was improved by 17dB.

  • 3.
    Sanjuan, Joseba
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    3G Energy-Efficient Packet Handling Kernel Module for Android2012Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    The use of mobile devices is increasing due to the constant development of more advanced and appealing applications and computing features. However, these new features are very power hungry leading to short battery lifetimes. Research shows that a major reason for fast battery depletion is the excessive and inefficient use of the wireless interfaces. This thesis studies how we can attempt to increase the battery lifetime of the devices without having to sacrifice the usage of these advanced features in some applications.

    The thesis focuses on adapting the traffic pattern characteristics of mobile communication using a widespread wireless communication technology like 3G. Traffic pattern adaptation is performed at packet level in kernel space in Android. The data transfers are scheduled with the knowledge of the energy consumption characteristics of 3G. The performed measurements indicate that our solution can provide energy savings ranging from 7% to 59%.

    This work confirms that 3G conscious scheduling of network traffic reduces energy consumption, and that, both applications and energy saving libraries are potential directions to be further studied.

  • 4.
    Sundbom, Per
    et al.
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Cardiology in Linköping.
    Ahn, Henrik
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    Kornhall, B
    Skane University Hospital, Lund.
    Loebe, M
    Division of Transplant and Assist Devices at Methodist DeBakey Heart & Vascular Centre, Houston, Texas, USA.
    Granfeldt, Hans
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    (556) – Change in Acoustic Fingerprints at Increased Pump Speed During Echocardiographic Ramp Test2014Conference paper (Refereed)
    Abstract [en]

    Purpose

    The continuous flow mechanical circulatory support HeartMate II (Thoratec Corporation, Inc. Pleasanton, USA) (HMII), generates an auditory signal (acoustic fingerprint) that can be registered by routine auscultation. A temporary or permanent change in sound indicates a change in pump function. Previous mock loop studies have shown that changes in acoustic fingerprint are due to changes in speed, so the aim of this study was to see if the acoustic fingerprint changed during an echocardiographic ramp test.

    Methods

    Four stable, event-free patients included in the SoundMate study performed an echocardiographic ramp test. The speed was increased stepwise by 400 rpm between 8 000 and 12 000 rpm, and the left ventricular end diastolic diameter, flow, power consumption and blood pressure were measured. Sounds from HMII were recorded using an iPhone™ (Apple Inc. Cupertino, CA, USA) with the stethoscope application iStethPro™ (Dr. Peter J Bentley, UK) and the frequency map analyzed using the Audacity™ program (Unicode, Ash, Chinen and Crook, USA). The acoustic fingerprint is divided into regions (R1: 1 000-6 500, R2: 8 500-14 000, R3: 15 000-21 000 Hz) and peaks (P1: 0-1 000, P2: 6 500-8 500, P4: 21 000-23 000 Hz) in order to facilitate calculations and clarify changes in frequency.

    Results

    There were significant (p<005) changes in the acoustic fingerprint when increasing the pump speed between 8 000 and 12 000 rpm. In 2/4 patients there were no significant changes in P1, otherwise there were significant changes in all regions and peaks. During the ramp test the power increased in mean 7 W, flow 3,1 L/min and the blood pressure measured with Doppler increased by ~15 mmHg. The left ventricular size decreased with ~2 cm.

    Conclusion

    The acoustic fingerprint changes with pump speed. This implies that when using sound check for detection of pump dysfunction, a new baseline should be set after every adjustment of speed.

  • 5.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications2005In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05, 2005, I/127-I/130 p.Conference paper (Refereed)
    Abstract [en]

    The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

  • 6.
    Al Faisal, Muhammad Saud
    Linköping University, Department of Science and Technology. Linköping University, The Institute of Technology.
    6-9 GHz UWB Antenna-Low-Noise Amplifier Co-design2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    6 - 9 GHz antenna-low-noise amplifier co-design is a demanding task. Higher frequency band has new techniques for circuit design and matching. The usual lumped component matching technique is not an appropriate solution for High Frequency (HF) broad band. The new broad band demands transmission line matching. The low-power and high-data rate Ultra Wide Band (UWB) uses large portion of the communication radio-spectrum and wireless communication. The principal axis of this thesis is co-design in the frequency band of 6 - 9 GHz. The thesis has been divided in two parts, where first part includes implementation and evaluation of individual RF-circuits of circular monopole antenna, a band pass (BP) filter and a low-noise amplifier (LNA), while second part unite all three RF circuits and presents the co-design.

    Microstrip monopole antennas get more and more popular due to rapid change in the wireless communication. Higher datarate and even higher bandwidth demands a simple and compact ultra-wideband (UWB) antenna. Two monopole antennas circular and rectangular monopole antennas were designed. Simulated and experimental results of modified design indicate that antenna was achieved a VSWR of 1.2, with input reflection less then - 10 dB in 4 - 12 GHz band. These characteristic make the designed antenna suitable for various UWB application.

     The broad band matching and the flat gain are the two important factors for the UWB circuits. The co-design of antenna-low-noise amplifier utilizes a inter stage matching technique with a simple band pass filter, a third-order passive Chebychev filter is proposed as an input matching network. The filter achieves forward transmission less the - 0.8 dB and a return loss - 20 dB in 6 - 9 GHz band.

    Low-noise amplifier is the key RF circuit; minimal Noise Figure (NF) and the lower power consumption are desired parameters. The implemented low-noise amplifier (LNA) is the combination of bias network and ultra-wide band radio frequency (RF) choke. AVAGO Technologies pseudmorphic-high-electron-mobility transistor (PHEMT) with (SC-70) plastic package with nominal 0.2 µm gate length is used in amplifier. Passive distributed components of microstrip transmission line were used for matching, simulated results demonstrate maximum power gain of 12.74 dB and minimum noise figure (NFmin) of 1 dB is obtained.

    Finally all three individual RF circuits antenna, filter and low-noise amplifier are integrated into co-design and analyzed for 6 - 9 GHz band. Later on two more new designs are added. This co-design has large potential in Direct-broadcast-satellite (DBS) TV system, X-band radar detector, automotive radar, remote sensors, and Multichannel-multipoint-distribution-systems (MMDS). 

  • 7.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 8.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, 336-339 p.Conference paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 9.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, 244-248 p.Article in journal (Refereed)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 10.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-transistor CMOS full adder with full voltage-swing nodes1999In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'99, 1999, 713-722 p.Conference paper (Refereed)
    Abstract [en]

    We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 μm process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder

  • 11.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 12.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier2013Manuscript (preprint) (Other academic)
    Abstract [en]

    An ultra-low-voltage low-power switched-capacitor ΔΣ modulator running at a supply voltage as low as 270 mV is presented for medical implant devices. To reduce the supply voltage and power consumption, an inverter-based amplifier is used in the integrator, whose DC-gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. The entire modulator operates at 270 mV supply only, while the switches are driven by charge pump clock doubler. Designed in 65 nm CMOS and clocked at 256 kHz, the simulation results show that the converter achieves 64.4 dB signal-to-noise-ratio (SNR) and 61 dB signal-to-noise-and-distortionratio (SNDR) in 1 kHz bandwidth while consuming 0.85 "W power.

  • 13.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 86-89 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.   

  • 14.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2012In: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, 369-372 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 15.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2013Conference paper (Other academic)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 16.
    Ahmed, Tanvir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Garrido, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 512-point 8-parallel pipelined feedforward FFT for WPAN2011In: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), IEEE , 2011, 981-984 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm2.

  • 17.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices2011In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland: IEEE Solid-State Circuits Society, 2011, 467-470 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes an ultra-low-power SAR ADC in 0.13-um CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-um CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

  • 18.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 47, no 7, 1585-1593 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

  • 19. Balldin, J
    et al.
    Berglund, M
    Borg, S
    Mansson, M
    Bendtsen, Preben
    Linköping University, Faculty of Health Sciences. Linköping University, Department of Department of Health and Society, Beroendekliniken IHS. Östergötlands Läns Landsting, Local Health Care Services in Central Östergötland, Department of Dependency.
    Franck, J
    Gustafsson, L
    Halldin, J
    Nilsson, LH
    Stolt, G
    Willander, A
    A 6-month controlled naltrexone study: Combined effect with cognitive behavioral therapy in outpatient treatment of alcohol dependence2003In: Alcoholism: Clinical and Experimental Research, ISSN 0145-6008, Vol. 27, no 7, 1142-1149 p.Article in journal (Refereed)
    Abstract [en]

    Background: In several studies, patients with alcohol dependence treated with the opioid antagonist naltrexone have shown fewer relapses to heavy drinking than those receiving placebo. An interaction between the naltrexone effect and the type of psychological therapy has been observed. Methods: A 6-month, double-blind, placebo-controlled, parallel-group study was performed at 10 different investigation sites. After a placebo run-in period of 1 week, 118 patients were randomized into 4 treatment groups - 50 mg of naltrexone daily or placebo in combination with either cognitive behavioral therapy (CBT) or supportive therapy. The CBT was performed over nine sessions according to the manual of Project MATCH (Matching Alcoholism Treatments to Client Heterogeneity). The supportive therapy was defined as "the treatment as usual." Alcohol consumption, craving, carbohydrate-deficient transferrin, medication compliance by tablet count, and adverse clinical events were assessed at all visits. Other liver enzymes and psychiatric symptoms were also determined. Results: Ninety-one (77%) patients completed the study, and 92 (78%) were 80% compliant with the medication regimen. A lower percentage of heavy-drinking days was shown in the naltrexone group (p = 0.045) compared with the placebo group, as was a lower craving score (p = 0.029). These results are supported by the lower levels of liver enzyme activities (p < 0.010 for aspartate aminotransferase, alanine aminotransferase, and ?-glutamyltransferase), but not by the carbohydrate-deficient transferrin levels, in the naltrexone group. The mean time period before the first day of heavy drinking was longer for the group treated with CBT (p = 0.010), especially in combination with naltrexone (p = 0.007). Naltrexone was well tolerated, and no patients discontinued the study due to side effects. Conclusions: This study supports the effect of naltrexone in outpatient treatment of alcohol dependence and suggests that a beneficial interaction effect with CBT can be expected.

  • 20.
    Lindblad, Ulrik
    et al.
    Linköping University, Department of Electrical Engineering.
    Thalin, Patrik
    Linköping University, Department of Electrical Engineering.
    A Behavioral Model of a DSP Processor with Scalable Structure2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    In mobile digital devices, low power consumption is an important matter to reduce the need for a heavy and big battery. One way of reducing the power consumption is to construct the hardware so that the performance is optimal for the application. The demand of performance is dependent of the tasks that the device will be performing. This is where scalable structure of the hardware is an idea to solve the problem.

    This master thesis serve as a starting point for developing a digital signal processor with scalable structure. The digital signal processor is a common and important part of digital processing. Scalable struture is in this case adding and removing parts of the memory and/or the instruction set, and to make the data wordlength variable. The development is simplified by modeling it on an existing processor. The result of this master thesis is an instruction simulator written in C language. The simulator will be a model for development of the hardware.

  • 21.
    Nordgren, Anders
    Linköping University, Department of Culture and Communication, Centre for Applied Ethics. Linköping University, Faculty of Arts and Sciences.
    A climate tax on meat?2012In: Climate change and sustainable development :: ethical perspectives on land use and food production: ethical perspectives on land use and food production / [ed] Thomas Potthast, Simon Meisch, Wageningen: Wageningen Academic Publishers, 2012, 109-114 p.Conference paper (Other academic)
    Abstract [en]

    Climate change is a major framing condition for sustainable development of agriculture and food. Global food production is a major contributor to global greenhouse gas emissions and at the same time it is among the sectors worst affected by climate change. This book brings together a multidisciplinary group of authors exploring the ethical dimensions of climate change and food. Conceptual clarifications provide a necessary basis for putting sustainable development into practice. Adaptation and mitigation demand altering both agricultural and consumption practices. Intensive vs. extensive produc.

  • 22.
    Bengtsson, Mikael
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A clock driver with reduced EMI2014Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A clock driver that works on the principle of charging and discharging the clock network in a VLSI circuit in two steps is investigated in a few different configurations. The aim of the design is twofold:

    • to reduce the power consumption
    • to reduce the third harmonic of the clock signal, and thereby the EMI (electromagnetic interference) emitted by the clock network.

    The first should be possible to accomplish as the clock interconnect network gets charged by half the voltage during each rising transition, and the second should be possible to accomplish by carefully time the rising and falling transitions, so that the third Fourier coefficient of the resulting wave form cancels.

    The drivers are loaded by eight 16-bit adders. The drivers’ power consumption, and the spectrum of the output signal, are investigated under varying clock frequencies, power supply voltage, and driver architecture. The results are compared to a conventional square wave clock.

    The results are that while the third harmonics of the resulting output sees an improvement in all the investigated cases over the square wave clock, the power savings are, for higher clock frequencies, more than completely canceled by the extra power needed in the logic stage which controls these drivers. On the other hand, the power consumption of the new driver appears to drop below that of the conventional driver when the clock frequency drops below approximately 100MHz.

    A few suggestions for further investigations of new designs and clock wave forms are given.

  • 23.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 960- p.Conference paper (Refereed)
    Abstract [en]

    Multi-mode systems are characterised by a set of interacting operational modes to support different functionalities and standards. In this paper, we present a co-design methodology for multi-mode embedded systems that produces energy-efficient implementations. Based on the key observation that operational modes are executed with different probabilities, i.e., the system spends uneven amounts of time in the different modes, we develop a novel codesign technique that exploits this property to significantly reduce energy dissipation. We conduct several experi-ments, including a smart phone real-life example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported.

  • 24.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit2016In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 244, 243-251 p.Article in journal (Refereed)
    Abstract [en]

    A high-speed and compact in-pixel light-to-time converter (LTC), with low power consumption and wide dynamic range is presented. By using the proposed LTC, a digital pixel sensor (DPS) based on a pulse width modulation (PWM) scheme has been designed and fabricated in a standard 180-nm, single-poly, six-metal complementary metal oxide semiconductor (CMOS) technology. The prototype chip consists of a 16 x 16 pixel array with an individual pixel size of 21 x 21 mu m(2) and a fill factor of 39% in the 180-nm CMOS technology. Experimental results show that the circuit operates at supply voltages down to 800 mV and achieves an overall dynamic range of more than 140 dB. The power consumption at 800 mV supply and room light intensity is approximately 2.85 nW. (C) 2016 Elsevier B.V. All rights reserved.

  • 25.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A comparative analysis of logic styles for secure IC´s against DPA attacks2005In: 23rd NORCHIP Conference, Piscataway: IEEE , 2005, , 297-300 p.297-300 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a comparative analysis of logic styles for secure IC's against differential power analysis attacks. We have investigated the correlation between data and instantaneous power consumption in five logic styles including: static CMOS, single-ended domino, differential domino, charge recycling sense amplifier based logic, and dynamic current mode logic. Circuit simulations and statistical analysis show that dynamic current mode logic gives the lowest correlation between power consumption and data, while differential domino combined with a strict clocking scheme shows the best design complexity trade-off.

  • 26.
    Elwing, B
    et al.
    Linköping University, Faculty of Health Sciences. Linköping University, Department of Department of Health and Society, Division of Preventive and Social Medicine and Public Health Science.
    Kullberg, C
    Kucinskiene, Z
    Björegren, M
    Abaravicius, A
    Kristenson, Margareta
    Linköping University, Faculty of Health Sciences. Linköping University, Department of health and environment.
    A comparative study of food intake between Lithuanian and Swedish middle-aged men: The LiVicordia study2001In: Scandinavian Journal of Nutrition/Næringsforskning, ISSN 1102-6480, Vol. 45, no 3, 126-130 p.Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    Background: In 1994, the mortality in coronary heart disease was four times higher among Lithuanian middle-aged men than among Swedish men. Over the period 1993-1995, the LiVicordia study investigated possible causes for this difference. We have earlier reported lower serum levels of cholesterol and higher susceptibility of low-density lipoprotein cholesterol for oxidation among Lithuanian men. Objective: In this part of the study, the aim was to compare mean estimates of food intake. Design: Cross-sectional study of random samples of 50-year-old men from each of the cities of Link÷ping, Sweden and Vilnius, Lithuania (n=150). The volunteers were interviewed about their food intake with the 24-hour recall method. Results: We found no differences in total energy intake, but Vilnius men had a higher energy intake from fat. Vilnius men consumed more fat from meat and less vegetable fat, while fat intake from dairy products was almost the same. Also, Vilnius men had a higher intake of vegetables, while Link÷ping men had a higher intake of fruit and berries. Conclusion: The observed differences in food consumption and dietary composition are partly consistent with the higher CHD mortality among Lithuanian men. However, data on biomarkers indicate that other dietary and lifestyle factors play a role.

  • 27.
    Gustafsson, Fredrik
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    A Comparative Study on Change Detection for some Automotive Applications1997In: Proceedings of the 1997 European Control Conference, 1997Conference paper (Refereed)
    Abstract [en]

    This paper presents a comparison of some different change detection methods for three automotive applications. The applications are tire-road friction estimation, fuel consumption monitoring and navigation using wheel velocities. In simulation studies on real data, measures of performance are given. Experience of real-time implementations in a Volvo is also presented.

  • 28.
    Al-Taie, Mahir Jabbar Rashid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS Technology2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link.

    The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity.

    The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

  • 29.
    Almkvist, Per
    Linköping University, Department of Science and Technology. Linköping University, The Institute of Technology.
    A comparison of two line capacity models for railway traffic2006Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    There are a lot of different factors that affect the capacity on our railways. The infrastructure is one important part but also the timetable and the mixture of trains affect the capacity. The performance on the stations is of course a very important part of the railway system. In this report line capacity models are studied and the purpose of the models is to estimate the capacity on the track between the stations. The models that are studied in the report are the UIC-model and Banverkets model for line capacity. The UIC-model is developed by the European organization with the name UIC and aim to create a more common interpretation of line capacity in central Europe. The model from Banverket is used to give a first indication when seeking problem areas in the railway system. Both models gives a percentage use of the capacity witch is calculated by dividing the time that the track is occupied with the time that is studied. Afterwards the capacity consumption is compared to predefined values that give information about the traffic situation on the line. Also the restore ability is being examined in the report. The measure is based on the delay situation on the specific line.

    The UIC-model is more complex compared to Banverkets model. The UIC-model demand more information that describes the infrastructure and the vehicles. Also the user needs a simulation program to get the necessary information about the reservations of the block sections. The model from Banverket is easier to use but at the same time not as clear as the UIC-model. There is an obvious relation between the models stronger and weaker sides and there purposes.

    The line capacity models and the restore ability are used in a case at the line between Uppsala – Myrbackan (north of Stockholm). Two timetables from the autumn of 2004 and the autumn of 2006 are used in the case. The weekdays that are studied are Tuesday, Wednesday and Thursday. The line is being used the most at the time between 07.00 and 09.00, this is the time that are studied in the case. The results from the case are a bit contradictory. The line capacity models indicated no overload, at the same time the restore ability shows that the mount of delays increases on the line.

  • 30.
    Levi, Richard
    et al.
    Solberga Project/Karolinska Institute and Centre for Neurotraumatology, Karolinska Hospital, Stockholm, Sweden.
    Hultling, C
    Solberga Project/Karolinska Institute and Centre for Neurotraumatology, Karolinska Hospital, Stockholm, Sweden.
    Westgren, N
    Solberga Project/Karolinska Institute and Centre for Neurotraumatology, Karolinska Hospital, Stockholm, Sweden.
    A computer assisted follow up system for spinal cord injury patients.1994In: Paraplegia, ISSN 0031-1758, Vol. 32, no 11, 736-742 p.Article in journal (Refereed)
    Abstract [en]

    The comprehensive care of patients with traumatic spinal cord injuries (SCI) necessitates, among other things, a structured, life-long follow up. The high consumption of medical care in chronic SCI patients, often a result of diseases affecting many different organ systems, soon causes the cumulated medical documentation to be extensive and therefore hard to survey. The possibilities for rational patient management, adequate quality assurance, and clinical research may improve considerably by computerisation of medical records. A computerised medical records system for SCI has recently been developed, using a semistructured medical record format for data input and a medical entity dictionary for facilitated data storage and retrieval. The principles for developing this computer-assisted follow up system are described.

  • 31.
    Hjalmarson, Emil
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A computer-aided approach to design of robust analog circuits2006Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Traditional design methods for analog circuits are based on rules-of-thumbs, experience, and trial-and-error approaches involving the use of circuit simulators. It is an unstructured process, which is time-consuming, error prone, and requires the attention of a skilled analog designer. This situation calls for design methodologies that are more efficient.

    We have developed an efficient approach and corresponding tools that address these issues. A computer-aided design tool for design of large analog circuits with low level of human intervention has been developed. The tool combines efficient performance measure evaluation and optimization methods to determine the device sizes and generate layouts for analog circuits. Large analog circuits with about 200 devices have been designed. The circuits are optimized with respect to, e.g., power consumption, and subject to a large number of performance requirements. All performance measures are automatically derived, which reduces the probability of introducing errors.

    Experimental results indicate that our approach can be used to design robust high-performance analog circuits with improved performance compared to manual approaches. Furthermore, the computer-aided tool decreases both the overall design time and the time required of a skilled designer.

    To accomplish this, an optimization strategy that enables device sizing without an initial design has been developed. Robust circuits are obtained by taking the variations in the manufacturing process into account. Degrading layout effects are also considered using a parasitic feedback technique. To gain insight and allow exploration of the complex relation between performance measures in analog circuits, we have developed techniques for design space exploration.

  • 32.
    Sciarretta, A.
    et al.
    IFP Energies Nouvelles, France .
    Serrao, L.
    Dana Corporation, Italy.
    Dewangan, P.C.
    IFP Energies Nouvelles, France; IFP School, France .
    Tona, P.
    IFP Energies Nouvelles, France .
    Bergshoeff, E.N. D.
    TU Eindhoven, Netherlands.
    Bordons, C.
    University of Seville, Spain .
    Charmpa, L.
    IFP Sch, France Continental, France .
    Elbert, Ph.
    ETH Zurich, Switzerland.
    Eriksson, Lars
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Hofman, T.
    TU Eindhoven, Netherlands .
    Hubacher, M.
    TU Eindhoven, Netherlands .
    Isenegger, R.
    TU Eindhoven, Netherlands .
    Lacandia, F.
    Ohio State University, USA.
    Laveau, A.
    IFP School, France.
    Li, H.
    IFP School, France.
    Marcos, D.
    University of Seville, Spain .
    Nueesch, T.
    ETH Zurich, Switzerland.
    Onori, S.
    Ohio State University, USA .
    Pisu, P.
    Clemson University, USA .
    Rios, J.
    Clemson University, USA .
    Silvas, E.
    TU Eindhoven, Netherlands .
    Sivertsson, Martin
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Tribioli, L.
    Ohio State University, USA .
    van der Hoeven, A.-J.
    TU Eindhoven, Netherlands .
    Wu, M.
    IFP School, France.
    A control benchmark on the energy management of a plug-in hybrid electric vehicle2014In: Control Engineering Practice, ISSN 0967-0661, Vol. 29, 287-298 p.Article in journal (Refereed)
    Abstract [en]

    A benchmark control problem was developed for a special session of the IFAC Workshop on Engine and Powertrain Control, Simulation and Modeling (E-COSM 12), held in Rueil-Malmaison, France, in October 2012. The online energy management of a plug-in hybrid-electric vehicle was to be developed by the benchmark participants. The simulator, provided by the benchmark organizers, implements a model of the GM Voltec powertrain. Each solution was evaluated according to several metrics, comprising of energy and fuel economy on two driving profiles unknown to the participants, acceleration and braking performance, computational performance. The nine solutions received are analyzed in terms of the control technique adopted (heuristic rule-based energy management vs. equivalent consumption minimization strategies, ECMS), battery discharge strategy (charge depleting-charge sustaining vs. blended mode), ECMS implementation (vector-based vs. map-based), ways to improve the implementation and improve the computational performance. The solution having achieved the best combined score is compared with a global optimal solution calculated offline using the Pontryagins minimum principle-derived optimization tool HOT.

  • 33.
    Feiz, Roozbeh
    et al.
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Fenton, Paul
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Frändegård, Per
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Johansson, Nils
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Kanda, Wisdom
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Matschewsky, Johannes
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Mejía Dugand, Santiago
    Päivärinne, Sofia
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Wallsten, Björn
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    A corridor striving for sustainability - Reflecting upon PhD education at a Swedish University2015Conference paper (Other academic)
    Abstract [en]

    In this paper, we present an overview of interdisciplinary research from Ph.D. students working at the Division of Environmental Technology and Management at Linköping University, Sweden. Each of the Ph.D. students addresses the overall challenge of sustainability transitions in their research, although the themes and content of research varies considerably between individuals, encompassing research on actors, networks, products, materials, services and systems from the public and private sector, operating locally, regionally, nationally and internationally. The scientific literature and methods used to frame and conduct studies varies considerably within the group, as does the individual focus on immediate issues of sustainability.

  • 34.
    Dragioti, Elena
    et al.
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Medicine and Health Sciences.
    Larsson, Britt
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Medicine and Health Sciences. Region Östergötland, Anaesthetics, Operations and Specialty Surgery Center, Pain and Rehabilitation Center.
    Bernfort, Lars
    Linköping University, Department of Medical and Health Sciences, Division of Health Care Analysis. Linköping University, Faculty of Medicine and Health Sciences.
    Levin, Lars-Åke
    Linköping University, Department of Medical and Health Sciences, Division of Health Care Analysis. Linköping University, Faculty of Medicine and Health Sciences.
    Gerdle, Björn
    Linköping University, Department of Medical and Health Sciences, Division of Community Medicine. Linköping University, Faculty of Medicine and Health Sciences. Region Östergötland, Anaesthetics, Operations and Specialty Surgery Center, Pain and Rehabilitation Center.
    A cross-sectional study of factors associated with the number of anatomical pain sites in an actual elderly general population: results from the PainS65+cohort2017In: Journal of Pain Research, ISSN 1178-7090, E-ISSN 1178-7090, Vol. 10, 2009-2019 p.Article in journal (Refereed)
    Abstract [en]

    Background: Several studies have illustrated that multisite pain is more frequent than single pain site, and it is associated with an array of negative consequences. However, there is limited knowledge available about the potential factors associated with multisite pain in the elderly general population. Objective: This cross-sectional study examines whether the number of anatomical pain sites (APSs) is related to sociodemographic and health-related factors in older adults including oldestold ages using a new method (APSs) to assess the location of pain on the body. Materials and methods: The sample came from the PainS65+ cohort, which included 6,611 older individuals (mean age = 76.0 years; standard deviation [SD] = 7.4) residing in southeastern Sweden. All the participants completed and returned a postal survey that measured sociodemographic data, total annual income, pain intensity and frequency, general well-being, and quality of life. The number of pain sites (NPS) was marked on a body manikin of 45 sections, and a total of 23 APSs were then calculated. Univariable and multivariable models of regression analysis were performed. Results: Approximately 39% of the respondents had at least two painful sites. The results of the regression analysis showed an independent association between the APSs and the age group of 75-79 years, women, married, high pain intensity and frequency, and low well-being and quality of life, after adjustments for consumption of analgesics and comorbidities. The strongest association was observed for the higher frequency of pain. Conclusion: Our results suggest that APSs are highly prevalent with strong relationships with various sociodemographic and health-related factors and concur well with the notion that multisite pain is a potential indicator of increased pain severity and impaired quality of life in the elderly. Our comprehensive method of calculating the number of sites could be an essential part of the clinical presentation, assessment, and treatment of multisite pain.

  • 35.
    Öberg, Per
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    A DAE Formulation for Multi-Zone Thermodynamic Models and its Application to CVCP Engines2009Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    In the automotive area there are ever increasing demands from legislators and customers on low emissions and good fuel economy. In the process of developing and investigating new technologies, that can meet these demands, modeling and simulation have become important as standard engineering tools. To improve the modeling process new concepts and tools are also being developed.

    A formulation of a differential algebraic equation (DAE) that can be used for simulation of multi-zone in-cylinder models is extended and analyzed. Special emphasis is placed on the separation between thermodynamic state equations and the thermodynamic properties. This enables implementations with easy reuse of model components and analysis of simulation results in a structured manner which gives the possibility to use the formulation in a large number of applications. The introduction and depletion of zones are handled and it is shown that the DAE formulation has a unique solution as long as the gas model fulfills a number of basic criteria. Further, an example setup is used to validate that energy, mass, and volume are preserved when using the formulation in computer simulations. In other words, the numerical solution obeys the thermodynamic state equation and the first law of thermodynamics, and the results are consistent and converge as tolerances are tightened. As example applications, the DAE formulation is used to simulate spark ignited SI and Diesel engines as well as simple control volumes and 1-dimensional pipes. It is thus shown that the DAE formulation is able to adapt to the different requirements of the SI and Diesel engine models.

    An interesting application is the SI engine with continuously variable cam phasing (CVCP), which is a technology that reduces the fuel consumption. It influences the amount of air and residual gases in the engine in a non trivial manner and this SI application is used to evaluate three control oriented models for cylinder air charge and residual mass fraction for a CVCP-engine both for static and transient conditions. The models are: a simple generalized flow restriction model created with physical insight and two variants of a model that is based on an energy balance at intake valve closing (IVC). The two latter models require measurement of cylinder pressure and one also requires an air mass flow measurement. Using the SI model as reference it is shown that transients in cam positions have a large impact on air charge and residual mass fraction, and the ability of the models to capture these effects is evaluated. The main advantages of the generalized flow restriction model are that it is simple and does not require measurement of the cylinder pressure but it is also the model with the largest errors for static operating points and highest sensitivity in transients. The two models that use an energy balance at IVC both handle the transient cycles well. They are, however, sensitive to the temperature at IVC. For static cycles it is therefore advantageous to use the model with air mass flow measurement since it is less sensitive to input data. During transients however, if the external measurement is delayed, it is better to use the model that does not require the air mass flow.

    The conclusion is that the DAE formulation is a flexible, robust, tool, and that it is well suited for multi-zone in-cylinder models as well as models for manifolds and pipes outside the cylinder.

    List of papers
    1. Control Oriented Modeling of the Gas Exchange Process in Variable Cam Timing Engines
    Open this publication in new window or tab >>Control Oriented Modeling of the Gas Exchange Process in Variable Cam Timing Engines
    2006 (English)In: SAE Technical Paper 2006-01-0660, SAE , 2006Conference paper, Published paper (Refereed)
    Abstract [en]

    Variable cam timing engines pose new questions for engine control system designers. The cam timing directly influences cylinder air charge and residual mass fraction. Three models that predict residual mass fraction are investigated for a turbocharged dual independent Variable Cam Timing (VCT) engine. The three models (Fox et. al. 1993, Ponti et. al. 2002, and Mladek et. al. 2000) that all have real time capabilities are evaluated and validated against data from a crank angle based reference model. None of these models have previously been validated to cover this engine type. It is shown that all three models can be extended to dual independent VCT engines and that they also give a good description of the residual gas fraction. However, it is shown that the two most advanced models, based on a thermodynamic energy balance, are very sensitive to the model inputs and proper care must therefore be taken when these models are used

    Place, publisher, year, edition, pages
    SAE, 2006
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18306 (URN)
    Available from: 2009-05-18 Created: 2009-05-18 Last updated: 2009-10-14Bibliographically approved
    2. Control Oriented Gas Exchange Models for CVCP Engines and their Transient Sensitivity
    Open this publication in new window or tab >>Control Oriented Gas Exchange Models for CVCP Engines and their Transient Sensitivity
    2007 (English)In: Oil & gas science and technology, ISSN 1294-4475, Vol. 62, no 4, 573-584 p.Article in journal (Refereed) Published
    Abstract [en]

    The paper analyzes a set of control oriented models for the gas exchange phase in engines with continuously variable cam phasing (CVCP). These models describe the mass flow of fresh gases and the residual gases caught in the cylinder during the gas exchange phase. Simulations with CVCP transients are also performed to analyze the models performance during transients.

    Place, publisher, year, edition, pages
    IFP, 2007
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18307 (URN)10.2516/ogst:2007041 (DOI)
    Available from: 2009-05-18 Created: 2009-05-18 Last updated: 2009-05-18Bibliographically approved
  • 36.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 37.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB2012In: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), IEEE , 2012, 2027-2030 p.Conference paper (Refereed)
    Abstract [en]

    A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

  • 38.
    Korishe, Abdulah
    Linköping University, Department of Electrical Engineering, Electronics System.
    A Driver Circuit for Body-Coupled Communication2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The main concept of Body-Coupled Communication (BCC) is to transmit the electrical information through the human body as a communication medium by means of capacitive coupling. Nowadays the current research of wireless body area network are expanding more with the new ideas and topologies for better result in respect to the low power and area, security, reliability and sensitivity since it is first introduced by the Zimmerman in 1995. In contrast with the other existing wireless communication technology such as WiFi, Bluetooth and Zigbee, the BCC is going to increase the number of applications as well as solves the problem with the cell based communication system depending upon the frequency allocation. In addition, this promising technology has been standardized by a task group named IEEE 802.15.6 addressing a reliable and feasible system for low power in-body and on-body nodes that serves a variety of medical and non medical applications.

    The entire BAN project is divided into three major parts consisting of application layer, digital baseband and analog front end (AFE) transceiver. In the thesis work a strong driver circuit for BCC is implemented as an analog front end transmitter (Tx). The primary purpose of the study is to transmit a strong signal as the signal is attenuated by the body around 60 dB. The Driver circuit is cascaded of two single-stage inverter and an identical inverter with drain resistor. The entire driver circuit is designed with ST65 nm CMOS technology with 1.2 V supply operated at 10 MHz frequency, has a driving capability of 6 mA which is the basic requirement. The performance of the transmitter is compared with the other architecture by integrating different analysis such as corner analysis, noise analysis and eye diagram. The cycle to cycle jitter is 0.87% which is well below to the maximum point and the power supply rejection ratio (PSRR) is 65 dB indicates the good emission of supply noise. In addition, the transmitter does not require a filter to emit the noise because the body acts like a low pass filter.

    In conclusion the findings of the thesis work is quite healthy compared to the previous work. Finally, there is some point to improve for the driver circuit in respect to the power consumption, propagation delay and leakage power in the future.   

  • 39.
    Palmkvist, Kent
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Nordhamn, Erik
    n/a.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A fast bit-serial lattice wave digital filter1992In: Proc. NUTEK Workshop on Digital Communications, 1992, 88-92 p.Conference paper (Other academic)
    Abstract [en]

    In this paper we discuss the implementation of maximally fast fixed-function digital filters. We demonstrate by means of an example that digital filters with sampling frequencies of more than hundred MHz can efficiently be implemented by using bit-serial PEs. The proposed approach lead to maximally fast filters that require little chip area and have low power consumption. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying equivalence transformations to the signal-flow graph.

  • 40.
    Bauer, Joanna
    et al.
    University of Bergen.
    Haugland, Dag
    University of Bergen.
    Yuan, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Science and Technology, Communications and Transport Systems.
    A fast local search method for minimum energy broadcast in wireless ad hoc networks2009In: OPERATIONS RESEARCH LETTERS, ISSN 0167-6377, Vol. 37, no 2, 75-79 p.Article in journal (Refereed)
    Abstract [en]

    Local search methods are often used to reduce the power consumption of broadcast routing in wireless networks. For a classic method, sweep, the best available time complexity result is O(vertical bar V vertical bar(4)). We present an O(vertical bar V vertical bar(2))-time method, which exhaustively removes unnecessary transmissions yielding a solution comparable to that of sweep.

  • 41.
    Kanda, Wisdom
    et al.
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Gonzaléz, Pablo del Rio
    Institute for Public Policies and Goods Madrid, Spain..
    Hjelm, Olof
    Linköping University, Department of Management and Engineering, Environmental Technology and Management. Linköping University, Faculty of Science & Engineering.
    Bienkowska, Dzamila
    Linköping University, Department of Management and Engineering, Project Innovations and Entrepreneurship. Linköping University, Faculty of Science & Engineering.
    A function of innovation systems approach for analysing the roles of intermediaries in eco-innovation2015Conference paper (Other academic)
    Abstract [en]

    This article draws from two bodies of literature, innovation intermediaries and technological innovation systems, to develop an approach for analysing the functions of intermediaries in eco-innovation. The link between the functions of innovation intermediaries and the functions of technological innovation systems has seldom been explicitly established in the scientific discourse and thus this article contributes to theoretical development in both literatures. To the technological innovation systems literature, this article addresses the lack of attention to the functions of innovation intermediaries who are a critical part in the formation of networks and also contribute to a number of innovation system functions. To the innovation intermediary literature, the functional approach advocates for a synthesis and consensus building in the literature regarding intermediary functions in view of the several redundancies and ambiguities on the subject matter. Empirical operationalization of the analytical approach including methodological choices from case studies in Region Scania, Sweden and North Rhine Westphalia, Germany are also discussed. The results of our analysis show that the functions of the innovation intermediaries are particularly relevant for the overall goals of an innovation system as compared to the configuration of intermediary actors. Particular challenges with a functional approach in this context include the difficulties of establishing a causal relation between the support functions of intermediaries and eco-innovation outcomes in firms.

  • 42.
    Östberg, AL
    et al.
    Public Dental Services and Skaraborg Institute, Skövde.
    Halling, Arne
    Östergötlands Läns Landsting, Public Dental Service.
    Lindblad, U
    Public Dental Services and Skaraborg Institute, Skövde.
    A gender perspective of self-perceived oral health in adolescents: associations with attitudes and behaviours2001In: Community Dental Health, ISSN 0265-539X, Vol. 18, no 2, 110-116 p.Article in journal (Refereed)
    Abstract [en]

    Objective To investigate the associations between dental attitudes and behaviours, and self-perceived oral health from a gender perspective in an adolescent population. Design A census survey. Self-reported questionnaires were answered anonymously in a standardised manner in classrooms. Attitudes studied included the importance of sound teeth and feelings towards visits to the dentist. Behaviours were represented by floss usage and sweets consumption. Setting All senior and upper secondary level schools in Skaraborg County, Sweden. Subjects 17,280 students, aged 13-18 years, Outcome measures Self-perceived oral health. represented by a single-item rating: satisfaction with the appearance of the teeth: self-assessed gum bleeding and a perceived oral health (POH) index. Results Recognising sound teeth as important was a predominating attitude among the respondents (boys 94%, girls 97%) and was significantly associated with a good perceived oral health overall. Individuals who experienced visits to dentist as unpleasant (boys 36%, girls 43%) were less likely to perceive good oral health as single-item rated (OR for boys 0.55[0.49, 0.63], girls 0.40[0.34, 0.47]). Regular use of floss had a small protective effect on bleeding gums. Daily sweets consumption showed a significant and inverse association with self-perceived oral health as single-item rated (OR for boys 0.53[0.44, 0.66], girls 0.49[0.40, 0.60]). Girls, more often than boys, perceived their oral health to be good, except in the perception of the appearance of their teeth. Conclusions It is concluded that the strong associations between attitudes and self-perceived oral health should be recognised in strategies for oral health promotion and that gender differences must be considered.

  • 43.
    Liu, Dake
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Hardware Architecture for a Multi Mode Block Interleaver2004In: International Conference on Circuits and Systems for Communications, ICCSC,2004, 2004Conference paper (Refereed)
    Abstract [en]

    We are interested in developing a programmable baseband processor for software defined radio and are trying to find configurable hardware blocks that can be used in multiple radio standards, including for example wireless LAN and 3G standards. This paper suggests an architecture for a multi mode block interleaver that is suitable e.g. for the IEEE 802.11a and 802.11g standards. Our implementation is based on a special matrix memory to which data is written as rows but read out as columns. To enable a comparison, an interleaver for theWireless LAN standard 802.11a has been implemented both using our suggested architecture and using a traditional interleaver implementation based on a bit memory. Our implementation reaches a significantly higher performance and a lower power consumption with no extra area. The price to pay is a small loss of generality.

  • 44.
    Ma, YT
    et al.
    Royal Inst Technol, Dept Elect, Stockholm, Sweden Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A hardware efficient control of memory addressing for high-performance FFT processors2000In: IEEE Transactions on Signal Processing, ISSN 1053-587X, Vol. 48, no 3, 917-921 p.Other (Other academic)
    Abstract [en]

    The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen's scheme, Compared Kith this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed, Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a nem ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.

  • 45.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Dehghani, Rasoul
    Isfahan University of Technology, Iran.
    Jalili, Armin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor2015In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 236, 82-91 p.Article in journal (Refereed)
    Abstract [en]

    This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 x 16 DPS with pixel size of 23 x 23 mu m(2) and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. (C) 2015 Elsevier B.V. All rights reserved.

  • 46.
    Gustavsson, Mikael
    et al.
    SP Devices AB.
    Ul Amin, Farooq
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Bjorklid, Anders
    SP Devices AB.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Xu, Cheng
    Royal Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography2012In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 59, no 1, 30-39 p.Article in journal (Refereed)
    Abstract [en]

    We describe a high-rate energy-resolving photon-counting ASIC aimed for spectral computed tomography. The chip has 160 channels and 8 energy bins per channel. It demonstrates a noise level of ENC= electrons at 5 pF input load at a power consumption of andlt;5mW/channel. Maximum count rate is 17 Mcps at a peak time of 40 ns, made possible through a new filter reset scheme, and maximum read-out frame rate is 37 kframe/s.

  • 47. Landernäs, Krister
    et al.
    Holmberg, Johnny
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A high-speed low-latency digit-serial hybrid adder2004In: IEEE Int. Symp. on Circuits and Systems, ISCAS'04, 2004, III-217-III-220 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area, and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the others studied in this paper for digit-sizes up to d=12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and a 21% smaller critical path that the digit-serial Ladner-Fisher adder.

  • 48.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Low Clock Load Conditional Flip-Flop2004In: Proceedings of IEEE International System-on-Chip Conference, Santa Clara, California, USA, September 2004, 2004, 169-170 p.Conference paper (Other academic)
    Abstract [en]

    We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.

  • 49.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Ohlsson, Henrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Low Power Decimation Filter Architecture for High-Speed Single-Bit Sigma-Delta Modulation2005In: IEEE International Symposium on Circuits and Systems,2005, Piscataway, NJ: IEEE , 2005, 1453- p.Conference paper (Refereed)
    Abstract [en]

    In this work a novel architecture suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation is proposed. By using efficient data and coefficient representation the total number of partial products is reduced leading to low power consumption. The work is focused on filters designed based on cascaded comb filters, although the approach is applicable to any FIR filter.

  • 50.
    Edman, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Christensen, J
    Emrich, A.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 36, 258-265 p.Article in journal (Refereed)
    Abstract [en]

    The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

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