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  • 1.
    Hassan Raza Naqvi, Syed
    Linköping University, Department of Electrical Engineering.
    1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology2007Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

    Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

  • 2.
    Chen, J.
    et al.
    Ericsson Research.
    Ze, H.
    Chalmers University of Technology.
    Bao, L.
    Ericsson Research.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Li, Y.
    Ericsson Research.
    Gunnarsson, S.
    SiversIMA AB.
    Stoij, C.
    SiversIMA AB.
    Zirath, H.
    Chalmers University of Technology.
    10 Gbps 16QAM Transmission over a 70/80 GHz (E-band) Radio Test-bed2012In: 2012 7th European Microwave Integrated Circuit Conference, IEEE , 2012, 556-559 p.Conference paper (Refereed)
    Abstract [en]

    A millimeter-wave radio test-bed is implemented which demonstrates 16QAM transmission over 70/80 GHz band for data rate up to 10 Gbps. Performance of the 16QAM transmitter and receiver is evaluated in a loop-back lab set-up. With the proposed 10 Gbps on single carrier system architecture, it is possible to achieve 40 Gbps over a 5 GHz bandwidth when combined with polarization and spatial multiplexing.

  • 3.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    10 GHz wideband low-noise amplifier using a 0,35um SiGe BiCMOS technology.2002In: SSoCC´02 confernce,2002, 2002Conference paper (Refereed)
  • 4.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    11th Swedish System-on-Chip Conference Sponsored by SSCS-Sweden in May2011Other (Other (popular science, discussion, etc.))
  • 5.
    Ni, Wei-Xin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Surface and Semiconductor Physics .
    Du, Chun-Xia
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology.
    Duteil, F.
    Elfving, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Surface and Semiconductor Physics .
    Hansson, Göran
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Surface and Semiconductor Physics .
    1.54 µm light emitting devices based on Er/O-doped Si layered structures grown by molecular beam epitaxy2001In: Optical materials (Amsterdam), ISSN 0925-3467, E-ISSN 1873-1252, Vol. 17, no 1-2, 65-69 p.Conference paper (Other academic)
    Abstract [en]

    Two types of Si:Er light emitting devices have been processed and characterized with an aim to efficiently use hot electrons for impact excitation. One is a p+-SiGe/i-Si/n-Si:Er:O/n+-Si tunneling diode with a design favoring electron tunneling from the SiGe valence band to the Si conduction band and subsequent acceleration. Another type of Si:Er light emitters is based on a heterojunction bipolar transistor (HBT) structure containing an Er-doped active layer in the collector. In these devices, one can introduce hot electrons from the HBT emitter in a controlled way with a collector bias voltage prior to the avalanche breakdown to improve the impact excitation efficiency. Intense electroluminescence was observed at 300 K at low current (0.1 A cm-2) and low bias (3 V). An impact cross-section value of 1 × 10-14 cm2 has been estimated, which is a 100-fold increase compared with the values reported from any other type of Er-doped LEDs. © 2001 Elsevier Science B.V.

  • 6.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    1.56 HGz On-chip Resonant Clocking in 130nm CMOS.2006In: IEEE Custom Integrated Circuits Conference CICC,2006, Piscataway: IEEE , 2006, 241- p.Conference paper (Refereed)
  • 7.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS2006In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

  • 8.
    Bengtsson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    2 Gb/s decision feedback equalizer in 3.3 V 0.35 µm CMOS2004In: Circuits, Signals, and Systems (CSS 2004) / [ed] M.H. Rashid, 2004Conference paper (Refereed)
    Abstract [en]

    A 2 Gb/s decision feedback equalizer is implemented in a 0.35 m CMOS process and experimentally demonstrated. Speed is enhanced through optimization of the unavoidable loop in a decision feedback equalizer, parallelism, differential current mode frontend, fast sense amplifier style comparators and single-phase flip-flops.

  • 9.
    Hofvendahl, Maria
    Linköping University, Department of Electrical Engineering.
    2.4 GHz Power Amplifier with Cartesian Feedback for WLAN2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This final year project describes the linearisation method Cartesian feedback and the design of such a feedback with a 2.4GHz power amplifier.

    To investigate the functionality of the Cartesian feedback ideal blocks with no current consumption were made and then gradually analog circuits were introduced into the feedback. The Cartesian feedback design consists of a subtracter, a modulator and a preamplifier in the top path and a demodulator and a filter in the feedback path. The blocks that are discussed in this report are the subtracter and the modulator unit. The circuits are designed in a 0.35µm SiGe BiCMOS technology.

    The result of the Cartesian feedback showed an increase in 1dB compression point by 6.2dBm and the IMD was improved by 17dB.

  • 10.
    Seppänen, Timo
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, The Institute of Technology.
    Hultman, Lars
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, The Institute of Technology.
    Birch, Jens
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics.
    248 nm cathodoluminescence in Al1-xInxN (0001) thin films grown on lattice-matched Ti1-yZryN (111) seed layers by low temperature magnetron sputter epitaxy2006In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 89, no 18Article in journal (Refereed)
    Abstract [en]

    Single-crystal Al0.8 In0.2 N (0001) thin films were grown epitaxially onto lattice-matched Ti0.2 Zr0.8 N (111) seed layers on MgO(111) substrates at 300 °C by magnetron sputter epitaxy. Low-energy ion-assisted epitaxial growth conditions were achieved by applying a substrate potential of -15 V. Cross-sectional high-resolution electron microscopy verified the epitaxy and high-resolution x-ray diffraction ω -rocking scans of the Al0.8 In0.2 N 0002 peak (full width at half maximum ∼2400 arc sec) indicated a high structural quality of the films. Cathodoluminescence measurements performed in a scanning electron microscope at 5 K revealed Al0.8 In0.2 N luminescence at 248 nm, or equivalently 5.0 eV, showing that Al0.8 In0.2 N is a promising material for deep-ultraviolet optoelectronic devices. © 2006 American Institute of Physics.

  • 11.
    Bengtson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    2.5 Gb/s, 72 dBΩ transimpedance amplifier in 0.35 μm CMOS2004Conference paper (Other academic)
    Abstract [en]

    A differential transimpedance amplifier in a 3.3 V 0.35 μm CMOS process with an fT of 17 GHz is presented. Measurements demonstrate a transimpedance gain of 72 dBΩ and 1.4 GHz bandwidth. Eye diagrams at a data rate of 2.5 Gb/s show a dynamic range of more than 60 dB. The performance is reached with a three-stage transimpedance amplifier, utilizing differential high-speed stages and carefully chosen peaking frequencies.

  • 12.
    Bengtsson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    2.5 Gb/s equalizer for opticla communication.2002In: Swedish System-on-Chip,2002, 2002Conference paper (Other academic)
  • 13.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    2.6 Gb/s Over a Four-Drop Bus Using an Adaptive 12-Tap DFE2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 470-473 p.Conference paper (Refereed)
    Abstract [en]

    For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.  

  • 14.
    Szymanski, Marek
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Surface Physics and Chemistry. Linköping University, Faculty of Science & Engineering.
    Tu, Deyu
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Forchheimer, Robert
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    2-D Drift-Diffusion Simulation of Organic Electrochemical Transistors2017In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 12, 5114-5120 p.Article in journal (Refereed)
    Abstract [en]

    A 2-D device model of the organic electrochemical transistor is described and validated. Devices with channel length in range 100 nm-10 mm and channel thickness in range 50 nm-5 mu m are modeled. Steady-state, transient, and AC simulations are presented. Using the realistic values of physical parameters, the results are in good agreement with the experiments. The scaling of transconductance, bulk capacitance, and transient responses with device dimensions is well reproduced. The model reveals the important role of the electrical double layers in the channel, and the limitations of device scaling.

  • 15.
    Patra, Santanu
    et al.
    Indian School Mines, India.
    Roy, Ekta
    Indian School Mines, India.
    Tiwari, Ashutosh
    Linköping University, Faculty of Science & Engineering. Linköping University, Department of Physics, Chemistry and Biology, Biosensors and Bioelectronics.
    Madhuri, Rashmi
    Indian School Mines, India.
    Sharma, Prashant K.
    Indian School Mines, India.
    2-Dimensional graphene as a route for emergence of additional dimension nanomaterials2017In: Biosensors & bioelectronics, ISSN 0956-5663, E-ISSN 1873-4235, Vol. 89Article in journal (Refereed)
    Abstract [en]

    Dimension has a different and impactful significance in the field of innovation, research and technologies. Starting from one-dimension, now, we all are moving towards 3-D visuals and try to do the things in this dimension. However, we still have some very innovative and widely applicable nanomaterials, which have tremendous potential in the form of 2-D only i.e. graphene. In this review, we have tried to incorporate the reported pathways used so far for modification of 2-D graphene sheets to make is three-dimensional. The modified graphene been applied in many fields like supercapacitors, sensors, catalysis, energy storage devices and many more. In addition, we have also incorporated the conversion of 2-D graphene to their various other dimensions like zero-, one- or three-dimensional nanostructures. (C) 2016 Elsevier B.V. All rights reserved.

  • 16. Brosselard, P.
    et al.
    Camara, N.
    ul-Hassan, Jawad
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials.
    Jordà, X.
    Bergman, Peder
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials.
    Montserrat, J.
    Millán, J.
    3.3 kV-10A 4H-SiC PiN diodes2009In: Materials Science Forum, Vols. 600-603, Trans Tech Publ. , 2009, 991-994 p.Conference paper (Refereed)
    Abstract [en]

    An innovative process has been developed by Linköping University to prepare the 4HSiC substrate surface before epitaxial growth. The processed PiN diodes have been characterized in forward and reverse mode at different temperature. The larger diodes (2.56 mm2) have a very low leakage current around 20 nA @ 500V for temperatures up to 300°C. A performant yield (68%) was obtained on these larger diodes have a breakdown voltage superior to 500V. Electroluminescence characteristics have been done on these devices and they show that there is no generation of Stacking Faults during the bipolar conduction.

  • 17.
    Waernér, Mikael
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    3D Graphics Technologies for Web Applications: An Evaluation from the Perspective of a Real World Application2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Web applications are becoming increasingly sophisticated and functionality that was once exclusive to regular desktop applications can now be found in web applications as well. One of the more recent advances in this field is the ability for web applications to render 3D graphics. Coupled with the growing number of devices with graphics processors and the ability of web applications to run on many different platforms using a single code base, this represents an exciting new possibility for developers of 3D graphics applications.

    This thesis aims to explore and evaluate the technologies for 3D graphics that can be used in web applications, with the final goal of using one of them in a prototype application. This prototype will serve as a foundation for an application to be included in a commercial product. The evaluation is performed using general criteria so as to be useful for other applications as well, with one part presenting the available technologies and another part evaluating the three most promising technologies more in-depth using test programs.

    The results show that, although some technologies are not production-ready, there are a few which can be used in commercial software, including the three chosen for further evaluation; WebGL, the Java library JOGL and Stage 3D for Flash. Among these, there is no clear winner and it is up to the application requirements to decide which to use. The thesis demonstrates an application built with WebGL and shows that fairly demanding 3D graphics web applications can be built. Also included are the lessons learned during the development and thoughts on the future of 3D graphics in web applications.

  • 18.
    Gardström, Karin
    Linköping University, Department of Science and Technology.
    3D Navigation for Real-Time MRI using Six Degree of Freedom Interaction Devices2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    Real-time MRI scanning is used to visualize tissue and organs in motion. The real-time approach requires new interaction techniques to facilitate interaction with the scanning plane. The aim of this thesis is to investigate the use of input with six degrees of freedom – 6DOF. An overview over existing 6DOF input devices is given. Three devices are chosen for implementation and evaluation, Flock of Birds, SpaceBall and SpaceMouse.

    A simulator application is developed to test the different input devices. The simulator purpose is to imitate the real-time scanning situation. To be able to evaluate speed andaccuracy of the different interaction techniques, methods for measuring time and error are developed. A statistical survey is done on two different tasks to gather data of the interaction. The data is analyzed and the result is that the test subjects find the SpaceMouse superior to the other devices thanks to its kinesthetic feed-back properties and ergonomic benefits. However, the statistical data shows that Flock of Birds is the fastest device and no great difference is showed in accuracy between Flock of Birds and SpaceMouse. SpaceBall was the device that generated the least satisfying data.

  • 19.
    Comina, German
    et al.
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, Faculty of Science & Engineering.
    Suska, Anke
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    Filippini, Daniel
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    3D printed disposable optics and lab-on-a-chip devices for chemical sensing with cell phones2017In: MICROFLUIDICS, BIOMEMS, AND MEDICAL MICROSYSTEMS XV, SPIE-INT SOC OPTICAL ENGINEERING , 2017, Vol. 10061, UNSP 100610EConference paper (Refereed)
    Abstract [en]

    Digital manufacturing (DM) offers fast prototyping capabilities and great versatility to configure countless architectures at affordable development costs. Autonomous lab-on-a-chip (LOC) devices, conceived as only disposable accessory to interface chemical sensing to cell phones, require specific features that can be achieved using DM techniques. Here we describe stereo-lithography 3D printing (SLA) of optical components and unibody-LOC (ULOC) devices using consumer grade printers. ULOC devices integrate actuation in the form of check-valves and finger pumps, as well as the calibration range required for quantitative detection. Coupling to phone camera readout depends on the detection approach, and includes different types of optical components. Optical surfaces can be locally configured with a simple polishing-free post-processing step, and the representative costs are 0.5 US$/device, same as ULOC devices, both involving fabrication times of about 20 min.

  • 20. Comina, German
    et al.
    Suska, Anke
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    Filippini, Daniel
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    3D Printed Unibody Lab-on-a-Chip: Features Survey and Check-Valves Integration dagger2015In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 6, no 4, 437-451 p.Article in journal (Refereed)
    Abstract [en]

    The unibody lab-on-a-chip (ULOC) concept entails a fast and affordable micro-prototyping system built around a single monolithic 3D printed element (unibody). A consumer-grade stereo lithography (SL) 3D printer can configure ULOCs with different forms of sample delivery, transport, handling and readout, while minimizing material costs and fabrication time. ULOC centralizes all complex fabrication procedures and replaces the need for clean room resources, delivering prototypes for less than 1 US$, which can be printed in 10 min and ready for testing in less than 30 min. Recent examples of ULOC integration of transport, chemical sensing for optical readout and flow mixing capabilities are discussed, as well as the integration of the first check-valves for ULOC devices. ULOC valves are strictly unidirectional up to 100 psi, show an exponential forward flow behavior up to 70 psi and can be entirely fabricated with the ULOC approach.

  • 21.
    Khikhlovskyi, Vsevolod
    et al.
    Eindhoven University of Technology, Netherlands; TNO, Netherlands.
    van Breemen, Albert J. J. M.
    Holst Centre, TNO-The Dutch Organization for Applied Scientific Research, The Netherlands.
    Michels, Jasper J.
    Max Planck Institute for Polymer Research (MPI), Germany.
    Janssen, Rene A. J.
    Department of Applied Physics, Eindhoven University of Technology, The Netherlands.
    Gelinck, Gerwin H.
    Department of Applied Physics, Eindhoven University of Technology, The Netherlands; Holst Centre, TNO-The Dutch Organization for Applied Scientific Research, The Netherlands.
    Kemerink, Martijn
    Linköping University, Department of Physics, Chemistry and Biology, Complex Materials and Devices. Linköping University, The Institute of Technology. Department of Applied Physics, Eindhoven University of Technology, The Netherlands.
    3D-Morphology Reconstruction of Nanoscale Phase-Separation in Polymer Memory Blends2015In: Journal of Polymer Science Part B: Polymer Physics, ISSN 0887-6266, E-ISSN 1099-0488, Vol. 53, no 17, 1231-1237 p.Article in journal (Refereed)
    Abstract [en]

    In many organic electronic devices functionality is achieved by blending two or more materials, typically polymers or molecules, with distinctly different optical or electrical properties in a single film. The local scale morphology of such blends is vital for the device performance. Here, a simple approach to study the full 3D morphology of phase-separated blends, taking advantage of the possibility to selectively dissolve the different components is introduced. This method is applied in combination with AFM to investigate a blend of a semiconducting and ferroelectric polymer typically used as active layer in organic ferroelectric resistive switches. It is found that the blend consists of a ferroelectric matrix with three types of embedded semiconductor domains and a thin wetting layer at the bottom electrode. Statistical analysis of the obtained images excludes the presence of a fourth type of domains. The criteria for the applicability of the presented technique are discussed. (c) 2015 Wiley Periodicals, Inc.

  • 22.
    Sanjuan, Joseba
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    3G Energy-Efficient Packet Handling Kernel Module for Android2012Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    The use of mobile devices is increasing due to the constant development of more advanced and appealing applications and computing features. However, these new features are very power hungry leading to short battery lifetimes. Research shows that a major reason for fast battery depletion is the excessive and inefficient use of the wireless interfaces. This thesis studies how we can attempt to increase the battery lifetime of the devices without having to sacrifice the usage of these advanced features in some applications.

    The thesis focuses on adapting the traffic pattern characteristics of mobile communication using a widespread wireless communication technology like 3G. Traffic pattern adaptation is performed at packet level in kernel space in Android. The data transfers are scheduled with the knowledge of the energy consumption characteristics of 3G. The performed measurements indicate that our solution can provide energy savings ranging from 7% to 59%.

    This work confirms that 3G conscious scheduling of network traffic reduces energy consumption, and that, both applications and energy saving libraries are potential directions to be further studied.

  • 23.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.2007In: 2007 International Symposium on System-on-Chip.,2007, Tampere: Tampere University of Technology , 2007, 125- p.Conference paper (Refereed)
  • 24.
    Bengtson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    3V CMOS 0.35 u transimpedance receiver for optical applications2001In: The 2001 IEEE International Symposium on Circuits and Systems, 2001: ISCAS 2001, Piscataway: IEEE , 2001, Vol. 4, 69-71 p.Conference paper (Refereed)
    Abstract [en]

    A new class of receivers for optical applications is described. The novelty of the design is the high speed stage. The receiver is designed for low noise, high bandwidth and high transimpedance-bandwidth product. The receiver is driving a 50 Ω load. Post simulations on chip with all capacitance parasitics and a 0.5 pF diode capacitance, gives a 1.3 GHz bandwidth. For an input diode current of 1 uA=zero and 10 uA=one, the output signal is 0.15 V peak to peak and the output SNR is 23 dB

  • 25.
    Sundbom, Per
    et al.
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Cardiology in Linköping.
    Ahn, Henrik
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    Kornhall, B
    Skane University Hospital, Lund.
    Loebe, M
    Division of Transplant and Assist Devices at Methodist DeBakey Heart & Vascular Centre, Houston, Texas, USA.
    Granfeldt, Hans
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    (556) – Change in Acoustic Fingerprints at Increased Pump Speed During Echocardiographic Ramp Test2014Conference paper (Refereed)
    Abstract [en]

    Purpose

    The continuous flow mechanical circulatory support HeartMate II (Thoratec Corporation, Inc. Pleasanton, USA) (HMII), generates an auditory signal (acoustic fingerprint) that can be registered by routine auscultation. A temporary or permanent change in sound indicates a change in pump function. Previous mock loop studies have shown that changes in acoustic fingerprint are due to changes in speed, so the aim of this study was to see if the acoustic fingerprint changed during an echocardiographic ramp test.

    Methods

    Four stable, event-free patients included in the SoundMate study performed an echocardiographic ramp test. The speed was increased stepwise by 400 rpm between 8 000 and 12 000 rpm, and the left ventricular end diastolic diameter, flow, power consumption and blood pressure were measured. Sounds from HMII were recorded using an iPhone™ (Apple Inc. Cupertino, CA, USA) with the stethoscope application iStethPro™ (Dr. Peter J Bentley, UK) and the frequency map analyzed using the Audacity™ program (Unicode, Ash, Chinen and Crook, USA). The acoustic fingerprint is divided into regions (R1: 1 000-6 500, R2: 8 500-14 000, R3: 15 000-21 000 Hz) and peaks (P1: 0-1 000, P2: 6 500-8 500, P4: 21 000-23 000 Hz) in order to facilitate calculations and clarify changes in frequency.

    Results

    There were significant (p<005) changes in the acoustic fingerprint when increasing the pump speed between 8 000 and 12 000 rpm. In 2/4 patients there were no significant changes in P1, otherwise there were significant changes in all regions and peaks. During the ramp test the power increased in mean 7 W, flow 3,1 L/min and the blood pressure measured with Doppler increased by ~15 mmHg. The left ventricular size decreased with ~2 cm.

    Conclusion

    The acoustic fingerprint changes with pump speed. This implies that when using sound check for detection of pump dysfunction, a new baseline should be set after every adjustment of speed.

  • 26.
    Ahmad, Ijaz
    et al.
    University of Oulu, Finland.
    Kumar, Tanesh
    University of Oulu, Finland.
    Liyanage, Madhusanka
    University of Oulu, Finland.
    Okwuibe, Jude
    University of Oulu, Finland.
    Ylianttila, Mika
    University of Oulu, Finland.
    Gurtov, Andrei
    Linköping University, Department of Computer and Information Science, Database and information techniques. Linköping University, Faculty of Science & Engineering.
    5G Security: Analysis of Threats and Solutions2017In: 2017 IEEE CONFERENCE ON STANDARDS FOR COMMUNICATIONS AND NETWORKING (CSCN), IEEE , 2017, 193-199 p.Conference paper (Refereed)
    Abstract [en]

    5G will provide broadband access everywhere, entertain higher user mobility, and enable connectivity of massive number of devices (e.g. Internet of Things (IoT)) in an ultrareliable and affordable way. The main technological enablers such as cloud computing, Software Defined Networking (SDN) and Network Function Virtualization (NFV) are maturing towards their use in 5G. However, there are pressing security challenges in these technologies besides the growing concerns for user privacy. In this paper, we provide an overview of the security challenges in these technologies and the issues of privacy in 5G. Furthermore, we present security solutions to these challenges and future directions for secure 5G systems.

  • 27. Krishnamurthy, R.
    et al.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Balamurugan, G.
    Shanbhag, N.
    Soumyanath, K.
    Borkar, S.
    A 0.13um 6GHz 256x32b Leakage-tolerant Register File2001In: In proceedings of: International Symposium  on VLSI Circuits, 2001, 25-26 p.Conference paper (Refereed)
  • 28.
    Ragavan, R.
    et al.
    Linköping University, Department of Electrical Engineering.
    Narayanan, A.
    Linköping University, Department of Electrical Engineering.
    Bengtsson, M.
    Linköping University, Department of Electrical Engineering.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 0.35um CMOS 6-bit Current Steering DAC2013Conference paper (Refereed)
  • 29.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 30.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS2009Manuscript (Other academic)
    Abstract [en]

    The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

  • 31.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 0.5–6GHz low gain linear RF front-end in 90nm CMOS2010In: Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems, Warsaw: IEEE , 2010, 168-171 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and measurement results of low gain RF front-end manufactured in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transconductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match better than -8dB up to 8GHz. The voltage conversion gain is 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz. Similarly, measured IIP3 is 2.5dBm and IIP2 is 40dBm at 1GHz. The complete front-end consumes 23mW with active chip area of only 0.048mm2.

  • 32.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices2013In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, 2010-2013 p.Conference paper (Refereed)
    Abstract [en]

    A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

  • 33.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage2013Conference paper (Refereed)
    Abstract [en]

    A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

  • 34.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, 336-339 p.Conference paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 35.
    Edman, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Björklid, Anders
    Saab Dynamics.
    Söderquist, Ingemar
    Saab Dynamics.
    A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters1998In: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers, 1998, 54-55 p.Conference paper (Refereed)
    Abstract [en]

    This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

  • 36.
    Jawed, Syed Arsalan
    et al.
    Elektroniska komponenter Linköpings universitet.
    Hauer, Hans
    Fraunhofer Institute of Integrated Circuits Erlangen, Germany.
    Hartmann, Marcus
    Fraunhofer Institute of Integrated Circuits Erlangen, Germany.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 10-bit 250khz sigma-delta non-uniform quantization analog-to-digital converter.2005In: RadioVetenskap och Kommunikation.,2005, 2005, 275-280 p.Conference paper (Refereed)
  • 37.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 10Gb/s Radio Link Prototype2011In: Radio Frequency MeasurementTechnology Conference (RFMTC), Gävle: Radiocentrum Gävle , 2011Conference paper (Other academic)
  • 38.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, 2306-2310 p.Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 39.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 40.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, 244-248 p.Article in journal (Refereed)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 41.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Carlsson, Ingvar
    EK-ISY Linköpings universitet.
    Natarajan, Sreedhar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 128Kb 5T SRAM in 0.18mm CMOS.2007In: International Conference on Memory Technology and Design ICMTD 2007,2007, 2007, 185- p.Conference paper (Refereed)
  • 42.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems., www.ieee.org , 2010, 29-32 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 43.
    Krishnamurthy, R.K.
    et al.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Balamurugan, G.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Shanbhag, R.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A 130-nm 6-GHz 256x32 bit leakage-tolerant register file2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, 624-632 p.Article in journal (Refereed)
    Abstract [en]

    Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented

  • 44.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS2007In: IEEE International Solid State Circuits Conference (ISSCC), San Francisco, California, USA, Februrary 11-15, IEEE , 2007, 424-613 p.Conference paper (Refereed)
    Abstract [en]

    A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm2. Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

  • 45.
    Hultman, Martin
    et al.
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    Fredriksson, Ingemar
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering. Perimed AB, Järfälla-Stockholm, Sweden.
    Larsson, Marcus
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Strömberg, Tomas
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup2017In: Journal of Biophotonics, ISSN 1864-063X, E-ISSN 1864-0648Article in journal (Refereed)
    Abstract [en]

    A multiple exposure laser speckle contrast imaging (MELSCI) setup for visualizing blood perfusion was developed using a field programmable gate array (FPGA), connected to a 1000 frames per second (fps) 1-megapixel camera sensor. Multiple exposure time images at 1, 2, 4, 8, 16, 32 and 64 milliseconds were calculated by cumulative summation of 64 consecutive snapshot images. The local contrast was calculated for all exposure times using regions of 4 × 4 pixels. Averaging of multiple contrast images from the 64-millisecond acquisition was done to improve the signal-to-noise ratio. The results show that with an effective implementation of the algorithm on an FPGA, contrast images at all exposure times can be calculated in only 28 milliseconds. The algorithm was applied to data recorded during a 5 minutes finger occlusion. Expected contrast changes were found during occlusion and the following hyperemia in the occluded finger, while unprovoked fingers showed constant contrast during the experiment. The developed setup is capable of massive data processing on an FPGA that enables processing of MELSCI data in 15.6 fps (1000/64 milliseconds). It also leads to improved frame rates, enhanced image quality and enables the calculation of improved microcirculatory perfusion estimates compared to single exposure time systems.

    The full text will be freely available from 2018-08-07 12:43
  • 46.
    Ohlsson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 16 GSPS 0.18 µm CMOS decimator for single-bit ∑∆-modulation.2004In: Norchip,2004, Piscataway: IEEE Inc. , 2004, 175- p.Conference paper (Refereed)
  • 47.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOSManuscript (preprint) (Other academic)
  • 48.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 49.
    Yeknami, Ali Fazli
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 uW 76 dB SNDR DT-ΔΣ Modulator for Medical Implant Devices2012In: NORCHIP 2012, IEEE , 2012, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 µW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit.

  • 50.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS2010In: IEEE European Solid-State Circuits Conference, Seville: IEEE , 2010, 370-373 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.

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