Analog to digital converters (ADCs) are the fundamental building blocks in communication
systems. The need to design ADCs, which are area and/or power efficient, has been common.
Various ADC architectures, constrained by resolution capabilities, can be used for this purpose.
The cyclic algorithmic architecture of ADC with moderate number of bits comes out to be
probably best choice for the minimum area implementation. In this thesis a cyclic ADC is
designed using CMOS 65 nm technology. The ADC high-level model is thoroughly explored and
its functional blocks are modelled to attain the best possible performance. In particular, the
nonlinearities which affect the cyclic/algorithmic converter are discussed. This ADC has been
designed for built-in-self-testing (BiST) on a chip. It is only functional during the testing phase,
so power dissipation is not a constraint while designing it. As it is supposed to be integrated as
an extra circuitry on a chip, its area really matters.
The ADC is designed as 10-bit fully differential switch-capacitor (SC) circuit using 65nm
CMOS process with 1.2V power supply. A two stage Operational Transconductance Amplifier
(OTA) is used in this design to provide sufficient voltage gain. The first stage is a telescopic
OTA whereas the second is a common source amplifier. The bottom plate sampling is used to
minimize the charge injection effect which is present in the switches.