liu.seSearch for publications in DiVA
Change search
Refine search result
1234567 1 - 50 of 4237
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the 'Create feeds' function.
  • 1.
    Hassan Raza Naqvi, Syed
    Linköping University, Department of Electrical Engineering.
    1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology2007Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

    Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

  • 2.
    Ahmed Aamir, Syed
    et al.
    University of Bielefeld, Germany .
    Angelov, Pavel
    AnaCatum Design AB, Linkoping, Sweden .
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS2014In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 22, no 4, 888-898 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

  • 3.
    Krus, Petter
    et al.
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.
    Sethson, MagnusLinköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.Ericson, LiselottLinköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.
    13th Scandinavian International Conference on Fluid Power, June 3-5, 2013, Linköping, Sweden2013Conference proceedings (editor) (Refereed)
  • 4.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS2006In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

  • 5.
    Hofvendahl, Maria
    Linköping University, Department of Electrical Engineering.
    2.4 GHz Power Amplifier with Cartesian Feedback for WLAN2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This final year project describes the linearisation method Cartesian feedback and the design of such a feedback with a 2.4GHz power amplifier.

    To investigate the functionality of the Cartesian feedback ideal blocks with no current consumption were made and then gradually analog circuits were introduced into the feedback. The Cartesian feedback design consists of a subtracter, a modulator and a preamplifier in the top path and a demodulator and a filter in the feedback path. The blocks that are discussed in this report are the subtracter and the modulator unit. The circuits are designed in a 0.35µm SiGe BiCMOS technology.

    The result of the Cartesian feedback showed an increase in 1dB compression point by 6.2dBm and the IMD was improved by 17dB.

  • 6.
    Turner, Anthony
    Linköping University, Department of Physics, Chemistry and Biology, Biosensors and Bioelectronics.
    24th Anniversary World Congress on Biosensors – Biosensors 20142014Conference proceedings (editor) (Refereed)
    Abstract [en]

    Welcome to Biosensors 2014 and welcome to Melbourne, ranked as the world's most liveable city!

    This is the 24th anniversary edition of the World Congress on Biosensors and we continue to evolve, adapt and grow into new roles to serve the analytical needs of a rapidly changing society. Advances in telecommunications, expert systems and distributed diagnostics are prompting us to question the conventional ways we deliver healthcare, while robust industrial sensors are facilitating new paradigms in R&D and production. Personalisation of everything from medicine to environmental control, is giving new impetus to consumer choice and ownership of information, and will inevitably generate new payment structures and business models. Moreover, a deeper understanding of the bio/electronic interface leads us towards new horizons in areas such as bionics, power generation and computing.  Wearable, mobile and integrated sensors are becoming common place, but most current products have taken the easy path of incorporating physical sensors for parameters such as temperature, pressure, orientation or position. There is still a glaring absence of suitably robust and convenient commercial biosensors for body chemistries and ecosystems, and therein lies the real opportunities for progress.  We are a still-emerging technology that is fuelling scientific discovery and underpinning new products to enhance the length and quality of life.

    Always in a new country and always with fresh plenary speakers, we aim to reflect the latest and the best in Biosensors. This three-day event, organised by Elsevier in association with Biosensors & Bioelectronics, consists of two daily plenary presentations from leading figures in the field, followed by four parallel sessions, comprising a rigorously refereed selection of submitted papers. This year, we received 1,156 submissions of which 124 with be presented as regular Oral papers, with an additional 20 singled out as Invited talks and a further 12 selected for extended Keynote talks. The Keynote speakers have also been invited to submit full papers for consideration for the Biosensors and Bioelectronics Prize for the most original contribution to the Congress and the winners will be announced at the conference banquet on Thursday night. There will also be poster awards and you will find voting slips for each of the three days in your delegate bags. The winners of these awards and a prize draw, sponsored by Linköping University and Acreo Swedish ICT, will be announced at the closing ceremony on Friday. In order to enhance the valued medium of poster presentation, this year we have introduced a new Poster in my Pocket Ap.  Poster presenters have been able to upload a PDF of their poster prior to the conference to help increase the exposure of their work. This compliments the other new Ap introduced this year to place the full programme at your fingertips. Selected oral presentations will also have the opportunity to upload their talks online for future viewing.

    The academic programme, as usual, is enhanced by a fine collection of commercial exhibits and in addition to browsing their stands; you will be able to hear short elevator pitches during the breaks. We must thank our main commercial sponsor, Ercon for their generous and continued support of our congress. Thanks also to New Tools for Health for sponsoring the pre-congress Networking Event.  Now a regular feature for Biosensors, we have a pre-congress school, this year on Optical Biosensors, which is brought to you by Profs Fran Ligler and Tanya Monro. Last, but not least I must thank our marvellous Local Organising Committee chaired by Prof Justin Gooding, our hard working main Organising Committee, all the speakers and delegates, and the Elsevier team for all their support.

    Our delegates come from the four corners of the globe to hear the science, to grasp the opportunities and to meet the people; it’s going to be the best meeting yet. Enjoy and don’t forget to join us again in Gothenburg, Sweden, 24-27 May for Biosensor 2016!

  • 7.
    Östlund, Martin
    et al.
    Linnaeus University, Kalmar.
    Dahlbäck, Nils
    Linköping University, Department of Computer and Information Science, NLPLAB - Natural Language Processing Laboratory. Linköping University, Faculty of Arts and Sciences.
    Petersson, Göran Ingemar
    Linnaeus University, Kalmar.
    3D Visualization as a Communicative Aid in Pharmaceutical Advice-Giving over Distance2011In: Journal of Medical Internet Research, ISSN 1438-8871, E-ISSN 1438-8871, Vol. 13, no 3Article in journal (Refereed)
    Abstract [en]

    Background: Medication misuse results in considerable problems for both patient and society. It is a complex problem with many contributing factors, including timely access to product information. less thanbrgreater than less thanbrgreater thanObjective: To investigate the value of 3-dimensional (3D) visualization paired with video conferencing as a tool for pharmaceutical advice over distance in terms of accessibility and ease of use for the advice seeker. less thanbrgreater than less thanbrgreater thanMethods: We created a Web-based communication service called AssistancePlus that allows an advisor to demonstrate the physical handling of a complex pharmaceutical product to an advice seeker with the aid of 3D visualization and audio/video conferencing. AssistancePlus was tested in 2 separate user studies performed in a usability lab, under realistic settings and emulating a real usage situation. In the first study, 10 pharmacy students were assisted by 2 advisors from the Swedish National Co-operation of Pharmacies call centre on the use of an asthma inhaler. The student-advisor interview sessions were filmed on video to qualitatively explore their experience of giving and receiving advice with the aid of 3D visualization. In the second study, 3 advisors from the same call centre instructed 23 participants recruited from the general public on the use of 2 products: (1) an insulin injection pen, and (2) a growth hormone injection syringe. First, participants received advice on one product in an audio-recorded telephone call and for the other product in a video-recorded AssistancePlus session (product order balanced). In conjunction with the AssistancePlus session, participants answered a questionnaire regarding accessibility, perceived expressiveness, and general usefulness of 3D visualization for advice-giving over distance compared with the telephone and were given a short interview focusing on their experience of the 3D features. less thanbrgreater than less thanbrgreater thanResults: In both studies, participants found the AssistancePlus service helpful in providing clear and exact instructions. In the second study, directly comparing AssistancePlus and the telephone, AssistancePlus was judged positively for ease of communication (P = .001), personal contact (P = .001), explanatory power (P andlt;.001), and efficiency (P andlt;.001). Participants in both studies said that they would welcome this type of service as an alternative to the telephone and to face-to-face interaction when a physical meeting is not possible or not convenient. However, although AssistancePlus was considered as easy to use as the telephone, they would choose AssistancePlus over the telephone only when the complexity of the question demanded the higher level of expressiveness it offers. For simpler questions, a simpler service was preferred. less thanbrgreater than less thanbrgreater thanConclusions: 3D visualization paired with video conferencing can be useful for advice-giving over distance, specifically for issues that require a higher level of communicative expressiveness than the telephone can offer. 3D-supported advice-giving can increase the range of issues that can be handled over distance and thus improve access to product information.

  • 8.
    Sanjuan, Joseba
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    3G Energy-Efficient Packet Handling Kernel Module for Android2012Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    The use of mobile devices is increasing due to the constant development of more advanced and appealing applications and computing features. However, these new features are very power hungry leading to short battery lifetimes. Research shows that a major reason for fast battery depletion is the excessive and inefficient use of the wireless interfaces. This thesis studies how we can attempt to increase the battery lifetime of the devices without having to sacrifice the usage of these advanced features in some applications.

    The thesis focuses on adapting the traffic pattern characteristics of mobile communication using a widespread wireless communication technology like 3G. Traffic pattern adaptation is performed at packet level in kernel space in Android. The data transfers are scheduled with the knowledge of the energy consumption characteristics of 3G. The performed measurements indicate that our solution can provide energy savings ranging from 7% to 59%.

    This work confirms that 3G conscious scheduling of network traffic reduces energy consumption, and that, both applications and energy saving libraries are potential directions to be further studied.

  • 9.
    Hall, Henning
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Luckey, Christian
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    3G Transmission Energy Savings through Adaptive Traffic Shaping Policies2014Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    This bachelor thesis will explore how two traffic shaping mechanisms can help preserve battery power while retaining a certain Quality of Service (QoS) in an Android based application developed for crisis management. The implemented user-space mechanisms will delay all elastic data requests in order to reduce the number of times the 3G transmission radio enters high power states. This lowers the QoS but extends the user equipment's battery life. The thesis will show that a shaping mechanism has the capability to reduce radio energy usage by up to 50% for the given Android application at the cost of added transmission delays by up to 134 seconds for background traffic. The study also presents two policies that help the application adapt to the current battery level and lower the QoS accordingly, namely one that has a lenient savings effect and one that has an aggressive savings effect.

  • 10.
    Eklund, Anders
    et al.
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization (CMIV). Linköping University, The Institute of Technology.
    Andersson, Mats
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization (CMIV). Linköping University, The Institute of Technology.
    Knutsson, Hans
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, Center for Medical Image Science and Visualization (CMIV). Linköping University, The Institute of Technology.
    4D Medical Image Processing with CUDA2012Conference paper (Other academic)
    Abstract [en]

    Learn how to do 4D image processing with CUDA, especially for medical imaging applications. In this session we will give a couple of examples of how 4D image processing can take advantage of the computational power of the GPU. We will present how to use the GPU for functional magnetic resonance imaging (fMRI) analysis and true 4D image denoising. Most of our examples use the GPU both to speedup the analysis and to visualize the results.

  • 11. Syrkin, A.
    et al.
    Dmitriev, V.
    Soukhoveev, V.
    Mynbaeva, M.
    Kakanakov, R.
    Hallin, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology.
    Janzén, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials.
    4H-SiC Power Schottky Diodes. On the Way to Solve the Size Limiting Issues2004In: Mater. Sci. Forum, Vol. 457-460, Trans Tech Publications Inc. , 2004Conference paper (Refereed)
    Abstract [en]

       

  • 12.
    Sundbom, Per
    et al.
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Cardiology in Linköping.
    Ahn, Henrik
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    Kornhall, B
    Skane University Hospital, Lund.
    Loebe, M
    Division of Transplant and Assist Devices at Methodist DeBakey Heart & Vascular Centre, Houston, Texas, USA.
    Granfeldt, Hans
    Linköping University, Department of Medical and Health Sciences, Division of Cardiovascular Medicine. Linköping University, Faculty of Health Sciences. Östergötlands Läns Landsting, Heart and Medicine Center, Department of Thoracic and Vascular Surgery.
    (556) – Change in Acoustic Fingerprints at Increased Pump Speed During Echocardiographic Ramp Test2014Conference paper (Refereed)
    Abstract [en]

    Purpose

    The continuous flow mechanical circulatory support HeartMate II (Thoratec Corporation, Inc. Pleasanton, USA) (HMII), generates an auditory signal (acoustic fingerprint) that can be registered by routine auscultation. A temporary or permanent change in sound indicates a change in pump function. Previous mock loop studies have shown that changes in acoustic fingerprint are due to changes in speed, so the aim of this study was to see if the acoustic fingerprint changed during an echocardiographic ramp test.

    Methods

    Four stable, event-free patients included in the SoundMate study performed an echocardiographic ramp test. The speed was increased stepwise by 400 rpm between 8 000 and 12 000 rpm, and the left ventricular end diastolic diameter, flow, power consumption and blood pressure were measured. Sounds from HMII were recorded using an iPhone™ (Apple Inc. Cupertino, CA, USA) with the stethoscope application iStethPro™ (Dr. Peter J Bentley, UK) and the frequency map analyzed using the Audacity™ program (Unicode, Ash, Chinen and Crook, USA). The acoustic fingerprint is divided into regions (R1: 1 000-6 500, R2: 8 500-14 000, R3: 15 000-21 000 Hz) and peaks (P1: 0-1 000, P2: 6 500-8 500, P4: 21 000-23 000 Hz) in order to facilitate calculations and clarify changes in frequency.

    Results

    There were significant (p<005) changes in the acoustic fingerprint when increasing the pump speed between 8 000 and 12 000 rpm. In 2/4 patients there were no significant changes in P1, otherwise there were significant changes in all regions and peaks. During the ramp test the power increased in mean 7 W, flow 3,1 L/min and the blood pressure measured with Doppler increased by ~15 mmHg. The left ventricular size decreased with ~2 cm.

    Conclusion

    The acoustic fingerprint changes with pump speed. This implies that when using sound check for detection of pump dysfunction, a new baseline should be set after every adjustment of speed.

  • 13.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications2005In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05, 2005, I/127-I/130 p.Conference paper (Refereed)
    Abstract [en]

    The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

  • 14.
    Al Faisal, Muhammad Saud
    Linköping University, Department of Science and Technology. Linköping University, The Institute of Technology.
    6-9 GHz UWB Antenna-Low-Noise Amplifier Co-design2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    6 - 9 GHz antenna-low-noise amplifier co-design is a demanding task. Higher frequency band has new techniques for circuit design and matching. The usual lumped component matching technique is not an appropriate solution for High Frequency (HF) broad band. The new broad band demands transmission line matching. The low-power and high-data rate Ultra Wide Band (UWB) uses large portion of the communication radio-spectrum and wireless communication. The principal axis of this thesis is co-design in the frequency band of 6 - 9 GHz. The thesis has been divided in two parts, where first part includes implementation and evaluation of individual RF-circuits of circular monopole antenna, a band pass (BP) filter and a low-noise amplifier (LNA), while second part unite all three RF circuits and presents the co-design.

    Microstrip monopole antennas get more and more popular due to rapid change in the wireless communication. Higher datarate and even higher bandwidth demands a simple and compact ultra-wideband (UWB) antenna. Two monopole antennas circular and rectangular monopole antennas were designed. Simulated and experimental results of modified design indicate that antenna was achieved a VSWR of 1.2, with input reflection less then - 10 dB in 4 - 12 GHz band. These characteristic make the designed antenna suitable for various UWB application.

     The broad band matching and the flat gain are the two important factors for the UWB circuits. The co-design of antenna-low-noise amplifier utilizes a inter stage matching technique with a simple band pass filter, a third-order passive Chebychev filter is proposed as an input matching network. The filter achieves forward transmission less the - 0.8 dB and a return loss - 20 dB in 6 - 9 GHz band.

    Low-noise amplifier is the key RF circuit; minimal Noise Figure (NF) and the lower power consumption are desired parameters. The implemented low-noise amplifier (LNA) is the combination of bias network and ultra-wide band radio frequency (RF) choke. AVAGO Technologies pseudmorphic-high-electron-mobility transistor (PHEMT) with (SC-70) plastic package with nominal 0.2 µm gate length is used in amplifier. Passive distributed components of microstrip transmission line were used for matching, simulated results demonstrate maximum power gain of 12.74 dB and minimum noise figure (NFmin) of 1 dB is obtained.

    Finally all three individual RF circuits antenna, filter and low-noise amplifier are integrated into co-design and analyzed for 6 - 9 GHz band. Later on two more new designs are added. This co-design has large potential in Direct-broadcast-satellite (DBS) TV system, X-band radar detector, automotive radar, remote sensors, and Multichannel-multipoint-distribution-systems (MMDS). 

  • 15.
    Du, Chun
    et al.
    Chinese Academy of Science.
    Li, Cuihong
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology.
    Li, Weiwei
    Chinese Academy of Science.
    Chen, Xiong
    Chinese Academy of Science.
    Bo, Zhishan
    Beijing Normal University.
    Veit, Clemens
    Fraunhofer Institute for Solar Energy Systems ISE.
    Ma, Zaifei
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Wuerfel, Uli
    Fraunhofer Institute for Solar Energy Systems ISE.
    Zhu, Hongfei
    Chinese Academy of Science.
    Hu, Wenping
    Chinese Academy of Science.
    Zhang, Fengling
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, The Institute of Technology.
    9-Alkylidene-9H-Fluorene-Containing Polymer for High-Efficiency Polymer Solar Cells2011In: Macromolecules, ISSN 0024-9297, E-ISSN 1520-5835, Vol. 44, no 19, 7617-7624 p.Article in journal (Refereed)
    Abstract [en]

    A novel donor-acceptor copolymer containing 9-alkylidene-9H-fluorene unit in the main chain, poly[9-(1-hexylheptylidene)-2,7-fluorene-alt-5, 5-(4,7-di-2-thienyl-5,6-dialkoxy-2,1,3-benzothiadiazole)] (PAFDTBT), has been synthesized and evaluated in bulk heterojunction polymer solar cells (BHJ PSCs). The polymer possesses a low band gap of 1.84 eV, a low-lying HOMO energy level (5.32 eV), and excellent solubility in common organic solvents. PSCs based on PAFDTBT and (6,6)-phenyl-C(71)-butyric add methyl ester (PC(71)BM) demonstrate a power conversion efficiency (PCE) of 6.2% with a high fill factor (FF) of 0.70, which indicates that 9-alkylidene-9H-fluorene can be a very useful building block for constructing narrow band gap conjugated polymers for high-efficiency BHJ PSCs.

  • 16.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 17.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices2013In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, 2010-2013 p.Conference paper (Refereed)
    Abstract [en]

    A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

  • 18.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage2013Conference paper (Refereed)
    Abstract [en]

    A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

  • 19.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, 336-339 p.Conference paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 20.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, 28-38 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

  • 21.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 22.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, 244-248 p.Article in journal (Refereed)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 23.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems., www.ieee.org , 2010, 29-32 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 24.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-Bit dual current-steering DAC2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper (Other academic)
    Abstract [en]

    A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

  • 25.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-transistor CMOS full adder with full voltage-swing nodes1999In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'99, 1999, 713-722 p.Conference paper (Refereed)
    Abstract [en]

    We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 μm process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder

  • 26.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS2007In: IEEE International Solid State Circuits Conference (ISSCC), San Francisco, California, USA, Februrary 11-15, IEEE , 2007, 424-613 p.Conference paper (Refereed)
    Abstract [en]

    A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm2. Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

  • 27.
    Jakonis, Darius
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    A 1.6 GHz downconversion sampling mixer in CMOS2003In: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003: ISCAS '03, Piscataway: IEEE , 2003, 725-728 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a downconversion sampling mixer design in CMOS. A MOS switch linearization technique is utilized, which enables high frequency sampling of an RF signal. The measurement results show a 1.6 GHz input signal downconversion with a sampling rate of 1.55 GHz, +22 dBm IIP3, 1.4 ps sampling jitter, 8 dB conversion loss and 25 dB noise figure. The chip is fabricated in a 0.35 μm 3.3 V CMOS process and bonded directly onto a printed circuit board. The downconversion sampling mixer occupies an active area of 0.05 mm2 and consumes 43 mW power.

  • 28.
    Säll, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A 1.8V 10-bit 80MS/s Low Power Track-and-Hold Circuit in a 0.18µm CMOS Process2003In: IEEE International Symposium on Circuits and Systems, ISCAS,2003, 2003Conference paper (Other academic)
    Abstract [en]

    A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18um CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the T&H circuit and the amplifier is a folded cascode OTA with gain boosting. This paper describes the design of the complete T&H, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.

  • 29.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 30.
    Yeknami, Ali Fazli
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 uW 76 dB SNDR DT-ΔΣ Modulator for Medical Implant Devices2012In: NORCHIP 2012, IEEE , 2012, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 µW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit.

  • 31.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS2006In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, 257-260 p.Conference paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

  • 32.
    Sundström, Timmy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 2.5-GS/s 30-mW 4-bit flash ADC in 90nm CMOS2008In: NORCHIP, IEEE , 2008, 264-267 p.Conference paper (Refereed)
    Abstract [en]

    A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS, avoids traditional power, speed and accuracy trade-offs by using comparator redundancy with power-gating capabilities. Redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators. Measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 gate-able comparators, the ADC achieves 4.0 effective number of bits.

  • 33.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier2013Manuscript (preprint) (Other academic)
    Abstract [en]

    An ultra-low-voltage low-power switched-capacitor ΔΣ modulator running at a supply voltage as low as 270 mV is presented for medical implant devices. To reduce the supply voltage and power consumption, an inverter-based amplifier is used in the integrator, whose DC-gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. The entire modulator operates at 270 mV supply only, while the switches are driven by charge pump clock doubler. Designed in 65 nm CMOS and clocked at 256 kHz, the simulation results show that the converter achieves 64.4 dB signal-to-noise-ratio (SNR) and 61 dB signal-to-noise-and-distortionratio (SNDR) in 1 kHz bandwidth while consuming 0.85 "W power.

  • 34.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 86-89 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.   

  • 35.
    Johansson, Ted
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bengtsson, Olof
    Lotfi, Sara
    Uppsala University, Sweden.
    Vestling, Lars
    Uppsala University, Sweden.
    Norström, Hans
    Uppsala University, Sweden.
    Olsson, Jörgen
    Uppsala University, Sweden.
    Nyström, Christian
    A +32.8 dBm LDMOS power amplifier for WLAN in 65 nm CMOS technology2013Conference paper (Refereed)
    Abstract [en]

    Postlingually acquired hearing impairment (HI) is associated with changes in the representation of sound in semantic long-term memory. An indication of this is the lower performance on visual rhyme judgment tasks in conditions where phonological and orthographic cues mismatch, requiring high reliance on phonological representations. In this study, event-related potentials (ERPs) were used for the first time to investigate the neural correlates of phonological processing in visual rhyme judgments in participants with acquired HI and normal hearing (NH). Rhyme task word pairs rhymed or not and had matching or mismatching orthography. In addition, the inter-stimulus interval (ISI) was manipulated to be either long (800 ms) or short (50 ms). Long ISIs allow for engagement of explicit, top-down processes, while short ISIs limit the involvement of such mechanisms. We hypothesized lower behavioral performance and N400 and N2 deviations in HI in the mismatching rhyme judgment conditions, particularly in short ISI. However, the results showed a different pattern. As expected, behavioral performance in the mismatch conditions was lower in HI than in NH in short ISI, but ERPs did not differ across groups. In contrast, HI performed on a par with NH in long ISI. Further, HI, but not NH, showed an amplified N2-like response in the non-rhyming, orthographically mismatching condition in long ISI. This was also the rhyme condition in which participants in both groups benefited the most from the possibility to engage top-down processes afforded with the longer ISI. Taken together, these results indicate an early ERP signature of HI in this challenging phonological task, likely reflecting use of a compensatory strategy. This strategy is suggested to involve increased reliance on explicit mechanisms such as articulatory recoding and grapheme-to-phoneme conversion.

  • 36.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE2011In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE , 2011, 127-130 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

  • 37.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 241-247 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 38.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2013Conference paper (Other academic)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 39.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2012In: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, 369-372 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

  • 40.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 4-bit 2.5-GS/s 30-mW Flash ADC in 90nm CMOS2009In: Swedish System on Chip Conference, SSoCC, Arild, May 4-5, Lunds universitet, 2009Conference paper (Other academic)
    Abstract [en]

    A 2.5 GS/s flash ADC, fabricated in 90nm CMOS,avoids traditional power, speed and accuracy trade-offs by usingcomparator redundancy with power-gating capabilities.Redundancy removes the need to control comparator offsets,allowing the large process-variation induced mismatch of smalldevices in nanometer technologies. This enables the use of smallsized,ultra-low-power comparators. Measurement results showthat the ADC dissipates 30 mW at 1.2 V. With 63 gate-ablecomparators, the ADC achieves 4.0 effective number of bits.

  • 41.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS2010In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

  • 42.
    Ahmed, Tanvir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Garrido, Mario
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 512-point 8-parallel pipelined feedforward FFT for WPAN2011In: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), IEEE , 2011, 981-984 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm2.

  • 43.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices2011In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland: IEEE Solid-State Circuits Society, 2011, 467-470 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes an ultra-low-power SAR ADC in 0.13-um CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-um CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

  • 44.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, 1585-1593 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

  • 45.
    Vangal, Sriram R.
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Hoskote, Yatin V.
    Intel Microprocessor Technology Labs.
    Borkar, Nitin Y.
    Intel Microprocessor Technology Labs.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 6.2 GFLOPS Floating Point Multiply-Accumulator with Conditional Normalization2006In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 41, no 10, 2314-2323 p.Article in journal (Refereed)
    Abstract [en]

    A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic with delayed addition is described. A combination of algorithmic, logic, and circuit techniques enables multiply-accumulate operations at speeds exceeding 3 GHz with single-cycle throughput. The optimizations allow removal of the costly normalization step from the critical accumulate loop. This logic is conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading-zero anticipator (LZA) and overflow prediction logic applicable to carry-save format is presented. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFlops of performance while dissipating 1.2 W at 3.1 GHz, 1.3-V supply

  • 46.
    Aamir, Syed Ahmed
    Linköping University. Linköping University, Department of Electrical Engineering.
    A 65nm, Low Voltage, Fully Differential, SC Programmable Gain Amplifier for Video AFE2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Due to rapid growth of home entertainment consumer market, video technology has been continuously pushed to deliver sharper pictures with higher resolution. This has brought about stringent requirements on the video analog front end, which often coupled with the low power and low voltage regulations had to deal with short channel effects of the deep submicron CMOS processes.

    This thesis presents the design of a fully differential programmable gain amplifier, as a subcircuit of a larger video digitizing IC designed at division of Electronic Systems. The switched capacitor architecture of the PGA does not only buffer the signal, but performs compensation for the sync-tip of analog video signal.

    The pseudo differential OTA eliminates tail current source and maintains high signal swing and has efficient common mode feedforward mechanism. When coupled with a similar stage provides inherent common moode feedback without using an additional SC-CMFB block.

    The PGA has been implemented using a 65 nm digital CMOS process. Expected difficulties in a 1.2 V OTA design make themselves evident in 65 nm, which is why cascaded OTA structures were inevitable for attaining gain specification of 60 dB. Nested Miller compensation with a pole shifting source follower, stabilizes the multipole system. The final circuit attains up to 200 MHz bandwidth and maintains high output swing of 0.85 V. High slew rate and good common mode and power supply rejection are observed. Noise requirements require careful design of input differential stage. Although output source follower stabilized the system, it reduces significant bandwidth and adds to second order non-linearity.

  • 47.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 215-222 p.Article in journal (Refereed)
    Abstract [en]

    A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

  • 48.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Ted
    Infineon Technologies Nordic AB Isafjordsgatan 16, SE-164 81 Stockholm, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 72.2Mbit/s LC-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN2008In: Proceedings of the 15th Mixed Design of Integrated Circuits and Systems (MIXDES) Conference, IEEE , 2008, 155-158 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and evaluation of a power amplifier (PA) for WLAN 802.11n in 65nm CMOS technology. The PA utilizes 3.3V thick-gate oxide (5.2nm) transistors and a two-stage differential configuration with two integrated inductors for input and interstage matching. For a 72.2Mbit/s, 64-QAM 802.11n OFDM signal at an average and peak output power of 9.4dBm and 17.4dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 14dBm.

  • 49.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN2008In: Proceedings of 26th IEEE NORCHIP Conference, IEEE , 2008, 54-56 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick-gate oxide (5.2 nm) transistors and a two-stage differential configuration with two integrated transformers for input and interstage matching. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 dBm and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 50.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOSManuscript (preprint) (Other academic)
    Abstract [en]

    This paper presents a pipeline analog-to-digital converter achieving 7.5 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used and by individually biasing the pMOS and nMOS, symmetrical layout as well as transconductance can be achieved, resulting in increased closed-loop linearity and a THD of -52 dB. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary weighted capacitors, which removes the need for digital background calibration. With a power dissipation of 73 mW and an FoM of 0.4 pJ/conv-step, high sample-rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency.

1234567 1 - 50 of 4237
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf