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  • 1.
    Hassan Raza Naqvi, Syed
    Linköping University, Department of Electrical Engineering.
    1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology2007Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

    Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

  • 2.
    Chen, J.
    et al.
    Ericsson Research.
    Ze, H.
    Chalmers University of Technology.
    Bao, L.
    Ericsson Research.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Li, Y.
    Ericsson Research.
    Gunnarsson, S.
    SiversIMA AB.
    Stoij, C.
    SiversIMA AB.
    Zirath, H.
    Chalmers University of Technology.
    10 Gbps 16QAM Transmission over a 70/80 GHz (E-band) Radio Test-bed2012In: 2012 7th European Microwave Integrated Circuit Conference, IEEE , 2012, 556-559 p.Conference paper (Refereed)
    Abstract [en]

    A millimeter-wave radio test-bed is implemented which demonstrates 16QAM transmission over 70/80 GHz band for data rate up to 10 Gbps. Performance of the 16QAM transmitter and receiver is evaluated in a loop-back lab set-up. With the proposed 10 Gbps on single carrier system architecture, it is possible to achieve 40 Gbps over a 5 GHz bandwidth when combined with polarization and spatial multiplexing.

  • 3.
    Li, Jia
    Linköping University, Department of Electrical Engineering.
    10G GPON Management System Study and Implementation2009Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis includes the GPON management system concept study and implementation work to translate the command line interface management mechanism to a user friendly GUI (graphic user interface). The original system was developed in C program with a client-server structure. The new system retains the same communication structure and protocol interface between the OLT PON card and user workstations. On the workstation side, a new GUI management client application is developed in Java to offer the similar functionalities as the original one, and a totally new graphic real-time system traffic statistics function is integrated to make it easier for user to monitor system traffic information in real time.

     

    The main object of this project is to study the GPON specifications, and understand GPON system working procedure and traffic transmission principle. On the other hand, ‘original system management application’ study is necessary including third party documentation reading and C code understanding. This study has resulted in the development of a new application in Java with third party user libraries and plug-ins. This new application has been tested using basic function tests executed in the GPON lab environment.

  • 4.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    11th Swedish System-on-Chip Conference Sponsored by SSCS-Sweden in May2011Other (Other (popular science, discussion, etc.))
  • 5.
    Ahmed Aamir, Syed
    et al.
    University of Bielefeld, Germany .
    Angelov, Pavel
    AnaCatum Design AB, Linkoping, Sweden .
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS2014In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 22, no 4, 888-898 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

  • 6.
    Krus, Petter
    et al.
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.
    Sethson, MagnusLinköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.Ericson, LiselottLinköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, The Institute of Technology.
    13th Scandinavian International Conference on Fluid Power, June 3-5, 2013, Linköping, Sweden2013Conference proceedings (editor) (Refereed)
  • 7.
    Halling, Jon
    Linköping University, Department of Electrical Engineering.
    1553-Simulator. In-/uppspelning av databusstrafik med hjälp av FPGA2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    At Saab Aerospace in Linköping, components for measurement systems to the fighter aircraft JAS 39 Gripen are developed. In this activity you sometimes want to record the traffic transmitted on the data busses that connects different sys-tems. This traffic on the data busses is using the military standard MIL-STD-1553.

    This project has aimed to create a system for recording and sending 1553-data. The system is used on an ordinary personal computer, equipped with a recon- figurable I/O card that among others has a programmable logic circuit (FPGA). The recorded data are stored on a hard drive. The system has a graphical user interface, where the user can configure different methods of filtering the data, and other preferences.

    The completed system has currently the capacity to record one channel. This works excellent and the system basically meets all the requirements stated at the start of the project. By using this system instead of the commercial available systems on the market one will get a competitive alternative. If the system where to be developed further, with more channels, it would get even more price worth. Both in case of price per channel, but also in functionality. This is because it is possible to design exactly the functions the user demands. But the current version is already fully functional and competitive compared to commercial systems.

  • 8.
    Zhang, Xuanjun
    et al.
    Structure Research Laboratory and Department of Chemistry, University of Science and Technology of China.
    Xie, Yi
    Structure Research Laboratory and Department of Chemistry, University of Science and Technology of China.
    Zhao, Qingrui
    Structure Research Laboratory and Department of Chemistry, University of Science and Technology of China.
    Tian, Yupeng
    Department of Chemistry, Anhui University, China.
    1-D coordination polymer template approach to CdS and HgS aligned-nanowire bundles2003In: New Journal of Chemistry, ISSN 1144-0546, E-ISSN 1369-9261, Vol. 27, no 5, 827-830 p.Article in journal (Refereed)
    Abstract [en]

    A 1D inorganic coordination polymer template route was firstly developed to synthesize metal sulfide aligned-nanowire bundles. Based on this strategy, CdS and HgS aligned-nanowire bundles with high yields were successfully prepared in a water system at room temperature using KCd(NCS)3 as a soft template. The results revealed that the morphologies of the MS (M=Cd, Hg) aligned-nanowire bundles were uniform with lengths of several microns and the diameters of each single wire were ca. 10–30 nm and 60–80 nm for CdS and HgS, respectively.

  • 9.
    Ren, Junyan
    et al.
    Fudan University.
    Gustafsson, OscarLinköping University, Department of Electrical Engineering, Electronics System.
    2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)2010Conference proceedings (editor) (Other academic)
  • 10.
    Kang, Shi-Yun
    et al.
    Linköping University, Department of Electrical Engineering.
    Wen, Hsiang-Chih
    Linköping University, Department of Electrical Engineering.
    2.4G ~ 10.4G Hz CMOS programmable Frequency Divider2005Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden.

    The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project.

    A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report.

    The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.

  • 11.
    Bengtsson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    2.5 Gb/s equalizer for opticla communication.2002In: Swedish System-on-Chip,2002, 2002Conference paper (Other academic)
  • 12.
    Vapen, Anna
    et al.
    Linköping University, Department of Computer and Information Science, Database and information techniques. Linköping University, The Institute of Technology.
    Byers, David
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, Database and information techniques.
    Shahmehri, Nahid
    Linköping University, Department of Computer and Information Science, Database and information techniques. Linköping University, The Institute of Technology.
    2-clickAuth - Optical Challenge-Response Authentication2010In: International Conference on Availability, Reliability, and Security, 2010. ARES '10, IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA , 2010, 79-86 p.Conference paper (Refereed)
    Abstract [en]

    Internet users today often have usernames and passwords at multiple web sites. To simplify things, many sites support some form of federated identity management, such as OpenID, that enables users to have a single account that allows them to log on to many different sites by authenticating to a single identity provider. Most identity providers perform authentication using a username and password. Should these credentials be compromised, e. g. captured by a key logger or malware on an untrusted computer, all the users accounts become compromised. Therefore a more secure authentication method is desirable. We have implemented 2-clickAuth, an optical challenge-response solution where a web camera and a camera phone are used for authentication. Two-dimensional barcodes are used for the communication between phone and computer, which allows 2-clickAuth to transfer relatively large amounts of data in a short period of time. 2-clickAuth is considerably more secure than passwords while still being easy to use and easy to distribute to users. This makes 2-clickAuth a viable alternative to passwords in systems where enhanced security is desired, but availability, ease-of-use, and cost cannot be compromised. We have implemented an identity provider in the OpenID federated identity management system that uses 2clickAuth for authentication, making 2-clickAuth available to all users of sites that support OpenID, including Facebook, Sourceforge and MySpace.

  • 13.
    Vapen, Anna
    et al.
    Linköping University, Department of Computer and Information Science, Database and information techniques. Linköping University, The Institute of Technology.
    Shahmehri, Nahid
    Linköping University, Department of Computer and Information Science, Database and information techniques. Linköping University, The Institute of Technology.
    2-clickAuth - Optical Challenge-Response Authentication using Mobile Handsets2011In: International Journal on Mobile Computing and Multimedia Communications, ISSN 1937-9412, E-ISSN 1937-9404, Vol. 3, no 2, 1-18 p.Article in journal (Refereed)
    Abstract [en]

    Internet users often have usernames and passwords at multiple web sites. To simplify things, many sites support federated identity management, which enables users to have a single account allowing them to log on to different sites by authenticating to a single identity provider. Most identity providers perform authentication using a username and password. Should these credentials be compromised, all of the user’s accounts become compromised. Therefore a more secure authentication method is desirable. This paper implements 2-clickAuth, a multimedia-based challenge-response solution which uses a web camera and a camera phone for authentication. Two-dimensional barcodes are used for the communication between phone and computer, which allows 2-clickAuth to transfer relatively large amounts of data in a short period of time. 2-clickAuth is more secure than passwords while easy to use and distribute. 2-clickAuth is a viable alternative to passwords in systems where enhanced security is desired, but availability, ease-of-use, and cost cannot be compromised. This paper implements an identity provider in the OpenID federated identity management system that uses 2-clickAuth for authentication, making 2-clickAuth available to all users of sites that support OpenID, including Facebook, Sourceforge, and MySpace.

  • 14.
    Auer, Cornelia
    et al.
    Zuse Institute Berlin, Berlin, Germany.
    Nair, Jaya
    IIIT – Bangalore, Electronics City, Hosur Road, Bangalore, India.
    Zobel, Valentin
    Zuse Institue Berlin, Berlin, Germany.
    Hotz, Ingrid
    Zuse Institue Berlin, Berlin, Germany.
    2D Tensor Field Segmentation2011In: Dagstuhl Follow-Ups, E-ISSN 1868-8977, Vol. 2, 17-35 p.Article in journal (Refereed)
    Abstract [en]

    We present a topology-based segmentation as means for visualizing 2D symmetric tensor fields. The segmentation uses directional as well as eigenvalue characteristics of the underlying field to delineate cells of similar (or dissimilar) behavior in the tensor field. A special feature of the resulting cells is that their shape expresses the tensor behavior inside the cells and thus also can be considered as a kind of glyph representation. This allows a qualitative comprehension of important structures of the field. The resulting higher-level abstraction of the field provides valuable analysis. The extraction of the integral topological skeleton using both major and minor eigenvector fields serves as a structural pre-segmentation and renders all directional structures in the field. The resulting curvilinear cells are bounded by tensorlines and already delineate regions of equivalent eigenvector behavior. This pre-segmentation is further adaptively refined to achieve a segmentation reflecting regions of similar eigenvalue and eigenvector characteristics. Cell refinement involves both subdivision and merging of cells achieving a predetermined resolution, accuracy and uniformity of the segmentation. The buildingblocks of the approach can be intuitively customized to meet the demands or different applications. Application to tensor fields from numerical stress simulations demonstrates the effectiveness of our method.

  • 15.
    Ask, Per
    et al.
    Linköping University, Department of Biomedical Engineering, Physiological Measurements. Linköping University, The Institute of Technology.
    Hägglund, Sture
    Linköping University, Department of Computer and Information Science, Human-Centered systems. Linköping University, The Institute of Technology.
    Olsson, Jan
    Linköping University, Department of Management and Engineering. Linköping University, Faculty of Arts and Sciences.
    Pettersson, Nils-Erik
    Sjöqvist, Bengt-Arne
    Åhlfeldt, Hans
    Linköping University, Department of Biomedical Engineering, Medical Informatics. Linköping University, The Institute of Technology.
    36-nätet och "pensionärsdatorer" kan bidra till att lösa sjukvårdens problem2003In: Läkartidningen, ISSN 0023-7205, Vol. 100, no 14, 1257-1258 p.Article in journal (Refereed)
  • 16.
    Ji, W
    et al.
    ABB Corp Res, SE-72178 Vasteras, Sweden Royal Inst Technol, Faxen Lab, SE-10044 Stockholm, Sweden Linkoping Univ, IFM, SE-58183 Linkoping, Sweden.
    Lofgren, PM
    ABB Corp Res, SE-72178 Vasteras, Sweden Royal Inst Technol, Faxen Lab, SE-10044 Stockholm, Sweden Linkoping Univ, IFM, SE-58183 Linkoping, Sweden.
    Hallin, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology.
    Gu, CY
    ABB Corp Res, SE-72178 Vasteras, Sweden Royal Inst Technol, Faxen Lab, SE-10044 Stockholm, Sweden Linkoping Univ, IFM, SE-58183 Linkoping, Sweden.
    3-D computational modeling of SiC epitaxial growth in a hot wall reactor2000In: Materials Science Forum, ISSN 0255-5476, Vol. 338-3, 149-152 p.Article in journal (Refereed)
    Abstract [en]

    A three-dimensional computational model for chemical vapor deposition (CVD) of silicon carbide (SiC) in a hot wall reactor is developed, where the susceptor is tapered with a rectangular cross-section. The present work focuses on the advection-diffusion-reaction process in the susceptor. The precursors are propane and silane, and the carrier gas is hydrogen with mass fraction higher than 98%. Computed growth rates under different system pressures and precursor concentrations are compared with the experimental data measured on samples grown in the Linkoping CVD reactor. The gas composition distribution and the growth rate profile are shown. Dependence of the growth rate on precursor concentrations is investigated.

  • 17. Imura, M
    et al.
    Kuroda, T
    Oshiro, O
    Chihara, K
    Brandberg, Joakim
    Linköping University, The Institute of Technology. Linköping University, Department of Biomedical Engineering, Physiological Measurements.
    Ask, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Biomedical Engineering, Physiological Measurements.
    3-D flow visualization for construction of the model of the blood flow in the heart2000In: Japanese Journal of Applied Physics, ISSN 0021-4922, Vol. 39, no 5 B, 3246-3251 p.Article in journal (Refereed)
    Abstract [en]

    The authors have been developing a model of blood flow in the heart. The flow model of the heart enables us to estimate the entire blood flow of the heart from a couple of 2-D color Doppler images. Therefore, the load on patients is expected to be reduced. To develop the model of the heart, precise observation and an understanding of the blood flow are indispensable, because the flow is strongly related to the diagnosis of heart diseases. The visualization method must have the following features: (1) 3-D (2) objectivity (3) interactivity and (4) multi-aspect. The authors have developed visualization methods to meet the above-mentioned requirements and evaluated the proposed methods with the in-vitro flow data set. The results clearly reveal that the proposed system enables the researchers of the modeling group to obtain the state of entire flow, such as the occurrence of turbulence.

  • 18.
    Lundqvist, Tobias
    Linköping University, Department of Electrical Engineering, Computer Vision.
    3D mapping with iPhone2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Today, 3D models of cities are created from aerial images using a camera rig. Images, together with sensor data from the flights, are stored for further processing when building 3D models. However, there is a market demand for a more mobile solution of satisfactory quality. If the camera position can be calculated for each image, there is an existing algorithm available for the creation of 3D models.

    This master thesis project aims to investigate whether the iPhone 4 offers good enough image and sensor data quality from which 3D models can be created. Calculations on movements and rotations from sensor data forms the foundation of the image processing, and should refine the camera position estimations.

    The 3D models are built only from image processing since sensor data cannot be used due to poor data accuracy. Because of that, the scaling of the 3D models are unknown and a measurement is needed on the real objects to make scaling possible. Compared to a test algorithm that calculates 3D models from only images, already available at the SBD’s system, the quality of the 3D model in this master thesis project is almost the same or, in some respects, even better when compared with the human eye.

  • 19.
    Wikström, Jonas
    Linköping University, Department of Management and Engineering, Machine Design.
    3D Model of Fuel Tank for System Simulation: A methodology for combining CAD models with simulation tools2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Engineering aircraft systems is a complex task. Therefore models and computer simulations are needed to test functions and behaviors of non existing systems, reduce testing time and cost, reduce the risk involved and to detect problems early which reduce the amount of implementation errors. At the section Vehicle Simulation and Thermal Analysis at Saab Aeronautics in Linköping every basic aircraft system is designed and simulated, for example the fuel system. Currently 2-dimensional rectangular blocks are used in the simulation model to represent the fuel tanks. However, this is too simplistic to allow a more detailed analysis. The model needs to be extended with a more complex description of the tank geometry in order to get a more accurate model.

    This report explains the different steps in the developed methodology for combining 3-dimensional geometry models of any fuel tank created in CATIA with dynamic simulation of the fuel system in Dymola. The new 3-dimensional representation of the tank in Dymola should be able to calculate fuel surface location during simulation of a maneuvering aircraft. 

    The first step of the methodology is to create a solid model of the fuel contents in the tank. Then the area of validity for the model has to be specified, in this step all possible orientations of the fuel acceleration vector within the area of validity is generated. All these orientations are used in the automated volume analysis in CATIA. For each orientation CATIA splits the fuel body in a specified number of volumes and records the volume, the location of the fuel surface and the location of the center of gravity. This recorded data is then approximated with the use of radial basis functions implemented in MATLAB. In MATLAB a surrogate model is created which are then implemented in Dymola. In this way any fuel surface location and center of gravity can be calculated in an efficient way based on the orientation of the fuel acceleration vector and the amount of fuel.

    The new 3-dimensional tank model is simulated in Dymola and the results are compared with measures from the model in CATIA and with the results from the simulation of the old 2-dimensional tank model. The results shows that the 3-dimensional tank gives a better approximation of reality and that there is a big improvement compared with the 2-dimensional tank model. The downside is that it takes approximately 24 hours to develop this model.

  • 20.
    Markström, Johannes
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    3D Position Estimation of a Person of Interest in Multiple Video Sequences: People Detection2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In most cases today when a specific person's whereabouts is monitored through video surveillance it is done manually and his or her location when not seen is based on assumptions on how fast he or she can move. Since humans are good at recognizing people this can be done accurately, given good video data, but the time needed to go through all data is extensive and therefore expensive. Because of the rapid technical development computers are getting cheaper to use and therefore more interesting to use for tedious work.

    This thesis is a part of a larger project that aims to see to what extent it is possible to estimate a person of interest's time dependent 3D position, when seen in surveillance videos. The surveillance videos are recorded with non overlapping monocular cameras. Furthermore the project aims to see if the person of interest's movement, when position data is unavailable, could be predicted. The outcome of the project is a software capable of following a person of interest's movement with an error estimate visualized as an area indicating where the person of interest might be at a specific time.

    This thesis main focus is to implement and evaluate a people detector meant to be used in the project, reduce noise in position measurement, predict the position when the person of interest's location is unknown, and to evaluate the complete project.

    The project combines known methods in computer vision and signal processing and the outcome is a software that can be used on a normal PC running on a Windows operating system. The software implemented in the thesis use a Hough transform based people detector and a Kalman filter for one step ahead prediction. The detector is evaluated with known methods such as Miss-rate vs. False Positives per Window or Image (FPPW and FPPI respectively) and Recall vs. 1-Precision.

    The results indicate that it is possible to estimate a person of interest's 3D position with single monocular cameras. It is also possible to follow the movement, to some extent, were position data are unavailable. However the software needs more work in order to be robust enough to handle the diversity that may appear in different environments and to handle large scale sensor networks.

  • 21.
    Johansson, Victor
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    3D Position Estimation of a Person of Interest in Multiple Video Sequences: Person of Interest Recognition2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Because of the increase in the number of security cameras, there is more video footage available than a human could efficiently process. In combination with the fact that computers are getting more efficient, it is getting more and more interesting to solve the problem of detecting and recognizing people automatically.

    Therefore a method is proposed for estimating a 3D-path of a person of interest in multiple, non overlapping, monocular cameras. This project is a collaboration between two master theses. This thesis will focus on recognizing a person of interest from several possible candidates, as well as estimating the 3D-position of a person and providing a graphical user interface for the system. The recognition of the person of interest includes keeping track of said person frame by frame, and identifying said person in video sequences where the person of interest has not been seen before.

    The final product is able to both detect and recognize people in video, as well as estimating their 3D-position relative to the camera. The product is modular and any part can be improved or changed completely, without changing the rest of the product. This results in a highly versatile product which can be tailored for any given situation.

  • 22.
    Karhu, Jonas
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    3-D Positioning in Large Warehouses using Radio-frequency identification2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In large warehouses, there are a lot of articles that needs do be kept track of. As the number of articles grows larger, the administrative complexity increases. Thus, a solution that automatically keeps track of the position of each article in real-time is of interest. That is, if an item in the warehouse is moved, no manual administration should be needed to know the new position of the item.

    Radio detection and ranging (RADAR) is a ranging technique that doesn’t need to communicate with an object to find the distance to it, instead signals are sent and when they are reflected off the object and returned to the sender, the distance to the object may be calculated. However, you cannot tell two equally shaped objects apart purely based on RADAR techniques. There are many other techniques for ranging, sound navigation and ranging (SONAR) is another example, but they all lack the possibility of detecting the identity of the object.

    So, in order to find a specific item’s position, some kind of  communication with the item is necessary. Radiofrequency identification (RFID) is a neat technology with which this is possible. An RFID reader can send radio signals out in the air, and objects that are in the vicinity of the reader and are tagged with an RFID tag can receive that signal and respond with it’s unique identification number. This way, the RFID reader can identify the RFID tagged object from a distance. There are also a variety of ways to approximate the distance between reader and tag. Unfortunately this is a rather difficult task, especially in indoor  environments.

    There are already some existing products on the market that uses RFID for different kinds of positioning. In this thesis, the theory behind positioning, the fundamentals of RFID and different positioning solutions will be analysed and presented.

    A number of tests were carried out with an RFID system within the ultra-high frequency (UHF) band, which is around 866 MHz. The test system only supported range estimation based on the received signal strength indicator (RSSI) and the test results showed that narrowband RSSI measurements are highly disturbed by multipath propagation which make the overall positioning performance insufficient. Further analysis of time based range estimation techniques, such as time of arrival (TOA), time of flight (TOF) and time difference of arrival (TDOA), revealed that better positioning accuracy is possible, especially if ultra-wide bandwidth (UWB) is used.

  • 23. Comina, German
    et al.
    Suska, Anke
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    Filippini, Daniel
    Linköping University, Department of Physics, Chemistry and Biology, Chemical and Optical Sensor Systems. Linköping University, Faculty of Science & Engineering.
    3D Printed Unibody Lab-on-a-Chip: Features Survey and Check-Valves Integration dagger2015In: Micromachines, ISSN 2072-666X, Vol. 6, no 4, 437-451 p.Article in journal (Refereed)
    Abstract [en]

    The unibody lab-on-a-chip (ULOC) concept entails a fast and affordable micro-prototyping system built around a single monolithic 3D printed element (unibody). A consumer-grade stereo lithography (SL) 3D printer can configure ULOCs with different forms of sample delivery, transport, handling and readout, while minimizing material costs and fabrication time. ULOC centralizes all complex fabrication procedures and replaces the need for clean room resources, delivering prototypes for less than 1 US$, which can be printed in 10 min and ready for testing in less than 30 min. Recent examples of ULOC integration of transport, chemical sensing for optical readout and flow mixing capabilities are discussed, as well as the integration of the first check-valves for ULOC devices. ULOC valves are strictly unidirectional up to 100 psi, show an exponential forward flow behavior up to 70 psi and can be entirely fabricated with the ULOC approach.

  • 24.
    Lång, Magnus
    Linköping University, The Institute of Technology. Linköping University, Department of Science and Technology.
    3D Teleconferencing: The construction of a fully functional, novel 3D Teleconferencing system2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This report summarizes the work done to develop a 3D teleconferencing system, which enables remote participants anywhere in the world to be scanned in 3D, transmitted and displayed on a constructed 3D display with correct vertical and horizontal parallax, correct eye contact and eye gaze. The main focus of this report is the development of this system and especially how to in an efficient and general manner render to the novel 3D display. The 3D display is built out of modified commodity hardware and show a 3D scene for observers in up to 360 degrees around it and all heights. The result is a fully working 3D Teleconferencing system, resembling communication envisioned in movies such as holograms from Star Wars. The system transmits over the internet, at similar bandwidth requirements as concurrent 2D videoconferencing systems.

  • 25.
    Arvidsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    3D Visualization Package for OpenModelica2012Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    A 3D representation of a physical phenomena is often a good way to present it. It’s often easier to see an event in an animation rather than just read data tables. The goal of this thesis is to create an application that visualizes a physical simulation in Modelica. This thesis explains how the OMVisualize application was developed. To create the OMVisualize the OpenSceneGraph library was used. The OpenSceneGraph is a 3D package written in C++ that is used in many different applications from game to scientific applications.

  • 26.
    Dunström, Hampus
    et al.
    Linköping University, Department of Computer and Information Science.
    Holmberg, Olof
    Linköping University, Department of Computer and Information Science.
    Jannering, Gustav
    Linköping University, Department of Computer and Information Science.
    Karlsson, Michael
    Linköping University, Department of Computer and Information Science.
    Lundberg, Martin
    Linköping University, Department of Computer and Information Science.
    Tuhkala, Hannes
    Linköping University, Department of Computer and Information Science.
    Wallström, Fredrik
    Linköping University, Department of Computer and Information Science.
    3D-Kopiering: Registrering och meshning av punktmoln för utskrift2017Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    The technology to be able to print 3D objects has been available for many years, but it is only recently that 3D printers have been made available for regular consumers. There is one issue though: to be able to use the 3D printer either knowledge of CAD software or 3D models made by others are needed. By using a system for 3D copying a real object can instead be copied. This report presents a bachelor project that was done by seven students studying engineering programs in computer science or software technology at Linköping University, 2017. The goal of the project was to develop a system that could take several point clouds as input and then register them to a complete point cloud. Then use this point cloud to generate a 3D mesh to be printed on a 3D printer. The 3D printer will then be able to print the object. In the early stages of the project the main focus was to develop an already existing system. This goal was then renegotiated since the existing system contained several errors. The project resulted in 3DCopy, a software system that registers point clouds and from these point clouds generates a 3D mesh.

  • 27.
    Khikhlovskyi, Vsevolod
    et al.
    Eindhoven University of Technology, Netherlands; TNO, Netherlands.
    van Breemen, Albert J. J. M.
    Holst Centre, TNO-The Dutch Organization for Applied Scientific Research, The Netherlands.
    Michels, Jasper J.
    Max Planck Institute for Polymer Research (MPI), Germany.
    Janssen, Rene A. J.
    Department of Applied Physics, Eindhoven University of Technology, The Netherlands.
    Gelinck, Gerwin H.
    Department of Applied Physics, Eindhoven University of Technology, The Netherlands; Holst Centre, TNO-The Dutch Organization for Applied Scientific Research, The Netherlands.
    Kemerink, Martijn
    Linköping University, Department of Physics, Chemistry and Biology, Complex Materials and Devices. Linköping University, The Institute of Technology. Department of Applied Physics, Eindhoven University of Technology, The Netherlands.
    3D-Morphology Reconstruction of Nanoscale Phase-Separation in Polymer Memory Blends2015In: Journal of Polymer Science Part B: Polymer Physics, ISSN 0887-6266, E-ISSN 1099-0488, Vol. 53, no 17, 1231-1237 p.Article in journal (Refereed)
    Abstract [en]

    In many organic electronic devices functionality is achieved by blending two or more materials, typically polymers or molecules, with distinctly different optical or electrical properties in a single film. The local scale morphology of such blends is vital for the device performance. Here, a simple approach to study the full 3D morphology of phase-separated blends, taking advantage of the possibility to selectively dissolve the different components is introduced. This method is applied in combination with AFM to investigate a blend of a semiconducting and ferroelectric polymer typically used as active layer in organic ferroelectric resistive switches. It is found that the blend consists of a ferroelectric matrix with three types of embedded semiconductor domains and a thin wetting layer at the bottom electrode. Statistical analysis of the obtained images excludes the presence of a fourth type of domains. The criteria for the applicability of the presented technique are discussed. (c) 2015 Wiley Periodicals, Inc.

  • 28.
    Fredriksson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.2007In: 2007 International Symposium on System-on-Chip.,2007, Tampere: Tampere University of Technology , 2007, 125- p.Conference paper (Refereed)
  • 29.
    Qureshi, Fahad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Alam, Syed Asad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    4-k point FFT algorithms based on optimized twiddle factor multiplication for FPGAs2010In: The Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, Sept. 22-24, 2010., 2010, 225-228 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

  • 30.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications2005In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05, 2005, I/127-I/130 p.Conference paper (Refereed)
    Abstract [en]

    The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

  • 31.
    Hossain, Mohammad Billal
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    6-9 GHz Low-Noise Amplifier Design and Implementation2010Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    Low-noise amplifier design (LNA) is a critical step when designing a receiver front- end. For the broadband technologies and particularly ultra-wideband (UWB) system, designing the LNA becomes more challenging. This master thesis mainly focuses on the LNA design for the European UWB recommendation, i.e. LNA covering the 6 - 9 GHz spectrum. Moreover, better understandings of the design process in correlation with the implementing of the LNA on a printed circuit board (PCB) were expected.

    The LNA was manufactured, assembled and measured with network analyzer. This report presents a complete functional design of an UWB LNA. 

  • 32.
    Al Faisal, Muhammad Saud
    Linköping University, Department of Science and Technology. Linköping University, The Institute of Technology.
    6-9 GHz UWB Antenna-Low-Noise Amplifier Co-design2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    6 - 9 GHz antenna-low-noise amplifier co-design is a demanding task. Higher frequency band has new techniques for circuit design and matching. The usual lumped component matching technique is not an appropriate solution for High Frequency (HF) broad band. The new broad band demands transmission line matching. The low-power and high-data rate Ultra Wide Band (UWB) uses large portion of the communication radio-spectrum and wireless communication. The principal axis of this thesis is co-design in the frequency band of 6 - 9 GHz. The thesis has been divided in two parts, where first part includes implementation and evaluation of individual RF-circuits of circular monopole antenna, a band pass (BP) filter and a low-noise amplifier (LNA), while second part unite all three RF circuits and presents the co-design.

    Microstrip monopole antennas get more and more popular due to rapid change in the wireless communication. Higher datarate and even higher bandwidth demands a simple and compact ultra-wideband (UWB) antenna. Two monopole antennas circular and rectangular monopole antennas were designed. Simulated and experimental results of modified design indicate that antenna was achieved a VSWR of 1.2, with input reflection less then - 10 dB in 4 - 12 GHz band. These characteristic make the designed antenna suitable for various UWB application.

     The broad band matching and the flat gain are the two important factors for the UWB circuits. The co-design of antenna-low-noise amplifier utilizes a inter stage matching technique with a simple band pass filter, a third-order passive Chebychev filter is proposed as an input matching network. The filter achieves forward transmission less the - 0.8 dB and a return loss - 20 dB in 6 - 9 GHz band.

    Low-noise amplifier is the key RF circuit; minimal Noise Figure (NF) and the lower power consumption are desired parameters. The implemented low-noise amplifier (LNA) is the combination of bias network and ultra-wide band radio frequency (RF) choke. AVAGO Technologies pseudmorphic-high-electron-mobility transistor (PHEMT) with (SC-70) plastic package with nominal 0.2 µm gate length is used in amplifier. Passive distributed components of microstrip transmission line were used for matching, simulated results demonstrate maximum power gain of 12.74 dB and minimum noise figure (NFmin) of 1 dB is obtained.

    Finally all three individual RF circuits antenna, filter and low-noise amplifier are integrated into co-design and analyzed for 6 - 9 GHz band. Later on two more new designs are added. This co-design has large potential in Direct-broadcast-satellite (DBS) TV system, X-band radar detector, automotive radar, remote sensors, and Multichannel-multipoint-distribution-systems (MMDS). 

  • 33.
    Säll, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    6-bit flash ADC with dynamic element matching2006In: Proc. IEEE 24th Norchip Conf., NORCHIP'06, 2006, , 159-162 p.159-162 p.Conference paper (Refereed)
    Abstract [en]

    Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter. The converter is sent for manufacturing in a 130 nm partially depleted silicon-on-insulator CMOS technology. It was simulated at transistor level in Cadence using the foundry provided BSIM3SOI Eldo models. These simulations yield a maximum sampling frequency of at least 350 MHz. The simulations also indicate a performance improvement in terms of spurious free dynamic range when using dynamic element matching.

  • 34.
    Kihlman, Henrik
    et al.
    Linköping University, Department of Mechanical Engineering. Linköping University, The Institute of Technology.
    Loser, Raimund
    Leica Geosystems AG.
    6DOF metrology-integrated robot control2003Conference paper (Refereed)
    Abstract [en]

    This paper describes ongoing research into Metrology-integrated robot control. The research is a part of an ongoing EU funded aircraft industry project – ADFAST*. The ADFAST project tries to implement the use of industrial robots in low-volume production, high-demand-on-accuracy operations and for dynamic force compensation. To detect and compensate deflection in industrial robots during a process, the robot uses a metrology system. The metrology system supervises the tool center point of the robot as it executes its processes. Leica has recently released a new metrology system; the LTD800, which measures distances with laser interferometry and can simultaneously measure orientation of targets, through photogrammetry, using an additional camera on top of the measuring unit. This paper will describe theory and results from tests performed on integrating the LTD800 with the robot.

  • 35.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 36.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition2012In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, 336-339 p.Conference paper (Refereed)
    Abstract [en]

    A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

  • 37.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, 28-38 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

  • 38.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, 2306-2310 p.Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 39.
    Angelov, Pavel
    et al.
    AnaCatum Design AB, S-58330 Linkoping, Sweden.
    Ahmed Aamir, Syed
    Heidelberg University, Germany.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, Vol. 61, no 11, 860-864 p.Article in journal (Refereed)
    Abstract [en]

    We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.

  • 40.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, 244-248 p.Article in journal (Refereed)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 41.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems., www.ieee.org , 2010, 29-32 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 42.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-Bit dual current-steering DAC2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper (Other academic)
    Abstract [en]

    A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

  • 43.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-transistor CMOS full adder with full voltage-swing nodes1999In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'99, 1999, 713-722 p.Conference paper (Refereed)
    Abstract [en]

    We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 μm process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder

  • 44.
    Hultman, Martin
    et al.
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    Fredriksson, Ingemar
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering. Perimed AB, Järfälla-Stockholm, Sweden.
    Larsson, Marcus
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Strömberg, Tomas
    Linköping University, Department of Biomedical Engineering, Division of Biomedical Engineering. Linköping University, Faculty of Science & Engineering.
    A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup2017In: Journal of Biophotonics, ISSN 1864-063X, E-ISSN 1864-0648Article in journal (Refereed)
    Abstract [en]

    A multiple exposure laser speckle contrast imaging (MELSCI) setup for visualizing blood perfusion was developed using a field programmable gate array (FPGA), connected to a 1000 frames per second (fps) 1-megapixel camera sensor. Multiple exposure time images at 1, 2, 4, 8, 16, 32 and 64 milliseconds were calculated by cumulative summation of 64 consecutive snapshot images. The local contrast was calculated for all exposure times using regions of 4 × 4 pixels. Averaging of multiple contrast images from the 64-millisecond acquisition was done to improve the signal-to-noise ratio. The results show that with an effective implementation of the algorithm on an FPGA, contrast images at all exposure times can be calculated in only 28 milliseconds. The algorithm was applied to data recorded during a 5 minutes finger occlusion. Expected contrast changes were found during occlusion and the following hyperemia in the occluded finger, while unprovoked fingers showed constant contrast during the experiment. The developed setup is capable of massive data processing on an FPGA that enables processing of MELSCI data in 15.6 fps (1000/64 milliseconds). It also leads to improved frame rates, enhanced image quality and enables the calculation of improved microcirculatory perfusion estimates compared to single exposure time systems.

    The full text will be freely available from 2018-08-07 12:43
  • 45.
    Ohlsson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 16 GSPS 0.18 µm CMOS decimator for single-bit ∑∆-modulation.2004In: Norchip,2004, Piscataway: IEEE Inc. , 2004, 175- p.Conference paper (Refereed)
  • 46.
    Säll, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A 1.8V 10-bit 80MS/s Low Power Track-and-Hold Circuit in a 0.18µm CMOS Process2003In: IEEE International Symposium on Circuits and Systems, ISCAS,2003, 2003Conference paper (Other academic)
    Abstract [en]

    A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18um CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the T&H circuit and the amplifier is a folded cascode OTA with gain boosting. This paper describes the design of the complete T&H, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.

  • 47.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOSManuscript (preprint) (Other academic)
  • 48.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS2006In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, 257-260 p.Conference paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

  • 49.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.5-GHz DLL-based multiphase clock generator in 90-nm CMOS.2008In: Swedish System-on-Chip Conference SSoCC.,2008, 2008Conference paper (Other academic)
  • 50.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s2013Conference paper (Other academic)
    Abstract [en]

    This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

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