In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 2(2ENOB), whereas the speed-bound increases by 2(ENOB-2) and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2(ENOB-1). The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, f(s)/2.

This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

Silicon photon-counting spectral detectors are candidates for the next generation of medical CT. For silicon detectors, a low noise floor is necessary to obtain good detection efficiency. A low noise floor can be obtained by having a slow shaping filter in the ASIC, but this leads to a long dead-time, thus decreasing the count-rate performance. In this work, we evaluate the benefit of utilizing two sub-channels with different shaping times. It is shown by simulation that utilizing a dual shaper can increase the dose efficiency for equal count-rate capability by up to 17%.

Disclosed is an x-ray detector system including a multitude of detector elements, each connected to a respective photon counting channel for providing at least one photon count output, and a read-out unit connected to the photon counting channels for outputting the photon count outputs. Each one of at least a subset of the photon counting channels includes at least two photon counting sub-channels, each photon counting sub-channel providing at least one photon count output and having a shaping filter, wherein the shaping filters of the photon counting sub-channels are configured with different shaping times, and wherein the photon counting sub-channels, having shaping filters with different shaping times, are adapted for counting photons of different energy levels. Furthermore, the read-out unit is configured to select, for each photon counting channel, photon count outputs from the photon counting sub-channels.

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This paper presents an implementation solution for a digital baseband receiver, which consists mainly of an analog symbol timing recovery (STR) block and a digital carrier recovery block. The STR is realized based on "one-sample-per-symbol" sampling, resulting in relaxed requirement on the A/D converters sampling speed. In this sense, the proposed implementation solution is hardware efficient. To functionally verify the solution, a proof-of-concept E-band link system is implemented and tested in the laboratory, which supports 5-Gbit/s data traffic using 16 quadrature amplitude modulation. The test results demonstrate that the proposed solution works for high-capacity millimeter-wave radios for point-to-point links, one of the targeted applications.

A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.

Power consumption of analog systems is poorly understoodtoday, in contrast to the very well developed analysis of digitalpower consumption. We show that there is good opportunity todevelop also the analog power understanding to a similar levelas the digital. Such an understanding will have a large impact inthe design of future electronic systems, where low power consumptionwill be crucial. Eventually we may reach a power centricanalog design methodology.

A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.