This paper presents a low-power, optical systemon-chip (SoC) enabling wireless fluorescence detection. The proposed SoC, in size of 2 x 2.7 mm², integrates a high-sensitivity optical front-end, battery management unit and energy harvesting, and a wireless data transceiver. A fast-settling transimpedance amplifier (TIA) ensures rapid startup and minimizes power consumption, supported by dual-mode low dropout regulators (LDO regulators) for efficient power management. The SoC achieves ultra-low power, 1 μW, operation with 0.5 pA sensitivity, suitable for non-invasive cellular monitoring. The SoC is implemented using 65 nm CMOS technology.

Backscatter (BackCom) communication using a cavity poses a significant challenge due to the bandpass filtering behavior of the cavity, which restricts the range of separation between uplink and downlink frequencies, potentially leading to self-jamming issues, requiring a high-sensitivity transceiver and a high quality-factor narrow-band filter. This paper proposes a new method for BackCom using a multimode rectangular cavity with dimensions of 49.6 cm × 49.6 cm × 30.4 cm, which resonates at 427.5 MHz in TE011 mode and 570 MHz in TM110 mode. A double-sided square loop coil, sized 1.2 mm × 1.2 mm on an FR4 substrate, serves as the miniaturized device (MD) antenna for freely moving small animal implants. The MD integrates an on-chip circuit implemented in a 0.35 μm CMOS technology, featuring a 5-stage differential rectifier with a power management unit and a low-power on-chip frequency generator. The frequency generator eliminates a power-hungry synthesizer by deriving the 142.5 MHz modulation signal from the 570 MHz downlink via frequency division. The multimode cavity as a reader receives an uplink signal of -20 dBm at 427.5 MHz in TE011 mode, with a downlink input power of 24 dBm at 570 MHz in TM110 mode applied to the cavity. This approach shows a sufficient separation of 142.5 MHz between the uplink and downlink modes, which eliminates self-jamming, relaxes filter requirements, and enables using the full cavity bandwidth for potentially higher data rates.

A comprehensive framework for designing a micro-nuclear magnetic resonance (NMR) front-end is presented. Key radio frequency (RF) engineering principles are established to enable efficient excitation and detection of NMR signals. This foundation aims to guide the optimal design of novel handheld NMR devices operating with magnetic fields (B0) below 0.5 Tesla and RF frequencies under 30 MHz. To address the complexities of signal-to-noise ratio optimization in this regime, a specialized metric called the coil performance factor (CPF) is introduced, emphasizing the role of coil design. Through systematic optimization under realistic constraints, an optimal coil configuration maximizing the CPF is identified. This design, with three turns, a coil width of 0.22 mm, and a coil spacing of 0.15 mm, achieves an optimal balance between magnetic field strength, homogeneity, and noise. This work serves as a valuable resource for engineers developing optimized coil designs and RF solutions for handheld NMR devices, providing clear explanations of essential concepts and a practical design methodology.

This paper investigates power amplifiers (PAs) for micro-nuclear magnetic resonance (NMR) applications, focusing on class-D and class-E topologies. Class-D is initially explored, offering advantages in integration due to its reduced component count. While class-E is known to surpass class-D in efficiency, it conventionally requires a significant number of passive components. To address this, an approach where the NMR coil itself is integrated as part of the class-E PA is proposed, eliminating the need for a separate matching network and resonator inductance. Both amplifier topologies were designed and simulated, delivering 450 mW of output power. Class-E demonstrated better efficiency, reaching approximately 66% compared to class-D’s 53% within the 21.3-63.9 MHz Larmour frequency range, corresponding to an external magnetic field of 0.5−1.5T suitable for micro-NMR. Additionally, a duty cycle controller was incorporated to enable flexible output power control for NMR experiments. This design allows class-E to achieve compactness comparable to class-D while maintaining its higher efficiency, making it a promising solution for micro-NMR applications.

This paper introduces a design methodology for optimizing a micro nuclear magnetic resonance (NMR) planar coil to ensure maximum signal-to-noise ratio (SNR) in NMR systems. Although the SNR is influenced by multiple factors, some remain nearly impossible to model and simulate using traditional electromagnetic simulators. To address this challenge, we propose the concept of the coil performance factor (CPF). The CPF exclusively considers coil-related parameters, such as magnetic flux density, inhomogeneity factor, coil temperature, and coil resistance. Utilizing this methodology, we evaluated multiple planar coils, each with varying turn numbers, trace widths, and shapes but maintaining a diameter consistent with the standard 5-mm NMR tubes, within an identical environment. Notably, unlike coils designed for other applications that prioritize high-quality factor (Q), NMR coils necessitate a balance between high homogeneity and other factors. Comparative analysis revealed that the optimized octagonal coil, comprising 3 turns and a 0.27 mm trace width, exhibited a CPF of 0.0214 millitesla per the square root of Kelvin ohms. In contrast, the high-Q coil demonstrated a CPF of 0.0102 millitesla per the square root of Kelvin ohms. Our findings underscore the potential of CPF as an insightful metric for micro-NMR planar coil design and optimization.

Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.