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Johansson, Håkan, ProfessorORCID iD iconorcid.org/0000-0001-6329-9132
Publications (10 of 182) Show all publications
Mondal, A., Mishra, D., Prasad, G. & Johansson, H. (2025). Joint Trajectory, User-Association, and Power Control for Green UAV-Assisted Data Collection Using Deep Reinforcement Learning. IEEE Transactions on Intelligent Vehicles, 10(1), 548-561
Open this publication in new window or tab >>Joint Trajectory, User-Association, and Power Control for Green UAV-Assisted Data Collection Using Deep Reinforcement Learning
2025 (English)In: IEEE Transactions on Intelligent Vehicles, ISSN 2379-8858, E-ISSN 2379-8904, Vol. 10, no 1, p. 548-561Article in journal (Refereed) Published
Abstract [en]

Because of the numerous benefits, unmanned aerial vehicles (UAVs) assist ground users in maintaining a satisfactory quality of service (QoS) even when they are far from terrestrial base stations (BSs) or outside the cellular coverage area. However, the limited energy capacity of UAVs restricts their operational duration. This study, therefore, investigates how to maximize energy efficiency (EE) in a UAV-enabled data collection system to prolong the network's lifespan, taking into account variations in UAV propulsion and data reception energy. The study focuses on optimizing user associations, their instantaneous transmit power allocation (PA), and UAV's trajectory while meeting users' minimum data rate requirements. This optimization problem is challenging due to its non-convex and combinatorial nature, making analytical solutions difficult. To address this, the study uses the Markov decision process (MDP) to split the problem into two sub-problems: user association with PA and UAV's optimal successive locations. These sub-problems are then solved alternately, first deriving optimal instantaneous transmit powers for each user analytically and then employing a deep reinforcement learning (DRL) framework based on the soft actor-critic (SAC) algorithm to acquire the UAV's optimal flying path. The proposed adaptive SAC algorithm allows the UAV to adjust its speed, heading direction, and altitude while efficiently shaping rewards to adhere to practical constraints. Numerical results validate the analysis and demonstrate significant improvements in total EE compared to benchmark deep deterministic policy gradient (DDPG), twin-delayed DDPG (TD3), and particle swarm optimization (PSO) techniques, with increases of 19.29%, 7.53%, and 53.96%, respectively.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-223165 (URN)10.1109/tiv.2024.3416067 (DOI)2-s2.0-85196749095 (Scopus ID)
Available from: 2026-04-21 Created: 2026-04-21 Last updated: 2026-06-12
Moryakova, O., Eriksson, T. & Johansson, H. (2025). Modeling, Analysis, and Optimization of Cascaded Power Amplifiers. In: 2025 33rd European Signal Processing Conference (EUSIPCO): . Paper presented at 2025 33rd European Signal Processing Conference (EUSIPCO) (pp. 2692-2696). European Association for Signal Processing (EURASIP)
Open this publication in new window or tab >>Modeling, Analysis, and Optimization of Cascaded Power Amplifiers
2025 (English)In: 2025 33rd European Signal Processing Conference (EUSIPCO), European Association for Signal Processing (EURASIP) , 2025, p. 2692-2696Conference paper, Published paper (Refereed)
Abstract [en]

This paper deals with modeling, analysis, and optimization of power amplifiers (PAs) placed in a cascaded structure, particularly the effect of cascaded nonlinearities is studied by showing potential ways to minimize the total nonlinearities. The nonlinear least-squares algorithm is proposed to optimize the PA parameters along with the input power level, and thereby minimize the total nonlinearities in the cascaded structure. The simulation results demonstrate that the performance of the optimized configurations for up to five PAs using the proposed framework can improve the linearity properties of the overall cascade.

Place, publisher, year, edition, pages
European Association for Signal Processing (EURASIP), 2025
Keywords
Power amplifier nonlinearity, Cascaded structure, Minimization of total nonlinearities, Nonlinear least-squares
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-222440 (URN)10.23919/EUSIPCO63237.2025.11226028 (DOI)9789464593624 (ISBN)9798350391831 (ISBN)
Conference
2025 33rd European Signal Processing Conference (EUSIPCO)
Available from: 2026-04-02 Created: 2026-04-02 Last updated: 2026-04-02Bibliographically approved
Rodríguez Linares, D. & Johansson, H. (2024). Digital Linearizer Based on 1-Bit Quantizations. In: 2024 IEEE 24th International Conference on Communication Technology (ICCT): . Paper presented at International Conference on Communication Technology (ICCT), Chengdu, China, 18-20 October 2024 (pp. 1659-1663). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Digital Linearizer Based on 1-Bit Quantizations
2024 (English)In: 2024 IEEE 24th International Conference on Communication Technology (ICCT), Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 1659-1663Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a novel low-complexity memoryless linearizer for suppression of distortion in analog frontends. It is based on our recently introduced linearizer which is inspired by neural networks, but with orders-of-magnitude lower complexity than conventional neural-networks considered in this context, and it can also outperform the conventional parallel memoryless Hammerstein linearizer. Further, it can be designed through matrix inversion and thereby the costly and time consuming numerical optimization traditionally used when training neural networks is avoided. The linearizer proposed in this paper is different in that it uses 1-bit quantizations as nonlinear activation functions and different bias values. These features enable a look-up table implementation which eliminates all but one of the multiplications and additions required for the linearization. Extensive simulations and comparisons are included in the paper, for distorted multi-tone signals and bandpass filtered white noise, which demonstrate the efficacy of the proposed linearizer.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Series
International Conference on Communication Technology (ICCT), ISSN 2576-7844, E-ISSN 2576-7828
Keywords
Training, Band-pass filters, Quantization (signal), Costs, Nonlinear distortion, Neural networks, White noise, Table lookup, Computational complexity, Optimization, Analog-to-digital interfaces, nonlinear distortion, memoryless linearizer, 1-bit quantization
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-213843 (URN)10.1109/ICCT62411.2024.10946352 (DOI)2-s2.0-105003156925 (Scopus ID)9798350363760 (ISBN)9798350363777 (ISBN)
Conference
International Conference on Communication Technology (ICCT), Chengdu, China, 18-20 October 2024
Projects
ELLIIT
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02
Available from: 2025-05-26 Created: 2025-05-26 Last updated: 2026-06-05Bibliographically approved
Moryakova, O. & Johansson, H. (2024). Efficient Design and Implementation of Fast-Convolution-Based Variable-Bandwidth Filters. In: Proceeeing of 32nd European Signal Processing Conference EUSIPCO 2024: . Paper presented at EUSIPCO 2024, 32nd European Signal Processing Conference, August 26-30 2024, Lyon, France (pp. 2557-2561). IEEE
Open this publication in new window or tab >>Efficient Design and Implementation of Fast-Convolution-Based Variable-Bandwidth Filters
2024 (English)In: Proceeeing of 32nd European Signal Processing Conference EUSIPCO 2024, IEEE , 2024, p. 2557-2561Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

This paper introduces an efficient design approach for a fast-convolution-based variable-bandwidth (VBW) filter. The proposed approach is based on a hybrid of frequency sampling and optimization (HFSO), that offers significant computational complexity reduction compared to existing solutions for a given performance. The paper provides a design procedure based on minimax optimization to obtain the minimum complexity of the overall filter. A design example includes a comparison of the proposed design-based VBW filter and time-domain designed VBW filters implemented in the time domain and in the frequency domain. It is shown that not only the implementation complexity can be reduced but also the design complexity by excluding any computations when the bandwidth of the filter is adjusted. Moreover, memory requirements are also decreased compared to the existing frequency-domain implementations. Index Terms—Variable bandwidth filter, fast convolution, frequency-domain design, time-varying systems, overlap-save, multirate filter banks.

Place, publisher, year, edition, pages
IEEE, 2024
Series
European Signal Processing Conference, ISSN 2076-1465
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-207039 (URN)001349787000511 ()9789464593617 (ISBN)
Conference
EUSIPCO 2024, 32nd European Signal Processing Conference, August 26-30 2024, Lyon, France
Available from: 2024-08-28 Created: 2024-08-28 Last updated: 2026-04-02Bibliographically approved
Moryakova, O. & Johansson, H. (2023). Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique. In: 2023 24th International Conference on Digital Signal Processing (DSP): . Paper presented at 24th International Conference on Digital Signal Processing (DSP), Rhodes, Greece, June 11-13, 2023. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

The paper introduces frequency-domain implementations of variable digital filters using the overlap-save method. Expressions for implementation and design complexities are derived for real-valued impulse responses. Design examples include implementations of a variable bandwidth (VBW) filter alone as well as a cascade of a VBW filter and a variable fractional delay(VFD) filter. Compared to a time-domain implementation and a filter bank approach, the proposed structures can reduce the implementation complexity significantly and achieve savings up to 95% in the multiplication rate and up to 89% in the addition rate.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
Keywords
Variable digital filter, frequency-domain implementations, implementation complexity, overlap-save
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201232 (URN)10.1109/DSP58604.2023.10167923 (DOI)2-s2.0-85165482542 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
24th International Conference on Digital Signal Processing (DSP), Rhodes, Greece, June 11-13, 2023
Available from: 2024-02-28 Created: 2024-02-28 Last updated: 2026-04-02Bibliographically approved
Rodríguez Linares, D. & Johansson, H. (2023). Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces. In: 2023 24th International Conference on Digital Signal Processing (DSP): . Paper presented at 2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a low-complexity memoryless linearizer for suppression of distortion in analog-to-digital interfaces. It is inspired by neural networks, but has a substantially lower complexity than the neural network schemes that have appeared earlier in the literature in this context. The paper demonstrates that the proposed linearizer can outperform the conventional parallel memoryless Hammerstein linearizer even when the nonlinearities have been generated through a memoryless polynomial model. Further, a design procedure is proposed in which the linearizer parameters are obtained through matrix inversion. Thereby, the costly and time consuming it- erative nonconvex optimization that is traditionally used when training neural networks is eliminated. Moreover, the design and evaluation incorporate a large set of multi-tone signals covering the first Nyquist band. Simulations show signal-to-noise-and-distortion ratio (SNDR) improvements of some 25 dB for multi-tone signals that correspond to the quadrature parts of OFDM signals with QPSK modulation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201140 (URN)10.1109/DSP58604.2023.10167765 (DOI)2-s2.0-85165488092 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02
Available from: 2024-02-23 Created: 2024-02-23 Last updated: 2026-03-19Bibliographically approved
Moryakova, O., Wang, Y. & Johansson, H. (2022). Reconfigurable FIR Lowpass Equalizers. In: 2022 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS): . Paper presented at 36th IEEE Workshop on Signal Processing Systems (SiPS), Rennes, FRANCE, nov 02-04, 2022 (pp. 114-119). IEEE
Open this publication in new window or tab >>Reconfigurable FIR Lowpass Equalizers
2022 (English)In: 2022 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), IEEE , 2022, p. 114-119Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces realizations of a reconfigurable finite-impulse-response (FIR) filter for simultaneous equalization and lowpass filtering. The proposed structures employ properties of both a variable bandwidth (VBW) filter and a variable equalizer (VE) with an adjustable coefficient using the Farrow structure, therefore they consist of weighted combinations of fixed subfilters. Design procedures using minimax optimization technique are provided. The paper includes a design example and complexity comparisons between the proposed structures of the reconfigurable lowpass equalizer (RLPE) and a common approach of using a regular FIR equalization filter requiring online redesign.

Place, publisher, year, edition, pages
IEEE, 2022
Series
IEEE Workshop on Signal Processing Systems, ISSN 1520-6130, E-ISSN 2374-7390
Keywords
Variable equalizer; variable bandwidth lowpass filter; Farrow structure; minimax optimization
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-198996 (URN)10.1109/SIPS55645.2022.9919214 (DOI)001081960800020 ()9781665485241 (ISBN)9781665485258 (ISBN)
Conference
36th IEEE Workshop on Signal Processing Systems (SiPS), Rennes, FRANCE, nov 02-04, 2022
Available from: 2023-11-07 Created: 2023-11-07 Last updated: 2024-12-03
Wang, Y., Liu, X., Johansson, H., Zhao, C., Chen, K. & Zhu, X. (2020). On first-order compensation of timing mismatch in two-channel TIADCs. In: 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, oct 10-21, 2020. IEEE
Open this publication in new window or tab >>On first-order compensation of timing mismatch in two-channel TIADCs
Show others...
2020 (English)In: 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2020Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, two first-order compensation strategies for timing mismatch in two-channel time-interleaved analog-to-digital converters (TIADCs) are analyzed, and expressions for the spurious-free dynamic range (SFDR) after compensation are derived. The derived expressions reveal that the strategy where both channels are compensated to match each other, using half the value of the mismatch with different signs, achieves a substantially greater SFDR than the strategy where only one channel is compensated to match the other (reference) channel. This is because, after compensation, the remaining aliasing distortion is shown to be of third order in the former strategy whereas it is of second order in the latter. Simulations included demonstrate the validity of the derived expressions.

Place, publisher, year, edition, pages
IEEE, 2020
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keywords
TIADCs; timing mismatch; compensation; undersampling
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-179878 (URN)10.1109/ISCAS45731.2020.9181227 (DOI)000706854700409 ()9781728133201 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, oct 10-21, 2020
Note

Funding: National Natural Science Foundation of ChinaNational Natural Science Foundation of China (NSFC) [61701509]; Science and Technology on Analog Integrated Circuit Laboratory [JCKY2019210C027]

Available from: 2021-10-04 Created: 2021-10-04 Last updated: 2021-11-17
Wang, Y., Johansson, H., Xu, H. & Diao, J. (2016). Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs. Analog Integrated Circuits and Signal Processing, 86(2), 275-288
Open this publication in new window or tab >>Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs
2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 2, p. 275-288Article in journal (Refereed) Published
Abstract [en]

In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper concentrates on a bandwidth-efficient background calibration method for nonlinear errors in M-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.

Place, publisher, year, edition, pages
SPRINGER, 2016
Keywords
Background Calibration; Bandwidth efficient; Nonlinear errors; M-channel; Time-interleaved ADCs
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-124626 (URN)10.1007/s10470-015-0677-x (DOI)000368182800012 ()
Available from: 2016-02-09 Created: 2016-02-08 Last updated: 2017-11-30
Wang, Y., Johansson, H. & Xu, H. (2015). Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs. IEEE Transactions on Circuits and Systems - II - Express Briefs, 62(3), 226-230
Open this publication in new window or tab >>Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 3, p. 226-230Article in journal (Refereed) Published
Abstract [en]

Due to channel mismatches in time-interleaved analog-to-digital converters (TIADCs), estimation and compensation methods are required to restore the resolution of the individual converters. Whereas several methods exist for linear mismatches, nonlinearity mismatches have not been widely investigated. This brief presents an adaptive background estimation method for nonlinearity mismatches in two-channel TIADCs. It utilizes a normalized least-mean-square algorithm and assumes slight oversampling as well as a polynomial nonlinearity model that is appropriate when smooth errors dominate. Furthermore, two implementation strategies are proposed to enhance its ability for different applications. The estimation performance of the proposed method is evaluated through behavioral-level simulations.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
Adaptive; analog-to-digital converter (ADC); background estimation; nonlinearity mismatches; polynomial models; time interleaving
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-116960 (URN)10.1109/TCSII.2014.2368976 (DOI)000350884900003 ()
Available from: 2015-04-10 Created: 2015-04-10 Last updated: 2017-12-04
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-6329-9132

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