Fiber-optic communication faces challenges to address impairment such as chromatic dispersion, which distorts signals, necessitating efficient chromatic dispersion compensation (CDC) solutions. In this work, architectural trade-offs when implementing finite-length impulse response (FIR) filters in the frequency-domain for high-speed CDC is presented. Most earlier works have considered a fully parallel FFT. However, as shown in this work, it is possible to reduce the power consumption by increasing the FFTs size, leading to time-multiplexed streaming FFT architectures. The results, implemented for a tentative 400G 16-QAM system, illustrates that traditionally used complexity measures, such as number of multiplications per sample, are not suitable when determining the best FFT size. It is also shown that this size is not necessarily a power of two. Instead, a ratio between the block length and the filter length of between one and two provides the best results in this case, lower than the commonly used multiplications per sample estimate. The results highlights the impact of the data shuffling, required for time-multiplexed FFTs, on the power consumption, but also the possibilities to lower the power consumption by not restricting to power-of-two FFTs.

Exact eight-bit floating-point multiplication performed using simple integer operations is considered in this work. For two-bit mantissa formats, correct rounding for all considered rounding modes can be obtained, either directly or by adding a conditional carry in. Using slightly more complicated expressions for the carry in, all rounding modes except directed modes can be obtained for three-bit mantissa formats. Hardware implementation results using both standard-cell and FPGA technology are presented, illustrating the potential benefit of integer computation. Savings in terms of resources and delay are obtained on both platforms, especially for the three-bit mantissa formats. The approach can also be attractive for platforms with integer vector instructions.

In this work, we present an investigation of the numerical properties of different symmetric matrix inversion algorithms, with a focus on two vector-based algorithms: Block LDLT and Tile LDLT. The inversion of symmetric positive-definite matrices finds applications in many different areas of signal processing, such as in MIMO detection and adaptive filtering. Using arithmetic simulations with the APyTypes Python software library, we demonstrate the numerical properties of different algorithms when using fixed-point number representations. The two algorithms in focus show potential, performing very close to the standard LDLT algorithm. The Tile LDLT algorithm slightly outperforms the Block LDLT algorithm in most cases, especially for larger matrix sizes. The application-specific hardware architecture for the two matrix inversion algorithms is only given at a high level, with the actual implementation left as future work.

Systolic arrays (SAs) for matrix multiplication are commonly used in machine learning (ML), wireless communication, and signal processing. Inherently offering high throughput with good data reuse, they are well-positioned for both low-power edge devices and accelerator applications in high-performance computing. Current realizations suffer from startup latency, defined as the time required to fully utilize all processing elements (PEs). In this work, this issue is addressed by introducing bidirectional systolic arrays with connected edges that form toroidal dataflows. The proposed systolic arrays significantly reduce computational and readout latency from 4n−2 to 2.5n−1 clock cycles for an n×n matrix multiplication, while simultaneously reducing energy per operation by up to 43% compared to conventional SAs. Moreover, a variety of differently shaped SAs are synthesized in a 22 nm CMOS technology, and it is shown that the toroidal designs offer a 5%−12% lower silicon area cost.

A new Python library, APyTypes, suitable for simulating and exploring finite word-length effects is presented. The library supports configurable bit-accurate fixed- and floating-point types of both scalars and multidimensional arrays and uses a C++ backend to accelerate runtime performance. The underlying design principles of the library are introduced and examples show how it can be used. We argue that APyTypes have significant advantages over existing arithmetic libraries, especially from a hardware design perspective. Finally, some directions for further work are outlined.

APyTypes is a new Python library, written in C++, that provides scalars and multi-dimensional arrays with configurable fixed- and floating-point representations. It is suitable for finite word-length design exploration and to provide reference data for custom hardware implementations.

A modern communication testbed based on distributed multiple-input multiple-output (MIMO) is constructed at Lund University. This testbed uses 16-antenna panels as a base for the distributed MIMO system. As the mixers in these panels are fully digital, there is a rational relationship between the sample frequency and the clock frequency of the field-programmable gate-array that performs the digital baseband processing. This rational relationship, combined with the multiple data streams in the panel, makes for an interesting design challenge when implementing high-utilization circuits. Three unique 16 multi-stream fast Fourier transform architectures tailored toward this particular distributed MIMO testbed are presented. The proposed architectures take the rational relationship between clock frequency and sample frequency into consideration and achieve 96.25%–100% butterfly utilization in the multi-streamFFT.

Spade is an HDL that enhances the productivity of HDL designers byadding useful abstractions for hardware design. These abstractionsare zero- or low-cost, meaning that the designer still has full controlover what hardware gets generated.

In this work, we analyze the step-size approximation for fixed-point least-mean-square (LMS) and block LMS (BLMS) algorithms. Our primary focus is on investigating how step size approximation impacts the convergence rate and steady-state mean square error (MSE) across varying block sizes and filter lengths. We consider three different FP quantized LMS and BLMS algorithms. The results demonstrate that the algorithm with two quantizers in single precision behaves approximately the same as one quantizer under quantized weights, regardless of block size and filter lengths. Subsequently, we explore the approximation effects of nearest power-of-two and their combinations with different design parameters on the convergence performance. Simulation results for within the context of a system identification problem under these approximations reveal intriguing insights. For instance, a single quantizer algorithm without quantized error is more robust than its counterpart under these approximations. Additionally, both single quantizer algorithms with combined power-of-two approximations matches the behavior of the actual step-size.

The time-to-market of a new product is one of its most crucial factors for success, therefore, reducing this time is of utter importance. However, this reduction must not come at the expense of a less thorough development process. This paper presents a compiler-driven approach for automatically analyzing metrics such as transaction delays or bus throughput on simulation waveforms of projects developed in the Spade Hardware Description Language (HDL). By utilizing the Spade compiler’s knowledge about design internals, an automatic analysis of the waveforms created during simulation is possible using the Waveform Analysis Language (WAL). Analysis programs can be bundled with Spade projects or libraries, such that they are automatically detected by Spade and can be reused by other projects using simple annotations. We call these bundled WAL programs analysis passes, since they fit into the Spade workflow and provide thorough analysis at no additional cost to the users of these libraries. In a detailed description, we present how new analysis passes can be defined using the example of a data streaming interface. Additionally, we highlight the possibilities of analysis passes in two case studies, including Finite State Machine (FSM) and Wishbone protocol analysis.