Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.

Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

This thesis describes some high-performance digital CMOS circuits and the design of these circuits.

The goal is to have a higher utilization of standard CMOS processes in order to increase performance of digital circuits. This is done without the use of aggressive processes. The designs are targeted towards very high clock rate and low power consumption.

At the high level, the design are adjusted to fit into a low level architecture optimized for high performance. The architecture is also optimized for the high level design. The logic style and the flip-flops are selected for high performance.

The digital processing chips presented in this thesis are based on a principle of heavily pipelined uni-directional processing in a data path. The logic is pipelined to a logic depth of one or two gates per pipeline stage. This design method and architecture is used for applications with high throughput processing of data.

Two chips are designed for processing of 10 Gb/s SDH (Synchronous Digital Hierarchy) data, for use in fiber optic transmission systems. They include processing for the framer and deframer functions of a SDH regenerator. The 10 Gb/s is internally processed with 16 bits in parallel at a clock rate of 622 MHz. The chips are implemented in standard 0.6-0.8 μm CMOS.

A quadrature 350 MHz Direct Digital Frequency Synthesizer is implemented in 0.8 μm CMOS. This DDFS is a high-speed compact implementation with on-chip DIA converters for the four-phase output. It calculates the sine and cosine values with a precision of 8 bits and with a frequency resolution below 1 Hz by using a sparse ROM-table and interpolation.

A correlator chip for satellite-based high-performance auto-correlator spectrometers is designed. This chip performs more than 0.5 Tera-Multiply and Accumulate operations per second at a speed of 320 MHz in 1664 multipliers and accumulators. This 58 mm² chip contains 1.6 million transistors and is implemented in a 0.6 μm process. The power consumption per operation is reduced with more than 5 times compared with other implementations, without any reduction in supply voltage. The internal noise level is reduced by dividing the processing and clock signal distribution into blocks with a clock buffer in between.

Finally, two different high-speed multiplexers are presented. A 2.4-Gb/s 4:1 multiplexer and a 4-Gb/s 2:1 multiplexer are implemented in 0.8 μm CMOS. Both multiplexers are designed to be clocked by an external high swing clock.

All chips results have been verified by measurements.