Fiber-optic communication faces challenges to address impairment such as chromatic dispersion, which distorts signals, necessitating efficient chromatic dispersion compensation (CDC) solutions. In this work, architectural trade-offs when implementing finite-length impulse response (FIR) filters in the frequency-domain for high-speed CDC is presented. Most earlier works have considered a fully parallel FFT. However, as shown in this work, it is possible to reduce the power consumption by increasing the FFTs size, leading to time-multiplexed streaming FFT architectures. The results, implemented for a tentative 400G 16-QAM system, illustrates that traditionally used complexity measures, such as number of multiplications per sample, are not suitable when determining the best FFT size. It is also shown that this size is not necessarily a power of two. Instead, a ratio between the block length and the filter length of between one and two provides the best results in this case, lower than the commonly used multiplications per sample estimate. The results highlights the impact of the data shuffling, required for time-multiplexed FFTs, on the power consumption, but also the possibilities to lower the power consumption by not restricting to power-of-two FFTs.

This thesis addresses the challenge of chromatic dispersion compensation (CDC) in coherent optical communication systems, focusing on high-speed, finite-length impulse response (FIR) filters. Chromatic dispersion, a significant limiting factor in long-distance, high data-rate fiber-optic networks, requires efficient filtering techniques to mitigate its impact on signal quality with low power dissipation. Although frequency-domain filtering has been well studied, most implementations have considered software for processor-based systems making them primarily suitable for off-line processing or limited data rates. High-speed real-time streaming implementations exist, but most only consider a small part of the available design space.

The primary contributions focus on design space exploration of frequency-domain FFT-based architectural approaches for CDC, considering both fully parallel and time-multiplexed configurations, implemented on FPGA and ASIC platforms. These designs, implemented for 16-QAM 60 GBaud systems, corresponding to 400 Gbps data rates, demonstrate an extended design space compared to earlier works. Especially, the FFT-length trade-off is considered, showing that estimates based on the number of multiplications are not fully relevant and that it is in general not possible to rely on only power-of-two-length FFTs. The results show that the extended design space provides better power efficiency. As part of the work, finite word-length effects are studied and novel blocks for performing overlap-save and overlap-add FFT-based filtering proposed.

Furthermore, a CDC filter design method for overlap-save processing that enhances filtering performance is proposed. Experimental results confirm that the proposed method significantly improves bit error rate (BER) performance without increasing latency or computational load when compared to optimal time-domain design.

The findings underscore the importance of optimizing both algorithmic and architectural aspects to optain energy efficient implementations of CDC filters in coherent optical communication systems. The presented works provide a scalable foundation for future high-speed, power-efficient static CDC.

FIR filtering realized in frequency domain can use different FFT sizes leading to different arithmetic complexities. The implementation results indicate that not only arithmetic complexities must be considered for minimal power consumption.

Approaches to shift-and-add realization of time-domain chromatic dispersion compensation FIR filters are considered. The coefficient word length has larger impact than filter length on both BER penalty and adder complexity.

Finite word length effects for frequency-domain implementation of chromatic dispersion compensation is analyzed. The results show a significant difference for the different factors when it comes to power consumption and receiver penalty.

Prime factor algorithms are beneficial in fully parallel frequency-domain implementation of CDC filters and enable a more continuous scaling of filter lengths. ASICimplementation results in 28-nm CMOS for 60 GBd are provided.